Path: chonsp.franklin.ch!not-for-mail
From: Neil Franklin <neil@franklin.ch.remove>
Newsgroups: comp.arch.fpga
Subject: VHDL vs Verilog
Date: 17 Oct 2000 22:57:42 +0200
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This is most likely newbie question no. <single-digit>.

In the various texts, posts here, listings of tools, etc I see
references to two languages: VHDL and Verilog. Both roughly the same
amount of references, so both seem to be widely used.

I assume these two to both be HDLs, just like there exist multiple
software programming languages (C, Fortran, Lisp, ...).

What are the differences? What the relative strenghts? What types of
jobs is one or the other best used for?

I know I could ask comp.lang.[vhdl|verilog], but I suspect the anser
there to be: ours is best. So what do you here on neutral ground think
of the two?


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, Mystic

######

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I don't think there is such a thing as neutral ground when it comes to that
subject.  It is more like religion.  That said, I use VHDL because it gives me
more control for getting the design to exactly what I want.  It is more verbose
than verilog, and can be more difficult to master (according to some).  However,
it has the controls I need to be able to do placement from within the code, and
use it as a generator as opposed to for synthesis.  As of last year, you
couldn't do everything I needed with verilog.

Outside of the US, VHDL is pretty much the standard.  In the US, verilog use is
fairly widespread, but then so is VHDL.  Comes down to what you are comforatble
with, and if it does what you need.

Neil Franklin wrote:
> 
> This is most likely newbie question no. <single-digit>.
> 
> In the various texts, posts here, listings of tools, etc I see
> references to two languages: VHDL and Verilog. Both roughly the same
> amount of references, so both seem to be widely used.
> 
> I assume these two to both be HDLs, just like there exist multiple
> software programming languages (C, Fortran, Lisp, ...).
> 
> What are the differences? What the relative strenghts? What types of
> jobs is one or the other best used for?
> 
> I know I could ask comp.lang.[vhdl|verilog], but I suspect the anser
> there to be: ours is best. So what do you here on neutral ground think
> of the two?
> 
> --
> Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
> Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, Mystic

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

######

From: Muzaffer Kal <muzaffer@dspia.com>
Newsgroups: comp.arch.fpga
Subject: Re: VHDL vs Verilog
Date: 17 Oct 2000 22:36:07 GMT
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Ray Andraka <ray@andraka.com> wrote:

>I don't think there is such a thing as neutral ground when it comes to that
>subject.  It is more like religion.  That said, I use VHDL because it gives me
>more control for getting the design to exactly what I want.  It is more verbose
>than verilog, and can be more difficult to master (according to some).  However,
>it has the controls I need to be able to do placement from within the code, and
>use it as a generator as opposed to for synthesis.  As of last year, you
>couldn't do everything I needed with verilog.

Ray,
would you like to expand little bit on what things VHDL does better
for you ? 

######

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From: Ray Andraka <ray@andraka.com>
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user attributes let me put INIT=, TNM, and RLOCs on instantiated primitives so I
can generate optimized macros that I know will do the logic the way I want it
everytime regardless of what the synthesizer wants to do.  Last I looked, there
was no way of doing that in Verilog.

Muzaffer Kal wrote:
> 
> Ray Andraka <ray@andraka.com> wrote:
> 
> >I don't think there is such a thing as neutral ground when it comes to that
> >subject.  It is more like religion.  That said, I use VHDL because it gives me
> >more control for getting the design to exactly what I want.  It is more verbose
> >than verilog, and can be more difficult to master (according to some).  However,
> >it has the controls I need to be able to do placement from within the code, and
> >use it as a generator as opposed to for synthesis.  As of last year, you
> >couldn't do everything I needed with verilog.
> 
> Ray,
> would you like to expand little bit on what things VHDL does better
> for you ?

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

######

From: Muzaffer Kal <muzaffer@dspia.com>
Newsgroups: comp.arch.fpga
Subject: Re: VHDL vs Verilog
Date: 18 Oct 2000 01:19:36 GMT
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Ray Andraka <ray@andraka.com> wrote:

>user attributes let me put INIT=, TNM, and RLOCs on instantiated primitives so I
>can generate optimized macros that I know will do the logic the way I want it
>everytime regardless of what the synthesizer wants to do.  Last I looked, there
>was no way of doing that in Verilog.

I think it would be synthesizer specific but I think you can do this
with xc_props and xc_rloc properties with Synplify.

Muzaffer
http://www.dspia.com

######

From: Kent Orthner <korthner@hotmail.nospam.com>
Newsgroups: comp.arch.fpga
Subject: Re: VHDL vs Verilog
Date: 18 Oct 2000 10:48:09 +0900
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Someone on one of these newsgroups had this to say about a month ago:

(Apologies for lack of reference, and probable misquote)

Verilog was written by hardware people with no real knowledge of how to 
write a programming language, and had to be banged around quite a 
bit before it was really useful.

VHDL was written by programming language peeople with no real 
knowledge of hardware, and had to be banged around quite a bit 
before it was really useful.

-Kent

######

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xc_rlocs doesn't work worth beans for synplicity VHDL.  Last year it wasn't
there for Verilog, but I have no confidence it would be any better. 
Nevertheless, with user attributes in VHDL, you've at least got a fighting
chance of it working with someone else's tools too.

Muzaffer Kal wrote:
> 
> Ray Andraka <ray@andraka.com> wrote:
> 
> >user attributes let me put INIT=, TNM, and RLOCs on instantiated primitives so I
> >can generate optimized macros that I know will do the logic the way I want it
> >everytime regardless of what the synthesizer wants to do.  Last I looked, there
> >was no way of doing that in Verilog.
> 
> I think it would be synthesizer specific but I think you can do this
> with xc_props and xc_rloc properties with Synplify.
> 
> Muzaffer
> http://www.dspia.com

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

######

From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Newsgroups: comp.arch.fpga
Subject: Re: VHDL vs Verilog
Date: Thu, 19 Oct 2000 13:26:09 -0700
Organization: National Optical Astronomy Observatory
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Muzaffer Kal wrote:
> 
> Ray Andraka <ray@andraka.com> wrote:
> 
> >I don't think there is such a thing as neutral ground when it comes to that
> >subject.  It is more like religion.  That said, I use VHDL because it gives me
> >more control for getting the design to exactly what I want.  It is more verbose
> >than verilog, and can be more difficult to master (according to some).  However,
> >it has the controls I need to be able to do placement from within the code, and
> >use it as a generator as opposed to for synthesis.  As of last year, you
> >couldn't do everything I needed with verilog.
> 
> Ray,
> would you like to expand little bit on what things VHDL does better
> for you ?

Here's my take on it.  I had a Verilog refresher yesterday.

VHDL forces you to think more about what you're trying to accomplish. 
It's verbose, but by being verbose, things are clearly specified.

Also, Verilog gives you enough rope to hang yourself.  For instance, it
allows you to connect things (vectors, ports, etc) with mismatched
sizes.  If the source port is narrower than the destination port, the
extra bits in the destination are filled with zeros.  If the source port
is wider than the destination, the extra bits are truncated!

VHDL, of course, says, "What are you, nuts?  Your ports must be the same
size."

I could go on, but I'm tired.  Software crash at the Los Angeles
flight-control center delayed my flight this morning.  They must have
been running Windows ME, or something.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

######

From: Brian Drummond <brian@shapes.demon.co.uk>
Newsgroups: comp.arch.fpga
Subject: Re: VHDL vs Verilog
Date: Fri, 20 Oct 2000 14:57:55 +0100
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On Thu, 19 Oct 2000 13:26:09 -0700, Andy Peters <"apeters <"@> n o a o
[.] e d u> wrote:

>Muzaffer Kal wrote:
>> 
>> Ray Andraka <ray@andraka.com> wrote:
>> 
>> >I don't think there is such a thing as neutral ground when it comes to that
>> >subject.  It is more like religion.  That said, I use VHDL because it gives me
>> >more control for getting the design to exactly what I want.  

>> Ray,
>> would you like to expand little bit on what things VHDL does better
>> for you ?
>
>Here's my take on it.  I had a Verilog refresher yesterday.
>
>VHDL forces you to think more about what you're trying to accomplish. 
>It's verbose, but by being verbose, things are clearly specified.
>
>Also, Verilog gives you enough rope to hang yourself.  For instance, it
>allows you to connect things (vectors, ports, etc) with mismatched
>sizes.  

Another way of looking at it; Verilog more closely resembles C, while
VHDL resembles academically designed programming languages like Modula-2
or Ada.

Verilog users prefer Verilog because of its resemblance to C; 
I prefer VHDL for precisely the same reason!

;-)

- Brian

######

From: erika_uk@my-deja.com
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Subject: Re: VHDL vs Verilog
Date: Sat, 21 Oct 2000 12:04:34 GMT
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could you do even FMAP.
do those attributes work with FPGA EXPRESS ?
In article <39ED0316.F754252C@andraka.com>,
  Ray Andraka <ray@andraka.com> wrote:
> xc_rlocs doesn't work worth beans for synplicity VHDL.  Last year it
wasn't
> there for Verilog, but I have no confidence it would be any better.
> Nevertheless, with user attributes in VHDL, you've at least got a
fighting
> chance of it working with someone else's tools too.
>
> Muzaffer Kal wrote:
> >
> > Ray Andraka <ray@andraka.com> wrote:
> >
> > >user attributes let me put INIT=, TNM, and RLOCs on instantiated
primitives so I
> > >can generate optimized macros that I know will do the logic the
way I want it
> > >everytime regardless of what the synthesizer wants to do.  Last I
looked, there
> > >was no way of doing that in Verilog.
> >
> > I think it would be synthesizer specific but I think you can do this
> > with xc_props and xc_rloc properties with Synplify.
> >
> > Muzaffer
> > http://www.dspia.com
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com
>


Sent via Deja.com http://www.deja.com/
Before you buy.

######

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Well...be careful there.  FMAP is a funny component.  If you have declare the
output as an output, the tools will complain that there are two nodes driving. 
If declaring it as an input, inout or buffer requires changing the primitive,
and I haven't had luck getting that modified primitive all the way through the
tools flow, at least not with synplicity.  Admittedly, I haven't pursued it much
since I got a working flow using the synplicity xc_fmap attribute.

erika_uk@my-deja.com wrote:
> 
> could you do even FMAP.
> do those attributes work with FPGA EXPRESS ?
> In article <39ED0316.F754252C@andraka.com>,
>   Ray Andraka <ray@andraka.com> wrote:
> > xc_rlocs doesn't work worth beans for synplicity VHDL.  Last year it
> wasn't
> > there for Verilog, but I have no confidence it would be any better.
> > Nevertheless, with user attributes in VHDL, you've at least got a
> fighting
> > chance of it working with someone else's tools too.
> >
> > Muzaffer Kal wrote:
> > >
> > > Ray Andraka <ray@andraka.com> wrote:
> > >
> > > >user attributes let me put INIT=, TNM, and RLOCs on instantiated
> primitives so I
> > > >can generate optimized macros that I know will do the logic the
> way I want it
> > > >everytime regardless of what the synthesizer wants to do.  Last I
> looked, there
> > > >was no way of doing that in Verilog.
> > >
> > > I think it would be synthesizer specific but I think you can do this
> > > with xc_props and xc_rloc properties with Synplify.
> > >
> > > Muzaffer
> > > http://www.dspia.com
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com  or http://www.fpga-guru.com
> >
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com