From: graham_moss@my-deja.com Newsgroups: comp.arch.fpga Subject: atmel verses altera Date: Thu, 28 Sep 2000 02:39:43 GMT Organization: Deja.com - Before you buy. Lines: 23 Message-ID: <8qub1g$3me$1@nnrp1.deja.com> NNTP-Posting-Host: 202.14.100.57 X-Article-Creation-Date: Thu Sep 28 02:39:43 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.0; Windows 98; DigExt; ICONZ IE5CD) X-Http-Proxy: 1.0 x62.deja.com:80 (Squid/1.1.22) for client 202.14.100.57 X-MyDeja-Info: XMYDJUIDgraham_moss Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!newsfeed.germany.net!fr.clara.net!small.fr.clara.net!news.tele.dk!144.212.100.101!newsfeed.mathworks.com!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:1418 Hello, My current project requires the use of a fpga to achieve all the associated logic functionality. Simply put the peripherals will communicate via a bus internal to the fpga, therefore the fpga will contains busses and muxes, registers (may use fpga ram), and contain some complex random logic and sequencers. I have investigated both the Atmel AT40 and the Altera Flex 10K family. This has left me confused as their architectures seem quite different, yet both could ultimately do the job. Have I missed the point? My question is how to determine which family will be better suited to my particular application. Any comments welcome! thanks, Graham Sent via Deja.com http://www.deja.com/ Before you buy. ###### From: "S. Ramirez" Newsgroups: comp.arch.fpga References: <8qub1g$3me$1@nnrp1.deja.com> Subject: Re: atmel verses altera Lines: 59 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Message-ID: Date: Thu, 28 Sep 2000 10:16:40 GMT NNTP-Posting-Host: 24.129.199.32 X-Complaints-To: abuse@rr.com X-Trace: typhoon.tampabay.rr.com 970136200 24.129.199.32 (Thu, 28 Sep 2000 06:16:40 EDT) NNTP-Posting-Date: Thu, 28 Sep 2000 06:16:40 EDT Organization: RoadRunner - Central Florida Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!pln-w!extra.newsguy.com!lotsanews.com!cyclone.tampabay.rr.com!typhoon.tampabay.rr.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:1451 Graham, What you are doing is very typical for an FPGA to handle. I have done what you are trying to do using both Altera 10K and Xilinx Virtex FPGAs. The Xilinx Spartan FPGAs will do, also. I had Atmel try to sell me on using their 6K family several years back. This was the family previous to the AT40. So I gave them the VHDL code and told them to place and route it in their part to see what kind of performance it would bring. I was looking for 36 MHz minimum performance, and I was achieving 42 MHz using the Xilinx 4KXL family. According to their sales pitch, they could run circles around Xilinx. But the proof is in the Putin, as they say in Russia. The local Atmel FAE guy squirmed when I asked him to fit the design into his super-fast Atmel FPGA. Actually, he squirmed, because he wasn't technically capable of doing it himself. So he had to ask the Atmel factory to do it. They did, and it came in at 27 MHz. After several episodes of the above, I think Atmel finally realized that the 6K family wasn't what it was cracked up to be. I was told that the AT40 family fixed a lot of the problems that the 6K family had. Nonetheless, I consider Atmel as following in the footsteps of the other FPGA vendors. So my advice is this. Given that there isn't much data on Atmel's AT40 family, why don't you ask the Atmel factory, or local FAE if he is up to it, to fit your design into one of their devices? You could also ask the other FPGA vendor to do the same and compare results. This sticking their feet to the fire approach does seem to weed out the misfits (no pun intended). Maybe someone in this newsgroup has extensive experience with the Atmel AT40 family, too. -Simon Ramirez, Consultant Synchronous Design, Inc. wrote in message news:8qub1g$3me$1@nnrp1.deja.com... > Hello, > My current project requires the use of a fpga to achieve all the > associated logic functionality. Simply put the peripherals will > communicate via a bus internal to the fpga, therefore the fpga will > contains busses and muxes, registers (may use fpga ram), and contain > some complex random logic and sequencers. > > I have investigated both the Atmel AT40 and the Altera Flex 10K family. > > This has left me confused as their architectures seem quite different, > yet both could ultimately do the job. > > Have I missed the point? My question is how to determine which family > will be better suited to my particular application. > > Any comments welcome! > > thanks, > Graham > > > Sent via Deja.com http://www.deja.com/ > Before you buy. > ###### From: "Ulf Samuelsson" Newsgroups: comp.arch.fpga References: <8qub1g$3me$1@nnrp1.deja.com> Subject: Re: atmel verses altera Lines: 46 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6600 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6600 Message-ID: NNTP-Posting-Host: 212.151.161.165 X-Complaints-To: news-abuse@swip.net X-Trace: nntpserver.swip.net 970233520 212.151.161.165 (Fri, 29 Sep 2000 15:18:40 MET DST) NNTP-Posting-Date: Fri, 29 Sep 2000 15:18:40 MET DST Organization: A Customer of Tele2 X-Sender: s-281058@d212-151-161-165.swipnet.se Date: Fri, 29 Sep 2000 13:38:17 +0200 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!informatik.tu-muenchen.de!news.informatik.uni-muenchen.de!uni-erlangen.de!newsfeeds.belnet.be!news.belnet.be!skynet.be!newspeer.clara.net!news.clara.net!newsfeed1.swip.net!swipnet!nntpserver.swip.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:1443 wrote in message news:8qub1g$3me$1@nnrp1.deja.com... > Hello, > My current project requires the use of a fpga to achieve all the > associated logic functionality. Simply put the peripherals will > communicate via a bus internal to the fpga, therefore the fpga will > contains busses and muxes, registers (may use fpga ram), and contain > some complex random logic and sequencers. > > I have investigated both the Atmel AT40 and the Altera Flex 10K family. > > This has left me confused as their architectures seem quite different, > yet both could ultimately do the job. > > Have I missed the point? My question is how to determine which family > will be better suited to my particular application. You need to specify your needs. Key to efficient use of the AT40K is to use the SRAM. SRAM can be used to implement logic in many different ways. If you have a design, which has some volume, Atmel can certainly Place and Route it for you. Send a mail to fpga@atmel.com and ask the question. Otherwise you can get the toolset for free at the Atmel website, do a P&R. The toolset supports timing analysis so you can find out if you will meet timing spec. If you need a controller in the design, then the new FPSLIC may be of interest to you. AVR RISC+ memory + 40K gates FPGA. -- Best regards, ulf at atmel dot com The contents of this message is intended to be my private opinion and may or may not be shared by my employer Atmel Sweden ###### Message-ID: <39D65138.D29662B2@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.73 [en] (WinNT; I) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: atmel verses altera References: <8qub1g$3me$1@nnrp1.deja.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 53 Date: Sat, 30 Sep 2000 20:47:56 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@home.net X-Trace: news1.wwck1.ri.home.com 970346876 24.13.238.93 (Sat, 30 Sep 2000 13:47:56 PDT) NNTP-Posting-Date: Sat, 30 Sep 2000 13:47:56 PDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news-stu1.dfn.de!news-mue1.dfn.de!news-nue1.dfn.de!uni-erlangen.de!newsfeeds.belnet.be!news.belnet.be!newsfeed.direct.ca!look.ca!newshub2.rdc1.sfba.home.com!news.home.com!news1.wwck1.ri.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:1476 The Achilles heel of the Atmel architecture, IMHO is that it does not have a fast carry chain. As a result, Altera and Xilinx implementations will run circles around anything done in Atmel for arithmetically heavy applications (that includes binary counters, folks!). If you can manage without carry chains, the parts are closer to equal, although Atmel does have the best partial reconfiguration out there right now. Ulf Samuelsson wrote: > > wrote in message > news:8qub1g$3me$1@nnrp1.deja.com... > > Hello, > > My current project requires the use of a fpga to achieve all the > > associated logic functionality. Simply put the peripherals will > > communicate via a bus internal to the fpga, therefore the fpga will > > contains busses and muxes, registers (may use fpga ram), and contain > > some complex random logic and sequencers. > > > > I have investigated both the Atmel AT40 and the Altera Flex 10K family. > > > > This has left me confused as their architectures seem quite different, > > yet both could ultimately do the job. > > > > Have I missed the point? My question is how to determine which family > > will be better suited to my particular application. > > You need to specify your needs. > Key to efficient use of the AT40K is to use the SRAM. > SRAM can be used to implement logic in many different ways. > > If you have a design, which has some volume, Atmel can certainly > Place and Route it for you. Send a mail to fpga@atmel.com and ask the > question. > > Otherwise you can get the toolset for free at the Atmel website, do a P&R. > The toolset supports timing analysis so you can find out if you > will meet timing spec. > > If you need a controller in the design, then the new FPSLIC may > be of interest to you. AVR RISC+ memory + 40K gates FPGA. > > -- > Best regards, > ulf at atmel dot com > The contents of this message is intended to be my private opinion and > may or may not be shared by my employer Atmel Sweden -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: atmel verses altera Date: Sat, 30 Sep 2000 18:58:56 -0400 Lines: 63 Message-ID: <39D67030.B426042E@yahoo.com> References: <8qub1g$3me$1@nnrp1.deja.com> <39D65138.D29662B2@andraka.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: JwIvrU95LIS2Ux18v9P1gFjvg+q3UL6LOEPIw0KhHnY= X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 30 Sep 2000 22:58:11 GMT X-Accept-Language: en X-Mailer: Mozilla 4.7 [en] (Win95; U) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!psinet-eu-nl!newsfeeds.belnet.be!news.belnet.be!xfer13.netnews.com!netnews.com!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:1497 I was looking at an Atmel FPSLIC ad today and it made me think about how it might let me put one chip on my board instead of four. I use four FPGAs for two reasons. One is that I need a total of about 350 IOs for the whole board. But the real reason is that at least two sections of the FPGA design are used as interface to add on daughter cards (AIO modules). When the AIO module is detected at boot up, the appropriate FPGA design is loaded to drive the module. This saves hardware on the modules and (theoretically) saves me money. The problem is that I have to use two separate chips for the AIO interfaces in addition to the main FPGA for the central board control. I am expecting to split the main FPGA in two because there is also some other board IO that I would like to make reconfigurable. If I could get one large FPGA with in circuit, partial reconfigurability, I could replace four parts with one or two. But looking at web pricing for the Atmel parts, it seems that it would still cost me more for one or two AT40K parts than it does for four Lucent or Xilinx parts. That still leaves the issue of how well Atmel supports partial reconfiguration, both in the design stage and in the reconfiguration stage. Anyone using these parts in a partial reconfiguration application? Ray Andraka wrote: > > The Achilles heel of the Atmel architecture, IMHO is that it does not have a > fast carry chain. As a result, Altera and Xilinx implementations will run > circles around anything done in Atmel for arithmetically heavy applications > (that includes binary counters, folks!). If you can manage without carry > chains, the parts are closer to equal, although Atmel does have the best partial > reconfiguration out there right now. > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.com -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com ###### Message-ID: <39D68F16.21B13DC0@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.73 [en] (WinNT; I) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: atmel verses altera References: <8qub1g$3me$1@nnrp1.deja.com> <39D65138.D29662B2@andraka.com> <39D67030.B426042E@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 80 Date: Sun, 01 Oct 2000 01:11:54 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@home.net X-Trace: news1.wwck1.ri.home.com 970362714 24.13.238.93 (Sat, 30 Sep 2000 18:11:54 PDT) NNTP-Posting-Date: Sat, 30 Sep 2000 18:11:54 PDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feeder.via.net!newshub2.rdc1.sfba.home.com!news.home.com!news1.wwck1.ri.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:1479 Atmel's device handles partial reconfig really nicely. A reconfiguration can be specified for any rectangular area down to a 1x1 cell area, which means you can reconfigure just what you want, not a whole column like virtex. Atmel has some tools for using reconfiguration for changing constants, and they may have added more since I last played with it. The toolset and silicon (as of over 2 years ago) is more friendly to partial configuration than any of the xilinx tools/silicon up to v3.1. That said, the device weaknesses in arithmetic applications may make it a non-contender for your application anyway. Nobody really has suitable tools yet for handling all the intricacies of partial reconfiguration correctly (especially if it is to be done while the application clock is running). rickman wrote: > > I was looking at an Atmel FPSLIC ad today and it made me think about how > it might let me put one chip on my board instead of four. I use four > FPGAs for two reasons. One is that I need a total of about 350 IOs for > the whole board. But the real reason is that at least two sections of > the FPGA design are used as interface to add on daughter cards (AIO > modules). When the AIO module is detected at boot up, the appropriate > FPGA design is loaded to drive the module. This saves hardware on the > modules and (theoretically) saves me money. > > The problem is that I have to use two separate chips for the AIO > interfaces in addition to the main FPGA for the central board control. I > am expecting to split the main FPGA in two because there is also some > other board IO that I would like to make reconfigurable. > > If I could get one large FPGA with in circuit, partial > reconfigurability, I could replace four parts with one or two. But > looking at web pricing for the Atmel parts, it seems that it would still > cost me more for one or two AT40K parts than it does for four Lucent or > Xilinx parts. > > That still leaves the issue of how well Atmel supports partial > reconfiguration, both in the design stage and in the reconfiguration > stage. Anyone using these parts in a partial reconfiguration > application? > > Ray Andraka wrote: > > > > The Achilles heel of the Atmel architecture, IMHO is that it does not have a > > fast carry chain. As a result, Altera and Xilinx implementations will run > > circles around anything done in Atmel for arithmetically heavy applications > > (that includes binary counters, folks!). If you can manage without carry > > chains, the parts are closer to equal, although Atmel does have the best partial > > reconfiguration out there right now. > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com or http://www.fpga-guru.com > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: atmel verses altera Date: Sat, 30 Sep 2000 21:53:53 -0400 Lines: 122 Message-ID: <39D69931.7C44C1D6@yahoo.com> References: <8qub1g$3me$1@nnrp1.deja.com> <39D65138.D29662B2@andraka.com> <39D67030.B426042E@yahoo.com> <39D68F16.21B13DC0@andraka.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: G6F4FqINIpV94dhq2nuF9BfAYw/+i6bsp2TqCwJDX6A= X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 1 Oct 2000 01:53:07 GMT X-Accept-Language: en X-Mailer: Mozilla 4.7 [en] (Win95; U) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.nextra.ch!news1.sunrise.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:1498 Actually, I guess I was wrong about needing to partial configure the part while running. With my current multichip design, I have to have the main FPGA running to talk to the rest of the board. But with an all in one chip approach, I can configure in sections in a complete reload of the FPGA. I do still need partial configuration so that I can separately develop and select the four sections of the chip. But I don't see where there is much support for the design side of things. But I have not looked at their tools. As you say, the chips are not the best architecture for many applications. And the cost is a significant issue as well. Do you have any idea how fast a 16 bit counter might run in a -1 part? I have not seen any info on this even in marketing material. In fact, the AT40K40AL does not even have a data sheet on the Atmel web site. But it is listed for sale at the Marshall web site. Ray Andraka wrote: > > Atmel's device handles partial reconfig really nicely. A reconfiguration can be > specified for any rectangular area down to a 1x1 cell area, which means you can > reconfigure just what you want, not a whole column like virtex. Atmel has some > tools for using reconfiguration for changing constants, and they may have added > more since I last played with it. The toolset and silicon (as of over 2 years > ago) is more friendly to partial configuration than any of the xilinx > tools/silicon up to v3.1. That said, the device weaknesses in arithmetic > applications may make it a non-contender for your application anyway. Nobody > really has suitable tools yet for handling all the intricacies of partial > reconfiguration correctly (especially if it is to be done while the application > clock is running). > > rickman wrote: > > > > I was looking at an Atmel FPSLIC ad today and it made me think about how > > it might let me put one chip on my board instead of four. I use four > > FPGAs for two reasons. One is that I need a total of about 350 IOs for > > the whole board. But the real reason is that at least two sections of > > the FPGA design are used as interface to add on daughter cards (AIO > > modules). When the AIO module is detected at boot up, the appropriate > > FPGA design is loaded to drive the module. This saves hardware on the > > modules and (theoretically) saves me money. > > > > The problem is that I have to use two separate chips for the AIO > > interfaces in addition to the main FPGA for the central board control. I > > am expecting to split the main FPGA in two because there is also some > > other board IO that I would like to make reconfigurable. > > > > If I could get one large FPGA with in circuit, partial > > reconfigurability, I could replace four parts with one or two. But > > looking at web pricing for the Atmel parts, it seems that it would still > > cost me more for one or two AT40K parts than it does for four Lucent or > > Xilinx parts. > > > > That still leaves the issue of how well Atmel supports partial > > reconfiguration, both in the design stage and in the reconfiguration > > stage. Anyone using these parts in a partial reconfiguration > > application? > > > > Ray Andraka wrote: > > > > > > The Achilles heel of the Atmel architecture, IMHO is that it does not have a > > > fast carry chain. As a result, Altera and Xilinx implementations will run > > > circles around anything done in Atmel for arithmetically heavy applications > > > (that includes binary counters, folks!). If you can manage without carry > > > chains, the parts are closer to equal, although Atmel does have the best partial > > > reconfiguration out there right now. > > > -- > > > -Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com or http://www.fpga-guru.com > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design > > > > Arius > > 4 King Ave > > Frederick, MD 21701-3110 > > 301-682-7772 Voice > > 301-682-7666 FAX > > > > Internet URL http://www.arius.com > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.com -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com ###### Message-ID: <39D6B602.20ED0AEC@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.73 [en] (WinNT; I) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: atmel verses altera References: <8qub1g$3me$1@nnrp1.deja.com> <39D65138.D29662B2@andraka.com> <39D67030.B426042E@yahoo.com> <39D68F16.21B13DC0@andraka.com> <39D69931.7C44C1D6@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 149 Date: Sun, 01 Oct 2000 03:57:58 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@home.net X-Trace: news1.wwck1.ri.home.com 970372678 24.13.238.93 (Sat, 30 Sep 2000 20:57:58 PDT) NNTP-Posting-Date: Sat, 30 Sep 2000 20:57:58 PDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.nextra.ch!news1.sunrise.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newshub2.home.com!news.home.com!news1.wwck1.ri.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:1481 No, last time I played with them the -2 part was all there was. IIRC, a 16 bit counter implemented as a sync. counter with a straight ripple carry chain was on the order of about 60 MHz. I seem to remember it taking about a ns per bit for the carry to propagate in the -2 parts. If there is a cell to cell timing in the data sheet, multiply that times the bits. I suspect they won't outright advertise a 16 bit counter performance because it doesn't compare very nicely with the chips that have a carry chain. The Atmel device really requires alot of the skills we used in the Xilinx 3K series when there was no carry chain. For example, using an LFSR for the count if at all possible. The 40K will work nicely in bit serial applications, but even there the more recent A and X parts will be faster. In just about any other application, you are giving up alot to have the partial reconfigurability. When the 40K came out (just before Xilinx announced the first spartan parts) it was targeted as a socket compatible xilinx replacement for the 4K parts, at what was to be a substantially lower price ($40 or so). The introduction of the spartan parts eliminated that, and the fact they overlooked the carry chain really limited the application. Since then, xilinx parts prices have dropped considerably, leaving the AT40K as a less capable, slower and now more expensive device compared to equivalent density Xilinx devices. Its a shame they left out the carry chain. It would have been a nice part with it. rickman wrote: > > Actually, I guess I was wrong about needing to partial configure the > part while running. With my current multichip design, I have to have the > main FPGA running to talk to the rest of the board. But with an all in > one chip approach, I can configure in sections in a complete reload of > the FPGA. I do still need partial configuration so that I can separately > develop and select the four sections of the chip. > > But I don't see where there is much support for the design side of > things. But I have not looked at their tools. As you say, the chips are > not the best architecture for many applications. And the cost is a > significant issue as well. > > Do you have any idea how fast a 16 bit counter might run in a -1 part? I > have not seen any info on this even in marketing material. In fact, the > AT40K40AL does not even have a data sheet on the Atmel web site. But it > is listed for sale at the Marshall web site. > > Ray Andraka wrote: > > > > Atmel's device handles partial reconfig really nicely. A reconfiguration can be > > specified for any rectangular area down to a 1x1 cell area, which means you can > > reconfigure just what you want, not a whole column like virtex. Atmel has some > > tools for using reconfiguration for changing constants, and they may have added > > more since I last played with it. The toolset and silicon (as of over 2 years > > ago) is more friendly to partial configuration than any of the xilinx > > tools/silicon up to v3.1. That said, the device weaknesses in arithmetic > > applications may make it a non-contender for your application anyway. Nobody > > really has suitable tools yet for handling all the intricacies of partial > > reconfiguration correctly (especially if it is to be done while the application > > clock is running). > > > > rickman wrote: > > > > > > I was looking at an Atmel FPSLIC ad today and it made me think about how > > > it might let me put one chip on my board instead of four. I use four > > > FPGAs for two reasons. One is that I need a total of about 350 IOs for > > > the whole board. But the real reason is that at least two sections of > > > the FPGA design are used as interface to add on daughter cards (AIO > > > modules). When the AIO module is detected at boot up, the appropriate > > > FPGA design is loaded to drive the module. This saves hardware on the > > > modules and (theoretically) saves me money. > > > > > > The problem is that I have to use two separate chips for the AIO > > > interfaces in addition to the main FPGA for the central board control. I > > > am expecting to split the main FPGA in two because there is also some > > > other board IO that I would like to make reconfigurable. > > > > > > If I could get one large FPGA with in circuit, partial > > > reconfigurability, I could replace four parts with one or two. But > > > looking at web pricing for the Atmel parts, it seems that it would still > > > cost me more for one or two AT40K parts than it does for four Lucent or > > > Xilinx parts. > > > > > > That still leaves the issue of how well Atmel supports partial > > > reconfiguration, both in the design stage and in the reconfiguration > > > stage. Anyone using these parts in a partial reconfiguration > > > application? > > > > > > Ray Andraka wrote: > > > > > > > > The Achilles heel of the Atmel architecture, IMHO is that it does not have a > > > > fast carry chain. As a result, Altera and Xilinx implementations will run > > > > circles around anything done in Atmel for arithmetically heavy applications > > > > (that includes binary counters, folks!). If you can manage without carry > > > > chains, the parts are closer to equal, although Atmel does have the best partial > > > > reconfiguration out there right now. > > > > -- > > > > -Ray Andraka, P.E. > > > > President, the Andraka Consulting Group, Inc. > > > > 401/884-7930 Fax 401/884-7950 > > > > email ray@andraka.com > > > > http://www.andraka.com or http://www.fpga-guru.com > > > > > > -- > > > > > > Rick "rickman" Collins > > > > > > rick.collins@XYarius.com > > > > > > Ignore the reply address. To email me use the above address with the XY > > > removed. > > > > > > Arius - A Signal Processing Solutions Company > > > Specializing in DSP and FPGA design > > > > > > Arius > > > 4 King Ave > > > Frederick, MD 21701-3110 > > > 301-682-7772 Voice > > > 301-682-7666 FAX > > > > > > Internet URL http://www.arius.com > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com or http://www.fpga-guru.com > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com