Message-ID: <39C46A24.79CA504@earthlink.net> From: Bill Lenihan Reply-To: lenihan3weNOSPAM@earthlink.net X-Mailer: Mozilla 4.7 [en] (Win98; I) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: virtex shape References: <8pgrq7$83f$1@nnrp1.deja.com> <8po684$pqo$1@nnrp1.deja.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 22 Date: Sun, 17 Sep 2000 06:51:10 GMT NNTP-Posting-Host: 209.178.177.82 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 969173470 209.178.177.82 (Sat, 16 Sep 2000 23:51:10 PDT) NNTP-Posting-Date: Sat, 16 Sep 2000 23:51:10 PDT Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!newsfeed.germany.net!blackbush.xlink.net!npeer.kpnqwest.net!news-peer.gip.net!news.gsl.net!gip.net!cyclone2.usenetserver.com!news-out.usenetserver.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:1216 Might have something to do with the relative (a)symetry of carry logic [in the vertical columns] and tri-state lines [in the horizontal rows] or something else to do with their overall routing scheme. husby@my-deja.com wrote: > erika_uk@my-deja.com wrote: > > why virtex chips are rectangular and not square > > My guess is because the BlockRam takes up several columns > which, if filled with CLBs would make it square. > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- ============================== William Lenihan lenihan3weNOSPAM@earthlink.net ============================== ###### From: "John L. Smith" Newsgroups: comp.arch.fpga Subject: Re: virtex shape Date: Sun, 17 Sep 2000 20:04:54 -0700 Organization: Visicom Imaging Products Lines: 60 Message-ID: <39C58656.74D0EED7@visicom.com> References: <8pgrq7$83f$1@nnrp1.deja.com> <8po684$pqo$1@nnrp1.deja.com> <39C46A24.79CA504@earthlink.net> Reply-To: jsmith@visicom.com NNTP-Posting-Host: cassandra.vigra.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------CEFFA3346C3F66A14102E20A" X-Mailer: Mozilla 4.7 [en] (Win95; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!newsfeed.germany.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!newsfeed.icl.net!netnews.com!howland.erols.net!nntp.flash.net!mercury.cts.com!newsfeed.cts.com!cheetah.visicom.com!usenet Xref: chonsp.franklin.ch comp.arch.fpga:1198 This is a multi-part message in MIME format. --------------CEFFA3346C3F66A14102E20A Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit > > erika_uk@my-deja.com wrote: > > > why virtex chips are rectangular and not square Why not? Seriously, is there an inherent advantage to the square for tiling the design space or the wafer? ( I used to wonder why the chips were not triangular or hexagonal.) In my work, the rectangle is probably a better shape. We do image processing, and since the parts still don't have enough internal ram for a complete frame buffer, we need to hang external banks of memory. If the processing is viewed as a pipeline, where the FPGA resident stuff is on top, and RAM storage is below: in-->( per/pixel ) ( warping ) ( Feature ) ( processing ) ( ) ( Extraction ) --> out | / \ | / \ | | | | \ / | \ / | [ Frame Store 1] [ Frame Store 2 ] (this is not a real application here, just to illustrate!) The rectangle is a more natural ( form-fitting) container for pipelined processes. Think of extending/enlarging the pipeline...with a rectangle, I/O never gets too far from the center(line), and I/O grows almost proportional to chip area. With a square, I/O grows proportional only to square root of chip area, and the center continually gets farther from the I/O. --------------CEFFA3346C3F66A14102E20A Content-Type: text/x-vcard; charset=us-ascii; name="jsmith.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for John L. Smith Content-Disposition: attachment; filename="jsmith.vcf" begin:vcard n:Smith;John L. tel;work:858-320-4102 x-mozilla-html:FALSE url:http://www.visicom.com org:Visicom;Imaging Products adr:;;10052 Mesa Ridge Court;San Diego;CA;92121;USA version:2.1 email;internet:jsmith@visicom.com title:Principal Engineer x-mozilla-cpt:;30864 fn:John L. Smith end:vcard --------------CEFFA3346C3F66A14102E20A-- ###### From: nweaver@boom.CS.Berkeley.EDU (Nicholas C. Weaver) Newsgroups: comp.arch.fpga Subject: Re: virtex shape Date: 18 Sep 2000 03:24:49 GMT Organization: University of California, Berkeley Lines: 11 Message-ID: <8q41u1$b20$1@agate.berkeley.edu> References: <8pgrq7$83f$1@nnrp1.deja.com> <8po684$pqo$1@nnrp1.deja.com> <39C46A24.79CA504@earthlink.net> NNTP-Posting-Host: boom.cs.berkeley.edu X-Trace: agate.berkeley.edu 969247489 11328 128.32.131.183 (18 Sep 2000 03:24:49 GMT) X-Complaints-To: abuse@berkeley.edu NNTP-Posting-Date: 18 Sep 2000 03:24:49 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.nextra.ch!news1.sunrise.ch!news.imp.ch!unlisys!news.snafu.de!news.tele.dk!128.32.206.55!newsfeed.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!nweaver Xref: chonsp.franklin.ch comp.arch.fpga:1243 Looking at the V2000E, (80 x 120 array), the amount of actual area taken up by the BlockRAMs is pretty mild, definatly not the 30% required to skew things. I suspect it is just how it is layed out, combined with some asymetries in the routing (the clock lines are vertically arranged). The resulting die is square. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: virtex shape Date: Tue, 19 Sep 2000 16:27:36 -0700 Organization: Xilinx Lines: 23 Message-ID: <39C7F667.278B32B9@xilinx.com> References: <8pgrq7$83f$1@nnrp1.deja.com> <8po684$pqo$1@nnrp1.deja.com> <39C46A24.79CA504@earthlink.net> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; I; PPC) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!psinet-eu-nl!newsfeeds.belnet.be!news.belnet.be!xfer13.netnews.com!netnews.com!news-feed.fnsi.net!news.idt.net!attmtf.ip.att.net!attla2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:1166 There was some speculation about the Virtex shape. Here are the facts: Physically, most Xilinx chips are close to square, a shape that is desirable for fitting them into a package. Physically, the Virtex CLB has a rectangular shape, it is roughly 50% higher than it is wide. That's why there are 50% more columns than rows. ( Assuming the conventional view of vertical columns and horizontal rows. ) Each BlockRAM has a height of four CLBs and a width of about 2.5 CLBs. So the BlockRAM area is equivalent to the area of about 10 CLBs. If you do the math, the chip size ends up almost square, but XCV405E and XCV812E with their huge number of BlockRAMs are oblong. Remember also that a Virtex CLB has four LUTs and flip-flops, while Spartan, XC4000 and XC3000 have only two LUTs in their CLB. Just to satisfy the curiosity... Peter Alfke, Xilinx Applications