From: "S. Ramirez" Newsgroups: comp.arch.fpga Subject: Spartan II vs. Virtex Lines: 9 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Message-ID: <3uUq5.2462$_8.341101@typhoon.tampabay.rr.com> Date: Tue, 29 Aug 2000 19:50:23 GMT NNTP-Posting-Host: 24.95.254.30 X-Complaints-To: abuse@rr.com X-Trace: typhoon.tampabay.rr.com 967578623 24.95.254.30 (Tue, 29 Aug 2000 15:50:23 EDT) NNTP-Posting-Date: Tue, 29 Aug 2000 15:50:23 EDT Organization: RoadRunner - Central Florida Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!psinet-eu-nl!newsfeeds.belnet.be!news.belnet.be!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.cwix.com!cyclone.tampabay.rr.com!typhoon.tampabay.rr.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:955 Does anyone know the exact differences, hardware wise, between a Spartan II and a Virtex? Peter mentioned earlier that there was a temperature diode difference (no diode in Spartan II), but there's got to be more to it in order to explain the cost differential. -Simon Ramirez, Consultant Synchronous Design, Inc. ####### From: nweaver@boom.CS.Berkeley.EDU (Nicholas C. Weaver) Newsgroups: comp.arch.fpga Subject: Re: Spartan II vs. Virtex Date: 29 Aug 2000 20:05:02 GMT Organization: University of California, Berkeley Lines: 13 Message-ID: <8oh51e$8hf$1@agate.berkeley.edu> References: <3uUq5.2462$_8.341101@typhoon.tampabay.rr.com> NNTP-Posting-Host: boom.cs.berkeley.edu X-Trace: agate.berkeley.edu 967579502 8751 128.32.131.183 (29 Aug 2000 20:05:02 GMT) X-Complaints-To: abuse@berkeley.edu NNTP-Posting-Date: 29 Aug 2000 20:05:02 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-hog.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!nweaver Xref: chonsp.franklin.ch comp.arch.fpga:635 In article <3uUq5.2462$_8.341101@typhoon.tampabay.rr.com>, S. Ramirez wrote: > Does anyone know the exact differences, hardware wise, between a >Spartan II and a Virtex? > Peter mentioned earlier that there was a temperature diode difference >(no diode in Spartan II), but there's got to be more to it in order to >explain the cost differential. My understanding is that the logic block was relayed out with more of an emphasis on compactness over performance, so it is denser in terms of CLBs/unit silicon area, but at a performance penalty. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### From: Marc Baker Newsgroups: comp.arch.fpga Subject: Re: Spartan II vs. Virtex Date: Tue, 29 Aug 2000 13:57:00 -0700 Organization: FPGA Applications Lines: 23 Message-ID: <39AC239C.C4E6CBDE@xilinx.com> References: <3uUq5.2462$_8.341101@typhoon.tampabay.rr.com> Reply-To: marc.baker@xilinx.com NNTP-Posting-Host: apps46.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en To: "S. Ramirez" Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news.uni-ulm.de!rz.uni-karlsruhe.de!blackbush.xlink.net!news0.de.colt.net!newscore.gigabell.net!ptdnetP!newsgate.ptd.net!attmtf.ip.att.net!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:221 The only significant architectural difference is that Spartan-II has power down pins in place of the Virtex temperature diode. The cost savings are mostly in the back end, using a more advanced process than the original Virtex family and different packages. The Spartan-II family spans a different density range than Virtex. See the Xilinx web site for more information (http://www.xilinx.com/products/spartan2/ask/architecture.htm). "S. Ramirez" wrote: > Does anyone know the exact differences, hardware wise, between a > Spartan II and a Virtex? > Peter mentioned earlier that there was a temperature diode difference > (no diode in Spartan II), but there's got to be more to it in order to > explain the cost differential. > -Simon Ramirez, Consultant > Synchronous Design, Inc. -- Marc Baker Xilinx Applications (408) 879-5375 ###### From: "Dan" Newsgroups: comp.arch.fpga References: <3uUq5.2462$_8.341101@typhoon.tampabay.rr.com> <8oh51e$8hf$1@agate.berkeley.edu> Subject: Re: Spartan II vs. Virtex Lines: 7 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6600 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6600 Message-ID: <6DWq5.764$O5.61983@news20.bellglobal.com> Date: Tue, 29 Aug 2000 22:16:34 GMT NNTP-Posting-Host: 216.209.56.112 X-Trace: news20.bellglobal.com 967587394 216.209.56.112 (Tue, 29 Aug 2000 18:16:34 EDT) NNTP-Posting-Date: Tue, 29 Aug 2000 18:16:34 EDT Organization: Sympatico Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!nntp-out.monmouth.com!newspeer.monmouth.com!cyclone2.usenetserver.com!news-out.usenetserver.com!news3.bellglobal.com!nf2.bellglobal.com!news20.bellglobal.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:797 Are you saying the route resource/Logic ratio was decreased in Spartan II. Thus making it more difficult to route your design in a Spartan II vs. a similarly sized Virtex ? Dan ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Spartan II vs. Virtex Date: Tue, 29 Aug 2000 22:49:49 -0400 Lines: 44 Message-ID: <39AC764D.EA69F259@yahoo.com> References: <3uUq5.2462$_8.341101@typhoon.tampabay.rr.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: cC4ipRvcHWZ2AHsakZ/98jBLd7s1uUOkCjfz3vwTZvM= X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 30 Aug 2000 02:49:07 GMT X-Accept-Language: en X-Mailer: Mozilla 4.7 [en] (Win95; U) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!newshunter!cosy.sbg.ac.at!news.tele.dk!128.230.129.106!news.maxwell.syr.edu!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:47 From what Peter has said in the past, the cost driver for the Spartan-II comes from the smaller geometry that they used in this family, .18 um vs. .25 um for the Virtex parts. Also contributing is the limited availability of package options. They span a range of sizes, but not a lot of different packages for any size part. So the package/part matrix is more sparce than the Virtex parts. This saves Xilinx money in production and inventory costs. As others have said, there is nearly no difference in the two functionally. "S. Ramirez" wrote: > > Does anyone know the exact differences, hardware wise, between a > Spartan II and a Virtex? > Peter mentioned earlier that there was a temperature diode difference > (no diode in Spartan II), but there's got to be more to it in order to > explain the cost differential. > -Simon Ramirez, Consultant > Synchronous Design, Inc. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com ###### Message-ID: <39AC83C3.F930E42B@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.73 [en] (WinNT; I) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Spartan II vs. Virtex References: <3uUq5.2462$_8.341101@typhoon.tampabay.rr.com> <8oh51e$8hf$1@agate.berkeley.edu> <6DWq5.764$O5.61983@news20.bellglobal.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 23 Date: Wed, 30 Aug 2000 03:49:36 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@home.net X-Trace: news1.wwck1.ri.home.com 967607376 24.13.238.93 (Tue, 29 Aug 2000 20:49:36 PDT) NNTP-Posting-Date: Tue, 29 Aug 2000 20:49:36 PDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!join.news.pipex.net!pipex!tank.news.pipex.net!pipex!howland.erols.net!newshub2.home.com!news.home.com!news1.wwck1.ri.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:241 No, the logic and routing resources are virtually identical. As a matter af fact, you can load a virtex50-FG256 with a bitstream for a spartanII50-FG256...so they are identical functionally down to the bitstream level. As Peter previously mentioned, the spartanII replaces the temp sense diode in virtex with a pair of pins that let you put it into a power down but still retain the contents mode. I got the impression the CLB was taped out again to make it physically smaller (less silicon area), and of course the packaging options are very limited. Dan wrote: > > Are you saying the route resource/Logic ratio was decreased in Spartan II. > Thus making it more difficult to route your design in a Spartan II vs. a > similarly sized Virtex ? > > Dan -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com ###### From: "S. Ramirez" Newsgroups: comp.arch.fpga References: <3uUq5.2462$_8.341101@typhoon.tampabay.rr.com> Subject: Re: Spartan II vs. Virtex Lines: 31 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Message-ID: Date: Wed, 30 Aug 2000 08:59:19 GMT NNTP-Posting-Host: 24.95.254.30 X-Complaints-To: abuse@rr.com X-Trace: typhoon.tampabay.rr.com 967625959 24.95.254.30 (Wed, 30 Aug 2000 04:59:19 EDT) NNTP-Posting-Date: Wed, 30 Aug 2000 04:59:19 EDT Organization: RoadRunner - Central Florida Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!nntp-out.monmouth.com!newspeer.monmouth.com!feed2.onemain.com!feed1.onemain.com!news-out.cwix.com!newsfeed.cwix.com!cyclone.tampabay.rr.com!typhoon.tampabay.rr.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:952 Here is some content that my local Xilinx FAE has come up with: "SpartanII is cheaper than Virtex because it is done on a hybrid process. The transistors are still .25 u. and the routing and all other features are done at .18 u. This does allow us to shrink the die and reduce the cost. The other factor in the cost reduction is the packaging. We targeted only the cheaper plastic packages and also reduced the number of packages offered for each density which also reduces the infrastructure costs and, in the end, reduces the parts cost as well." So functionally the part is the same, but the hybrid process and packaging is what drives down the cost. I wonder why they didn't go .18u all the way. It has to be timing issues. Now if only they will deliver in time! -Simon Ramirez, Consultant Synchronous Design, Inc. "S. Ramirez" wrote in message news:3uUq5.2462$_8.341101@typhoon.tampabay.rr.com... > Does anyone know the exact differences, hardware wise, between a > Spartan II and a Virtex? > Peter mentioned earlier that there was a temperature diode difference > (no diode in Spartan II), but there's got to be more to it in order to > explain the cost differential. > -Simon Ramirez, Consultant > Synchronous Design, Inc. ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Spartan II vs. Virtex Date: Wed, 30 Aug 2000 09:19:52 -0400 Lines: 41 Message-ID: <39AD09F8.FC6DBDB0@yahoo.com> References: <3uUq5.2462$_8.341101@typhoon.tampabay.rr.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: TtyqxUa9Pz+5M5RyRY7AuBE7UZjNQbD+g1z1ZSsGfKc= X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 30 Aug 2000 13:19:02 GMT X-Accept-Language: en X-Mailer: Mozilla 4.7 [en] (Win95; U) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!informatik.tu-muenchen.de!news.informatik.uni-muenchen.de!uni-erlangen.de!newspump.monmouth.com!newspeer.monmouth.com!xfer13.netnews.com!netnews.com!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:81 "S. Ramirez" wrote: > > Here is some content that my local Xilinx FAE has come up with: > > "SpartanII is cheaper than Virtex because it is done on a hybrid process. > The transistors are still .25 u. and the routing and all other features are > done at .18 u. This does allow us to shrink the die and reduce the cost. > So functionally the part is the same, but the hybrid process and > packaging is what drives down the cost. I wonder why they didn't go .18u > all the way. It has to be timing issues. Or possibly the voltage. As you reduce the geometry, the power supply voltage needs to decrease as well. Actually I would have preferred that it be a 1.8 volt process to be compatible with some of the DSP chips I would like to use. But these days the core voltages are all over the map. TI has new chips that use 1.5, 1.6 and 1.8 volts. What difference does 0.1 volts make??? -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com ###### Reply-To: "Tom Meagher" From: "Tom Meagher" Newsgroups: comp.arch.fpga References: <3uUq5.2462$_8.341101@typhoon.tampabay.rr.com> <39AD09F8.FC6DBDB0@yahoo.com> Subject: Re: Spartan II vs. Virtex Lines: 30 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6600 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6600 Message-ID: <3OEr5.39084$g53.696698@news5.giganews.com> NNTP-Posting-Date: Thu, 31 Aug 2000 21:48:31 CDT Organization: Giganews.Com - Premium News Outsourcing X-Trace: sv2-Pz3MOdjb7yTlKBcKjX9Yju6a0NX1dDKxF0rbJT0JaxazSpGr0kw0J0gkB9IhGB945V+UvGeHHVTg6Kh!SO1YOvf3N0S3H1wX1rwyPoN62P0YdQ== X-Complaints-To: abuse@GigaNews.Com X-Abuse-Info: Please be sure to forward a copy of ALL headers X-Abuse-Info: Otherwise we will be unable to process your complaint properly Date: Thu, 31 Aug 2000 21:39:03 -0500 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.nextra.ch!news1.sunrise.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!hermes.visi.com!news-out.visi.com!nntp2.giganews.com!nntp3.giganews.com!news5.giganews.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:798 "rickman" wrote in message news:39AD09F8.FC6DBDB0@yahoo.com... > Or possibly the voltage. As you reduce the geometry, the power supply > voltage needs to decrease as well. Actually I would have preferred that > it be a 1.8 volt process to be compatible with some of the DSP chips I > would like to use. But these days the core voltages are all over the > map. TI has new chips that use 1.5, 1.6 and 1.8 volts. What difference > does 0.1 volts make??? > Rick Collins Aren't Pentium and Alpha chips "tuned" during wafer test to find the exact supply voltage at which they operate at the maximum possible frequency? This voltage is then encoded into 5 pins which connect to the external power supply control chip to program it to deliver the optimum voltage, between 1.3 and 3.5 volts in 50 mV increments. Sometimes I long for the days when everything ran at 5 volts. We now have some units in production with three different logic supply voltages, to cater to all the different chips. Luckily, power supply technology has become so good that it doesn't take much space or heat. But it still represents an extra source of EMI and single point failures. Maybe we'll all standardize again on 0.7 volts or so, in about 5 years. In the meantime, it's the pits... Tom Meagher ICS Triplex Houston TX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Spartan II vs. Virtex Date: Thu, 31 Aug 2000 23:31:25 -0400 Lines: 61 Message-ID: <39AF230D.A7716E01@yahoo.com> References: <3uUq5.2462$_8.341101@typhoon.tampabay.rr.com> <39AD09F8.FC6DBDB0@yahoo.com> <3OEr5.39084$g53.696698@news5.giganews.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: XymSk+TjJFSr5Y5j7L4KI7TrF4IbxIilsA1gVWwlLLE= X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 1 Sep 2000 03:30:49 GMT X-Accept-Language: en X-Mailer: Mozilla 4.7 [en] (Win95; U) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!isdnet!howland.erols.net!outgoing.news.rcn.net.MISMATCH!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:1136 Tom Meagher wrote: > > "rickman" wrote in message > news:39AD09F8.FC6DBDB0@yahoo.com... > > Or possibly the voltage. As you reduce the geometry, the power supply > > voltage needs to decrease as well. Actually I would have preferred that > > it be a 1.8 volt process to be compatible with some of the DSP chips I > > would like to use. But these days the core voltages are all over the > > map. TI has new chips that use 1.5, 1.6 and 1.8 volts. What difference > > does 0.1 volts make??? > > Rick Collins > > Aren't Pentium and Alpha chips "tuned" during wafer test to find the exact > supply voltage at which they operate at the maximum possible frequency? > This voltage is then encoded into 5 pins which connect to the external power > supply control chip to program it to deliver the optimum voltage, between > 1.3 and 3.5 volts in 50 mV increments. > > Sometimes I long for the days when everything ran at 5 volts. We now have > some units in production with three different logic supply voltages, to > cater to all the different chips. Luckily, power supply technology has > become so good that it doesn't take much space or heat. But it still > represents an extra source of EMI and single point failures. > > Maybe we'll all standardize again on 0.7 volts or so, in about 5 years. In > the meantime, it's the pits... I have never heard that they are "tuned" since to the best of my knowledge all chips run faster at higher voltages. They pick a voltage that the chip will not self destruct at and try to keep it low to minimize power consumption. But I am pretty sure they don't alter it for each chip. They just pick a voltage for a given spin of the part and test them all at that voltage. The TI DSP chips seem to go for whatever voltage they feel like designing to that day. The TMS320VC33 uses 1.6 volts which is not any kind of a standard. To supply this voltage you have to use an adjustable regulator. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com