From: jimmy75@my-deja.com Newsgroups: comp.arch.fpga Subject: Help!! Virtex system gate count. Date: Sun, 06 Aug 2000 15:00:21 GMT Organization: Deja.com - Before you buy. Lines: 13 Message-ID: <8mjui4$aq1$1@nnrp1.deja.com> NNTP-Posting-Host: 143.117.5.34 X-Article-Creation-Date: Sun Aug 06 15:00:21 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.01; Windows NT) X-Http-Proxy: 1.1 x65.deja.com:80 (Squid/1.1.22) for client 143.117.5.34 X-MyDeja-Info: XMYDJUIDjimmy75 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!bignews.mediaways.net!netnews.com!cpk-news-hub1.bbnplanet.com!news.gtei.net!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:425 Hi Folks, I am pretty confused, how does Xilinx count the system gates for their Virtex series? I understand that the logic cell count is 4.5 logic cell per CLB (4.5 4LUT). How many gates does a logic cell represent?? I need this info urgently, please help! Sent via Deja.com http://www.deja.com/ Before you buy. ###### Message-ID: <398DB171.7F7518C9@polybus.com> From: "B. Joshua Rosen" Organization: Polybus Systems Corp X-Mailer: Mozilla 4.74 [en] (X11; U; Linux 2.2.14-win4lin i686) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Help!! Virtex system gate count. References: <8mjui4$aq1$1@nnrp1.deja.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 30 Date: Sun, 06 Aug 2000 14:41:53 -0400 NNTP-Posting-Host: 64.6.163.118 X-Complaints-To: news@intira.com X-Trace: news.dbn.net 965586979 64.6.163.118 (Sun, 06 Aug 2000 13:36:19 CDT) NNTP-Posting-Date: Sun, 06 Aug 2000 13:36:19 CDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed.mathworks.com!news.mathworks.com!uunet!ffx.uu.net!news.dbn.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:327 What's your specific objective? are you looking to compare a Xilinx FPGA to an ASIC? If so you can use the following rules of thumb. For an ASIC design that is being dropped into a Xilinx part, take the synopsis gate count and multiply by 6 to find the equivalent size Virtex part, i.e. 100,000 synopsis gates will fit in an XCV600. If the design is targeted directly at Xilinx and you make heavy use of Xilinx specific features like LUT RAMS, Block RAMs, delay lines, and synchronous clears, the effective gate count is pretty close to what Xilinx claims, i.e. that same XCV600 can hold 600K gates or more. The problem with doing a direct comparison is that the value of a LUT varies tremendously depending on how it is used. As a logic element it's only worth aproximately 3 gates, in an ASIC a two wide AOI and a couple of inverters would do much the same job. As memory it's worth a lot more, at least 16 ASIC gates, if you compare it to an ASIC RAM, or maybe as many as 64 gates if the equivalent structure was built out of random gates. Josh jimmy75@my-deja.com wrote: > > Hi Folks, > > I am pretty confused, how does Xilinx count the system gates for their > Virtex series? I understand that the logic cell count is 4.5 logic cell > per CLB (4.5 4LUT). How many gates does a logic cell represent?? > > I need this info urgently, please help! > > Sent via Deja.com http://www.deja.com/ > Before you buy. ###### From: jimmy75@my-deja.com Newsgroups: comp.arch.fpga Subject: Re: Help!! Virtex system gate count. Date: Sun, 06 Aug 2000 21:33:15 GMT Organization: Deja.com - Before you buy. Lines: 18 Message-ID: <8mklis$q54$1@nnrp1.deja.com> References: <8mjui4$aq1$1@nnrp1.deja.com> <398DB171.7F7518C9@polybus.com> NNTP-Posting-Host: 143.117.5.34 X-Article-Creation-Date: Sun Aug 06 21:33:15 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.01; Windows NT) X-Http-Proxy: 1.1 x64.deja.com:80 (Squid/1.1.22) for client 143.117.5.34 X-MyDeja-Info: XMYDJUIDjimmy75 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:440 > comparison is that the value of a LUT varies tremendously depending on > how it is used. As a logic element it's only worth aproximately 3 gates, > in an ASIC a two wide AOI and a couple of inverters would do much the > same job. As memory it's worth a lot more, at least 16 ASIC gates, if > you compare it to an ASIC RAM, or maybe as many as 64 gates if the > equivalent structure was built out of random gates. That's what I do not understand. How does Xilinx count the system gates? I understand the logic cell count (number of 4-LUTs). Now, what does 4-LUT give in terms of gates? I mean do they take it as <=> 3 gates (simple LUT) or 16, 64 gates -as you said- for an equivalent RAM??? it seems it is ~12 gates. Anyone from Xilinx can help me here??? Sent via Deja.com http://www.deja.com/ Before you buy. ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Help!! Virtex system gate count. Date: Mon, 07 Aug 2000 11:41:12 -0400 Lines: 49 Message-ID: <398ED898.5982D3BE@yahoo.com> References: <8mjui4$aq1$1@nnrp1.deja.com> <398DB171.7F7518C9@polybus.com> <8mklis$q54$1@nnrp1.deja.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: CtkntZMahq4YcPntedCA6IZBu+EPcfTawGJDmaV0TXA= X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 7 Aug 2000 15:40:53 GMT X-Accept-Language: en X-Mailer: Mozilla 4.7 [en] (Win95; U) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!news.gtei.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:41 jimmy75@my-deja.com wrote: > > > comparison is that the value of a LUT varies tremendously depending on > > how it is used. As a logic element it's only worth aproximately 3 > gates, > > in an ASIC a two wide AOI and a couple of inverters would do much the > > same job. As memory it's worth a lot more, at least 16 ASIC gates, if > > you compare it to an ASIC RAM, or maybe as many as 64 gates if the > > equivalent structure was built out of random gates. > > That's what I do not understand. How does Xilinx count the system > gates? I understand the logic cell count (number of 4-LUTs). Now, what > does 4-LUT give in terms of gates? I mean do they take it as <=> 3 > gates (simple LUT) or 16, 64 gates -as you said- for an equivalent > RAM??? it seems it is ~12 gates. Anyone from Xilinx can help me here??? Why does this matter? The gate count is a very poor indicator of anything useful. Even the LUT count is a marketing number which does not even count LUTs! They count 4.5 LUTs per CLB when there are only 4 LUTs in a CLB! So why would you expect the gate count to be anything other than marketing fluff? The gate counting that they do is a little complicated since they have to make some assumptions for how much of the block ram to count as well as what modes you will use the other features in. So I don't think you will be able to figure it out without contacting them directly. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Help!! Virtex system gate count. Date: Mon, 07 Aug 2000 11:21:10 -0700 Organization: Xilinx Lines: 82 Message-ID: <398EFE16.FDA3439E@xilinx.com> References: <8mjui4$aq1$1@nnrp1.deja.com> <398DB171.7F7518C9@polybus.com> <8mklis$q54$1@nnrp1.deja.com> <398ED898.5982D3BE@yahoo.com> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; I; PPC) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.cwix.com!cyclone00a-oak.pilot.net!cyclone01-oak.pilot.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:191 rickman wrote: to make some assumptions for how much of the block ram to count as well > as what modes you will use the other features in. So I don't think you > will be able to figure it out without contacting them directly. Peter answers: Here is what I explained more than a year ago. The numbers refer to an XC4000-XL part, but the concept is similar for Virtex. Gate count is a borderline meningless number when applied to LUT-based FPGAs, with large amounts of RAM on-chip, plus dedicated ( hidden and un-counted ) carry logic, sophisticated clock manipulation, and multi-standard I/Os. But as amanufacturer we have to come up with a number, and market the devices in a competitive environment. Anyhow, here is the old explanation from early 1999: Let me explain the 10,982 Logic Cells, 147 k bits of RAM and 265000 max logic gates claimed for the XC40125XV. This is a mixture of engineering specifications and marketing. Engineering specifications: The XC40125XV has a 68 x 68 array of CLBs = 4624 CLBs Each of these CLBs has 32 RAM bits = 147 968 RAM bits total. No ifs and no buts. Now we get into marketing: Since this is a competitive world, our users want to compare different manufacturers, but the structures are not the same. Altera puts eight LUTs in a block, Lucent puts four, and we put two LUTs into a CLB, but everybody's LUTs are more or less identical. So Xilinx decided to standardize the nomenclature and emphasize not CLBs but rather Logic Cells, as a lingua franca for FPGAs. Good idea! Then marketing saw the third LUT in our CLB and gave it a value of 3/8 of a Logic Cell, so the whole CLB is worth 2.375 LCs. Obviously, we can argue about this addition, but it is true that one can use the third LUT for some really nice and efficient solutions. :-) Multiply the 4624 CLBs by 2.375 and you get 10 982 Logic Cells. What is that in ASIC gates? There is no scientific answer, because it depends on the design. What is the LUT being used for, is the flip-flop being used at all, and what if you use the LUT as RAM ? Assume that every LUT is worth 6 gates and every flip-flop is worth 6 gates, then every Logic Cell is worth 12 gates (sometimes more, sometimes less). 12 gates times 10 982 LCs makes a bare-bone gate-count of 131 784, and that is reflected in the name of the device. We are conservative and round it down a little. :-) But there is the RAM in the LUT, and if only 25% of them are really used as RAM, these LUTs are not worth 6 gates, but rather 64 gates (16 bits with 4 bits per RAM cell, again, very conservative, ignoring the select structure and the read/write circuitry). That means, we must add another 58 gates times 25% of 9248 LUTs, which means another 134 096 gates, for a total of 265 880 logic gates. And we say explicitly that this assumes 20 to 30 % of the CLBs being used as RAM. That's how the XC40125XV got its name and its gate-count range of 125,000 to 265,000 gates. It is an attempt to bring some sanity to the gate-count confusion. Users will never agree about these assumption, and if you don't want to compare different manufacturers, then you can forget the whole thing and just stick with CLBs and RAM bits, for they are physical and thus non-controversial. Peter Alfke February 27, 1999 ###### Message-ID: <3990CB0B.1FBF773D@earthlink.net> From: Peter Alfke Reply-To: palfke@earthlink.net X-Mailer: Mozilla 4.61 (Macintosh; I; PPC) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Help!! Virtex system gate count. References: <8mjui4$aq1$1@nnrp1.deja.com> <398DB171.7F7518C9@polybus.com> <8mklis$q54$1@nnrp1.deja.com> <398ED898.5982D3BE@yahoo.com> Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Lines: 83 Date: Wed, 09 Aug 2000 03:07:55 GMT NNTP-Posting-Host: 158.252.218.47 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 965790475 158.252.218.47 (Tue, 08 Aug 2000 20:07:55 PDT) NNTP-Posting-Date: Tue, 08 Aug 2000 20:07:55 PDT Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!news.gtei.net!news.mindspring.net!newsfeed2.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:518 rickman wrote: as what modes you will use the other features in. So I don't think you > will be able to figure it out without contacting them directly. Peter answers: Here is what I explained more than a year ago. The numbers refer to an XC4000-XL part, but the concept is similar for Virtex. Gate count is a borderline meningless number when applied to LUT-based FPGAs, with large amounts of RAM on-chip, plus dedicated ( hidden and un-counted ) carry logic, sophisticated clock manipulation, and multi-standard I/Os. But as amanufacturer we have to come up with a number, and market the devices in a competitive environment. Anyhow, here is the old explanation from early 1999: Let me explain the 10,982 Logic Cells, 147 k bits of RAM and 265000 max logic gates claimed for the XC40125XV. This is a mixture of engineering specifications and marketing. Engineering specifications: The XC40125XV has a 68 x 68 array of CLBs = 4624 CLBs Each of these CLBs has 32 RAM bits = 147 968 RAM bits total. No ifs and no buts. Now we get into marketing: Since this is a competitive world, our users want to compare different manufacturers, but the structures are not the same. Altera puts eight LUTs in a block, Lucent puts four, and we put two LUTs into a CLB, but everybody's LUTs are more or less identical. So Xilinx decided to standardize the nomenclature and emphasize not CLBs but rather Logic Cells, as a lingua franca for FPGAs. Good idea! Then marketing saw the third LUT in our CLB and gave it a value of 3/8 of a Logic Cell, so the whole CLB is worth 2.375 LCs. Obviously, we can argue about this addition, but it is true that one can use the third LUT for some really nice and efficient solutions. :-) Multiply the 4624 CLBs by 2.375 and you get 10 982 Logic Cells. What is that in ASIC gates? There is no scientific answer, because it depends on the design. What is the LUT being used for, is the flip-flop being used at all, and what if you use the LUT as RAM ? Assume that every LUT is worth 6 gates and every flip-flop is worth 6 gates, then every Logic Cell is worth 12 gates (sometimes more, sometimes less). 12 gates times 10 982 LCs makes a bare-bone gate-count of 131 784, and that is reflected in the name of the device. We are conservative and round it down a little. :-) But there is the RAM in the LUT, and if only 25% of them are really used as RAM, these LUTs are not worth 6 gates, but rather 64 gates (16 bits with 4 bits per RAM cell, again, very conservative, ignoring the select structure and the read/write circuitry). That means, we must add another 58 gates times 25% of 9248 LUTs, which means another 134 096 gates, for a total of 265 880 logic gates. And we say explicitly that this assumes 20 to 30 % of the CLBs being used as RAM. That's how the XC40125XV got its name and its gate-count range of 125,000 to 265,000 gates. It is an attempt to bring some sanity to the gate-count confusion. Users will never agree about these assumption, and if you don't want to compare different manufacturers, then you can forget the whole thing and just stick with CLBs and RAM bits, for they are physical and thus non-controversial. Peter Alfke February 27, 1999 ###### From: jimmy75@my-deja.com Newsgroups: comp.arch.fpga Subject: Re: Help!! Virtex system gate count. Date: Wed, 09 Aug 2000 12:20:46 GMT Organization: Deja.com - Before you buy. Lines: 9 Message-ID: <8mrias$i7v$1@nnrp1.deja.com> References: <8mjui4$aq1$1@nnrp1.deja.com> <398DB171.7F7518C9@polybus.com> <8mklis$q54$1@nnrp1.deja.com> <398ED898.5982D3BE@yahoo.com> <3990CB0B.1FBF773D@earthlink.net> NNTP-Posting-Host: 143.117.5.34 X-Article-Creation-Date: Wed Aug 09 12:20:46 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.01; Windows NT) X-Http-Proxy: 1.1 x70.deja.com:80 (Squid/1.1.22) for client 143.117.5.34 X-MyDeja-Info: XMYDJUIDjimmy75 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.nextra.ch!news1.sunrise.ch!news.imp.ch!uni-erlangen.de!newsfeeds.belnet.be!news.belnet.be!feed2.onemain.com!feed1.onemain.com!xfer13.netnews.com!xfe11.netnews.com!netnews.com!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:492 Thanks Peter for your thorough reply. IT MAKES PERFECT SENSE. Moreover, I will go as far as saying that it is pretty conservative. You could easily make it look even bigger :-) Thanks again! Sent via Deja.com http://www.deja.com/ Before you buy.