From: Rodolfo Jardim de Azevedo Newsgroups: comp.arch,comp.arch.embedded,comp.arch.fpga,comp.lang.vhdl Subject: Memory specification Date: Fri, 04 Aug 2000 18:45:09 -0300 Organization: IC - UNICAMP Lines: 15 Message-ID: <398B3965.8BA09BD3@ic.unicamp.br> NNTP-Posting-Host: lampiao.lsc.dcc.unicamp.br Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: saturno.unicamp.br 965424973 15114 143.106.23.50 (4 Aug 2000 21:36:13 GMT) X-Complaints-To: usenet@unicamp.br NNTP-Posting-Date: 4 Aug 2000 21:36:13 GMT X-Mailer: Mozilla 4.73 [en] (X11; U; Linux 2.2.14-5.0 i686) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!HSNX.atgi.net!dcc.unicamp.br!saturno.unicamp.br!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:412 Hi, I'm trying to make an experimental board which will use 2 modules of memory. I will write some VHDL code and use a FPGA to implement it. But I could not find some information yet. I need SRAM modules (I think some PCs use them as cache memory, that would be the best choice). Where can I get some specification of such modules? How to make an interface? (pinouts, time diagrams, ...) In fact, I could even use EEPROMs, because I don't need to change the system memory too much. But I would prefer SRAM modules due to space constraints in my board. Thanks in advance, Rodolfo ###### From: rickman Newsgroups: comp.arch,comp.arch.embedded,comp.arch.fpga,comp.lang.vhdl Subject: Re: Memory specification Date: Fri, 04 Aug 2000 18:32:51 -0400 Lines: 60 Message-ID: <398B4493.98982D41@yahoo.com> References: <398B3965.8BA09BD3@ic.unicamp.br> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: vTFTMRh6dteDk+93mECYNjntWMpknleLqUHbN2OIQOU= X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 4 Aug 2000 22:32:53 GMT X-Accept-Language: en X-Mailer: Mozilla 4.7 [en] (Win95; U) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:1104 SRAM modules are not terribly common although they do exist. Much more common are DRAM modules although standard DRAM and EDO DRAM are being phased out. SDRAM and DDSDRAM (or whatever the acronym is for double data rate SDRAM) are the newer standards with more years left in them. SRAMs are easy to get as chips (other than for allocation problems >:). But you mention that you want density. EEPROMs are much more dense than SRAM. EEPROM in the Flash form are nearly as dense as DRAM and about 16 times more dense than SRAM. I can get 64 Mbit Flash chips but I don't think anyone is making async SRAM bigger than 4 Mbit. Sync SRAMs (the stuff they use as PC cache memory) comes up to 8 or 16 Mbit, IIRC. Of course Flash is much slower than SRAM, but you didn't say what speeds you need. If you don't need speed, SDRAM can be faster than Flash, but you need a more complex controller. Of course that all depends on what you are connecting it to. Sound complicated? It is! Until you learn about the different memory flavors. Rodolfo Jardim de Azevedo wrote: > > Hi, > > I'm trying to make an experimental board which will use 2 modules of > memory. I will write some VHDL code and use a FPGA to implement it. But > I could not find some information yet. I need SRAM modules (I think some > PCs use them as cache memory, that would be the best choice). Where can > I get some specification of such modules? How to make an interface? > (pinouts, time diagrams, ...) > In fact, I could even use EEPROMs, because I don't need to change the > system memory too much. But I would prefer SRAM modules due to space > constraints in my board. > > Thanks in advance, > > Rodolfo -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com ###### From: "Eric Braeden" Newsgroups: comp.arch,comp.arch.embedded,comp.arch.fpga,comp.lang.vhdl References: <398B3965.8BA09BD3@ic.unicamp.br> <398B4493.98982D41@yahoo.com> Subject: Re: Memory specification Date: Fri, 4 Aug 2000 21:49:21 -0400 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2615.200 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 Lines: 7 Message-ID: <398b727d$0$61820$53a6afc1@news.erinet.com> Organization: EriNet Online Communications - Dayton, OH NNTP-Posting-Host: e9ee44c6.news.erinet.com X-Trace: DXC=9ce_d;9mZ;DE4XNZ]a2YgLn2aQE[_=56ELfQeOY Newsgroups: comp.arch,comp.arch.embedded,comp.arch.fpga,comp.lang.vhdl Subject: Re: Memory specification References: <398B3965.8BA09BD3@ic.unicamp.br> <398B4493.98982D41@yahoo.com> <398b727d$0$61820$53a6afc1@news.erinet.com> X-Disclaimer: Everything I write is false. Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 04 Aug 2000 19:07:25 -0700 Message-ID: Lines: 8 X-Newsreader: Gnus v5.5/Emacs 20.3 NNTP-Posting-Host: ruckus.brouhaha.com X-Trace: 4 Aug 2000 19:10:25 -0700, ruckus.brouhaha.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news.sgi.com!news.spies.com!ruckus.brouhaha.com Xref: chonsp.franklin.ch comp.arch.fpga:888 "Eric Braeden" writes: > What about the RAM they put on High end video cards. > I'm looking at one right now that had 32 MB of on-board > RAM and it only has two chips. What is this? 128 Megabit SDRAM or SGRAM chips, most likely. The chips are probably each organized as 4 Megawords of 32 bits, although other organizations are also available. ###### From: rickman Newsgroups: comp.arch,comp.arch.embedded,comp.arch.fpga,comp.lang.vhdl Subject: Re: Memory specification Date: Sat, 05 Aug 2000 00:23:07 -0400 Lines: 42 Message-ID: <398B96AB.8846AB8B@yahoo.com> References: <398B3965.8BA09BD3@ic.unicamp.br> <398B4493.98982D41@yahoo.com> <398b727d$0$61820$53a6afc1@news.erinet.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: oFCFUe8Cwhp8T8nGvjke0TQsqiJJpabEAEv17XdCjaY= X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 5 Aug 2000 04:23:06 GMT X-Accept-Language: en X-Mailer: Mozilla 4.7 [en] (Win95; U) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:45 SDRAM or possibly older VDRAM. VDRAM is a standard DRAM with a second IO port which is a serial 4 bit port. The page to be read/written is selected from the standard port with a special command. The data is loaded into what amounts to a 1024 bit shift register (I think it is really a SRAM) and is shifted out at rates up to around 50 MHz or so. With SDRAM running at over 100 MHz the VDRAM has dropped from the picture on the newer boards. It was also very expensive compared to standard DRAM or even EDO DRAM. But all video cards for PCs use some form of DRAM since they are very cost sensitive. Eric Braeden wrote: > > What about the RAM they put on High end video cards. > I'm looking at one right now that had 32 MB of on-board > RAM and it only has two chips. What is this? > Eric -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com ###### From: gstse@home.com (Gary Tse) Newsgroups: comp.arch,comp.arch.embedded,comp.arch.fpga,comp.lang.vhdl Subject: Re: Memory specification References: <398B3965.8BA09BD3@ic.unicamp.br> Organization: Raoul Duke School of Pharmacology and Journalism Message-ID: User-Agent: slrn/0.9.5.7 (UNIX) Lines: 12 Date: Mon, 07 Aug 2000 06:36:08 GMT NNTP-Posting-Host: 24.5.202.72 X-Complaints-To: abuse@home.net X-Trace: news2.rdc1.on.home.com 965630168 24.5.202.72 (Sun, 06 Aug 2000 23:36:08 PDT) NNTP-Posting-Date: Sun, 06 Aug 2000 23:36:08 PDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newshub2.home.com!news.home.com!news2.rdc1.on.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:932 In article <398B3965.8BA09BD3@ic.unicamp.br>, Rodolfo Jardim de Azevedo wrote: >I need SRAM modules (I think some >PCs use them as cache memory, that would be the best choice). Where can >I get some specification of such modules? How to make an interface? >(pinouts, time diagrams, ...) http://www.idt.com/products/pages/SRAM-PL101_Sub244_Dev215.html , for example. I am sure other SRAM vendors sell modules also. -- Gary Tse, gstse@home.com "Will write Verilog for food." ###### From: Rodolfo Jardim de Azevedo Newsgroups: comp.arch,comp.arch.embedded,comp.arch.fpga,comp.lang.vhdl Subject: Re: Memory specification Date: Tue, 08 Aug 2000 10:32:15 -0300 Organization: IC - UNICAMP Lines: 27 Message-ID: <39900BDF.30964B98@ic.unicamp.br> References: <398B3965.8BA09BD3@ic.unicamp.br> <398B4493.98982D41@yahoo.com> NNTP-Posting-Host: lampiao.lsc.dcc.unicamp.br Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: saturno.unicamp.br 965741013 1418 143.106.23.50 (8 Aug 2000 13:23:33 GMT) X-Complaints-To: usenet@unicamp.br NNTP-Posting-Date: 8 Aug 2000 13:23:33 GMT To: rick.collins@arius.com X-Mailer: Mozilla 4.73 [en] (X11; U; Linux 2.2.14-5.0 i686) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.nextra.ch!news1.sunrise.ch!news.imp.ch!psinet-eu-nl!newsfeeds.belnet.be!news.belnet.be!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!HSNX.atgi.net!dcc.unicamp.br!saturno.unicamp.br!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:403 rickman wrote: > > SRAM modules are not terribly common although they do exist. Much more > common are DRAM modules although standard DRAM and EDO DRAM are being > phased out. SDRAM and DDSDRAM (or whatever the acronym is for double > data rate SDRAM) are the newer standards with more years left in them. > > SRAMs are easy to get as chips (other than for allocation problems >:). > But you mention that you want density. EEPROMs are much more dense than > SRAM. EEPROM in the Flash form are nearly as dense as DRAM and about 16 > times more dense than SRAM. I can get 64 Mbit Flash chips but I don't > think anyone is making async SRAM bigger than 4 Mbit. Sync SRAMs (the > stuff they use as PC cache memory) comes up to 8 or 16 Mbit, IIRC. > > Of course Flash is much slower than SRAM, but you didn't say what speeds > you need. If you don't need speed, SDRAM can be faster than Flash, but > you need a more complex controller. Of course that all depends on what > you are connecting it to. > > Sound complicated? It is! Until you learn about the different memory > flavors. Do you sugest me any book? Thanks again, Rodolfo ###### From: rickman Newsgroups: comp.arch,comp.arch.embedded,comp.arch.fpga,comp.lang.vhdl Subject: Re: Memory specification Date: Tue, 08 Aug 2000 09:41:39 -0400 Lines: 90 Message-ID: <39900E13.413AB9D8@yahoo.com> References: <398B3965.8BA09BD3@ic.unicamp.br> <398B4493.98982D41@yahoo.com> <39900BDF.30964B98@ic.unicamp.br> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: 0D0d0Cp6JgAtwObyGCN1nk1UFslIrKnTYWxCTkbSQ2s= X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 8 Aug 2000 13:41:22 GMT X-Accept-Language: en X-Mailer: Mozilla 4.7 [en] (Win95; U) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:1118 Rodolfo Jardim de Azevedo wrote: > > rickman wrote: > > > > SRAM modules are not terribly common although they do exist. Much more > > common are DRAM modules although standard DRAM and EDO DRAM are being > > phased out. SDRAM and DDSDRAM (or whatever the acronym is for double > > data rate SDRAM) are the newer standards with more years left in them. > > > > SRAMs are easy to get as chips (other than for allocation problems >:). > > But you mention that you want density. EEPROMs are much more dense than > > SRAM. EEPROM in the Flash form are nearly as dense as DRAM and about 16 > > times more dense than SRAM. I can get 64 Mbit Flash chips but I don't > > think anyone is making async SRAM bigger than 4 Mbit. Sync SRAMs (the > > stuff they use as PC cache memory) comes up to 8 or 16 Mbit, IIRC. > > > > Of course Flash is much slower than SRAM, but you didn't say what speeds > > you need. If you don't need speed, SDRAM can be faster than Flash, but > > you need a more complex controller. Of course that all depends on what > > you are connecting it to. > > > > Sound complicated? It is! Until you learn about the different memory > > flavors. > > Do you sugest me any book? > > Thanks again, > > Rodolfo No one book, but go to the web sites for several of the memory manufacturers and read the datasheets, the app notes and the selection guides for all of their parts. Some good sites to visit are Micron, Samsung and Intel. Micron data sheets are very clear and they have good app notes. Samsung has a nice variety of parts. Intel has a poor web site that is hard to navigate, but they sell a lot of Flash and have some rather unique parts. I don't think you will find much of this stuff in a text book of any kind. Summary: Async SRAM - Fast to slow, no clock, no overhead for first access. Sync SRAM - Fast, clock up to 200 MHz(?), one or two clock overhead for first access. EEPROM - Moderately slow, no clock, no overhead for first read, erase and write bytes. Async Flash - Moderately slow, no clock, no overhead for first read, must erase in blocks. Sync Flash - I have not used this (or even looked at it yet) but Micron (or is it Samsung?) claims it is compatible with SDRAM. Sync DRAM - Fast, up to 133 MHz clock, multiple cycle delay for first read or write, fast block read/writes. DD DRAM - Like Sync, but transfers data on each clock edge. RAMBUS - Sync DRAM with a special very high speed interface up to 400 MHz(?), used in high end PCs. There are others, but they are for special applications and cost more or a lot more money. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com ###### From: Mark W Brehob Newsgroups: comp.arch,comp.arch.embedded,comp.arch.fpga,comp.lang.vhdl Subject: Re: Memory specification Date: 8 Aug 2000 15:03:06 GMT Organization: Michigan State University Lines: 116 Message-ID: <8mp7fa$k8j$1@msunews.cl.msu.edu> References: <398B3965.8BA09BD3@ic.unicamp.br> <398B4493.98982D41@yahoo.com> <39900BDF.30964B98@ic.unicamp.br> <39900E13.413AB9D8@yahoo.com> NNTP-Posting-Host: phalange.cse.msu.edu User-Agent: tin/pre-1.4-980618 (UNIX) (SunOS/5.8 (sun4u)) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!nntp-out.monmouth.com!newspeer.monmouth.com!cyclone.bc.net!logbridge.uoregon.edu!msunews!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:679 Some books that might be of interest. Look at things written by Betty Prince. She has two books out I think, both of which may be in the second edition. They are fairly detailed. Micron's free book about what they sell is an interesting read if you take your time. I learned a lot from it. Both of these can be fairly detailed and neither are really what you are really looking for, but the info you want is likely inside of both. Careful web searching might help too. If your company is willing to hire someone to get you all up to speed, you might try Ms. Prince. She comes across as quite knowledgeable and is available for such things. (I've only met her once.) Best of luck, Mark In comp.arch rickman wrote: > Rodolfo Jardim de Azevedo wrote: >> >> rickman wrote: >> > >> > SRAM modules are not terribly common although they do exist. Much more >> > common are DRAM modules although standard DRAM and EDO DRAM are being >> > phased out. SDRAM and DDSDRAM (or whatever the acronym is for double >> > data rate SDRAM) are the newer standards with more years left in them. >> > >> > SRAMs are easy to get as chips (other than for allocation problems >:). >> > But you mention that you want density. EEPROMs are much more dense than >> > SRAM. EEPROM in the Flash form are nearly as dense as DRAM and about 16 >> > times more dense than SRAM. I can get 64 Mbit Flash chips but I don't >> > think anyone is making async SRAM bigger than 4 Mbit. Sync SRAMs (the >> > stuff they use as PC cache memory) comes up to 8 or 16 Mbit, IIRC. >> > >> > Of course Flash is much slower than SRAM, but you didn't say what speeds >> > you need. If you don't need speed, SDRAM can be faster than Flash, but >> > you need a more complex controller. Of course that all depends on what >> > you are connecting it to. >> > >> > Sound complicated? It is! Until you learn about the different memory >> > flavors. >> >> Do you sugest me any book? >> >> Thanks again, >> >> Rodolfo > No one book, but go to the web sites for several of the memory > manufacturers and read the datasheets, the app notes and the selection > guides for all of their parts. Some good sites to visit are Micron, > Samsung and Intel. Micron data sheets are very clear and they have good > app notes. Samsung has a nice variety of parts. Intel has a poor web > site that is hard to navigate, but they sell a lot of Flash and have > some rather unique parts. > I don't think you will find much of this stuff in a text book of any > kind. > Summary: > Async SRAM - Fast to slow, no clock, no overhead for first access. > Sync SRAM - Fast, clock up to 200 MHz(?), one or two clock overhead for > first access. > EEPROM - Moderately slow, no clock, no overhead for first read, erase > and write bytes. > Async Flash - Moderately slow, no clock, no overhead for first read, > must erase in blocks. > Sync Flash - I have not used this (or even looked at it yet) but Micron > (or is it Samsung?) claims it is compatible with SDRAM. > Sync DRAM - Fast, up to 133 MHz clock, multiple cycle delay for first > read or write, fast block read/writes. > DD DRAM - Like Sync, but transfers data on each clock edge. > RAMBUS - Sync DRAM with a special very high speed interface up to 400 > MHz(?), used in high end PCs. > There are others, but they are for special applications and cost more or > a lot more money. > -- > Rick Collins > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > Internet URL http://www.arius.com -- ~~~~~~~~~~~~~~~~ http://www.cps.msu.edu/~brehob ~~~~~~~~~~~~~~~~~~ | | The reports of SIMD's death have been greatly exaggerated | | | -=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- | ~~~~~~Mark Brehob: Ultimate Player, Gamer, Computer Geek~~~~~~~~~~ ###### Message-ID: <399093F6.1D692450@polybus.com> From: "B. Joshua Rosen" Organization: Polybus Systems Corp X-Mailer: Mozilla 4.74 [en] (X11; U; Linux 2.2.14-win4lin i686) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch,comp.arch.embedded,comp.arch.fpga,comp.lang.vhdl Subject: Re: Memory specification References: <398B3965.8BA09BD3@ic.unicamp.br> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 22 Date: Tue, 08 Aug 2000 19:12:54 -0400 NNTP-Posting-Host: 64.6.163.118 X-Complaints-To: news@intira.com X-Trace: news.dbn.net 965776035 64.6.163.118 (Tue, 08 Aug 2000 18:07:15 CDT) NNTP-Posting-Date: Tue, 08 Aug 2000 18:07:15 CDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!hermes.visi.com!news-out.visi.com!uunet!ffx.uu.net!news.dbn.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:261 Goto the www.micron.com site. They provide Verilog and VHDL models for all of their RAMs. YOu probably want to use either Sync DRAM or ZBT sync SRAMs. Rodolfo Jardim de Azevedo wrote: > > Hi, > > I'm trying to make an experimental board which will use 2 modules of > memory. I will write some VHDL code and use a FPGA to implement it. But > I could not find some information yet. I need SRAM modules (I think some > PCs use them as cache memory, that would be the best choice). Where can > I get some specification of such modules? How to make an interface? > (pinouts, time diagrams, ...) > In fact, I could even use EEPROMs, because I don't need to change the > system memory too much. But I would prefer SRAM modules due to space > constraints in my board. > > Thanks in advance, > > Rodolfo ###### From: "dls2" Newsgroups: comp.arch,comp.arch.embedded,comp.arch.fpga,comp.lang.vhdl References: <398B3965.8BA09BD3@ic.unicamp.br> <398B4493.98982D41@yahoo.com> <39900BDF.30964B98@ic.unicamp.br> <39900E13.413AB9D8@yahoo.com> <8mp7fa$k8j$1@msunews.cl.msu.edu> Subject: Re: Memory specification Lines: 11 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6700 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6700 Message-ID: Date: Mon, 14 Aug 2000 12:10:11 GMT NNTP-Posting-Host: 24.13.83.35 X-Complaints-To: abuse@home.net X-Trace: news1.rdc1.nj.home.com 966255011 24.13.83.35 (Mon, 14 Aug 2000 05:10:11 PDT) NNTP-Posting-Date: Mon, 14 Aug 2000 05:10:11 PDT Organization: @Home Network Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newshub2.home.com!news.home.com!news1.rdc1.nj.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:927 "Mark W Brehob" wrote: > Micron's free book about what they sell is an interesting read if you take > your time. I learned a lot from it. What book? -- Derrick Shearer