User-Agent: Microsoft-Outlook-Express-Macintosh-Edition/5.02.2022 Subject: pdp8x, fpga code, and front panels From: David G Conroy Newsgroups: alt.sys.pdp8 Message-ID: Mime-version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Lines: 13 Date: Sun, 20 Aug 2000 00:25:18 GMT NNTP-Posting-Host: 207.21.131.65 X-Complaints-To: abuse@verio.net X-Trace: sjc-read 966731118 207.21.131.65 (Sun, 20 Aug 2000 00:25:18 GMT) NNTP-Posting-Date: Sun, 20 Aug 2000 00:25:18 GMT Organization: Verio Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!bignews.mediaways.net!news.vas-net.net!diablo.theplanet.net!news.maxwell.syr.edu!newsfeed.cwix.com!sjc-peer.news.verio.net!news.verio.net!sjc-read.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp8:55 I'll package up the code and attach it to the web pages (but not in the next couple of days, since I have guests from out-of-town). I considered building a front panel, but decided not to because it would have been more work to build, both in the simulators, and in real life. Personally, I'm still fond of lights (they give you a wonderful quick peek at what's going on) but I don't miss the switches at all. dgc ###### Message-ID: <399F0CD7.FFE87768@jetnet.ab.ca> Date: Sat, 19 Aug 2000 22:40:23 +0000 From: Ben Franchuk X-Mailer: Mozilla 4.73 [en] (X11; I; Linux 2.2.15 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp8 Subject: Re: pdp8x, fpga code, and front panels References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 207.153.6.48 X-Trace: 19 Aug 2000 18:27:57 -0700, 207.153.6.48 Organization: OA Internet Lines: 30 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!newsfeed.direct.ca!look.ca!west2.newsfeed.sprint-canada.net!news.oanet.com!207.153.6.48 Xref: chonsp.franklin.ch alt.sys.pdp8:58 David G Conroy wrote: > > I'll package up the code and attach it to the > web pages (but not in the next couple of days, since I have guests > from out-of-town). > > I considered building a front panel, but decided not > to because it would have been more work to build, both in the simulators, > and in real life. Personally, I'm still fond of lights (they give > you a wonderful quick peek at what's going on) but I don't miss the > switches at all. > > dgc I am building a FPGA cpu ( darn -- I could had a PDP-8 ) and would like to have some sort of octal display. In my case I may be limited by the I/O pins on the prototype board and/or the amount free CLB's in my FPGA left after I finish my design. Ben. PS - how fast can you over clock the cpu past 8 meg assuming the ram/eprom could keep up. A non-turbo - switch to drop down your clock by 1/3 would be handy for real PDP-I timing speeds. (I/O operation?) Continue the good work? -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Octal Computers:Where a step backward is two steps forward!" http://www.jetnet.ab.ca/users/bfranchuk/index.html ###### User-Agent: Microsoft-Outlook-Express-Macintosh-Edition/5.02.2022 Subject: Re: pdp8x, fpga code, and front panels From: David G Conroy Newsgroups: alt.sys.pdp8 Message-ID: References: <399F0CD7.FFE87768@jetnet.ab.ca> Mime-version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Lines: 54 Date: Sun, 20 Aug 2000 05:59:03 GMT NNTP-Posting-Host: 207.21.131.101 X-Complaints-To: abuse@verio.net X-Trace: sjc-read 966751143 207.21.131.101 (Sun, 20 Aug 2000 05:59:03 GMT) NNTP-Posting-Date: Sun, 20 Aug 2000 05:59:03 GMT Organization: Verio Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news.uni-stuttgart.de!uni-erlangen.de!newsfeeds.belnet.be!news.belnet.be!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.cwix.com!sjc-peer.news.verio.net!news.verio.net!sjc-read.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp8:54 in article 399F0CD7.FFE87768@jetnet.ab.ca, Ben Franchuk at bfranchuk@jetnet.ab.ca wrote on 8/19/00 3:40 PM: > David G Conroy wrote: >> >> I'll package up the code and attach it to the >> web pages (but not in the next couple of days, since I have guests >> from out-of-town). >> >> I considered building a front panel, but decided not >> to because it would have been more work to build, both in the simulators, >> and in real life. Personally, I'm still fond of lights (they give >> you a wonderful quick peek at what's going on) but I don't miss the >> switches at all. >> >> dgc > > I am building a FPGA cpu ( darn -- I could had a PDP-8 ) > and would like to have some sort of octal display. In my case > I may be limited by the I/O pins on the prototype board and/or the > amount free CLB's in my FPGA left after I finish my design. > Ben. > PS - how fast can you over clock the cpu past 8 meg assuming > the ram/eprom could keep up. A non-turbo - switch to drop down your > clock by 1/3 would be handy for real PDP-I timing speeds. (I/O operation?) > Continue the good work? > Neither the RAM nor the EPROM are critical path. The RAM has to run in a clock, but it's built from 15 ns SRAMS, because that's what I happened to have. The EPROM is known to be slow, so the logic arranges that it gets three cycles for access. The critical path is what you might expect. The major/minor state flopflops snap into a new state, some combinatorial logic computes the carry into the bottom of the adder, the carry ripples across 12 stages of adder, and then passes through the rotate box, and the result has to make setup on the registers attached to the global write bus. This runs at about 10 MHz worst-case today (the timing constraint on the clock said 8 MHz worst case). If I stuck a flipflop in the generation of the carry in signal (which is a little tricky because I execute group 1 OPR, and therefor IAC, in the tail end of the FETCH cycle), and replaced the 12-bit ripple carry adder with something better (like 3 6-bit adders in a carry-select configuration) the thing would run much faster. dgc -- Lynn in El Granada, California Now: lynncc@veriomail.com Previously: lynncc@quake.net and lynncc@psn.net ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp8 Subject: Re: pdp8x, fpga code, and front panels Date: 20 Aug 2000 23:51:50 +0200 Organization: My own Private Self Lines: 76 Message-ID: <6uog2nha89.fsf@chonsp.franklin.ch> References: <399F0CD7.FFE87768@jetnet.ab.ca> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 966808310 597 10.0.3.2 (20 Aug 2000 21:51:50 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 20 Aug 2000 21:51:50 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp8:68 David G Conroy writes: > in article 399F0CD7.FFE87768@jetnet.ab.ca, Ben Franchuk at > bfranchuk@jetnet.ab.ca wrote on 8/19/00 3:40 PM: > > > David G Conroy wrote: > >> > >> I considered building a front panel, but decided not > >> to because it would have been more work to build, Sure. But impressive :-). And 1 print full of LEDs is not that much work (compared to making all them logic descriptions for the Xilinxes). > >> and in real life. Personally, I'm still fond of lights (they give > >> you a wonderful quick peek at what's going on) Yes, ideal also to explain what is going on. Ideal for teaching. Where else will todays students learn the basics we leared. Sure not from playing with Windows. Actually I am on the lookout for an real or simulated pdp8 or pdp11 for teaching "real computing" to students. I have just has 2 pdp8/a offered and am going visiting them next wednesday. > but I don't miss the > >> switches at all. :-) They may be slow, but they force you to understand. > > and would like to have some sort of octal display. In my case > > I may be limited by the I/O pins on the prototype board and/or the > > amount free CLB's in my FPGA left after I finish my design. Ever thought of multiplexing the data out of the CPU chip? Have all the signals that correspond to an light run to an chip-internal n->1 multiplexer and then to 1 pin. Have that pin run externally to an 1->n demultiplexer. Add 2 pins for synchronising them (n selection counter clock and reset). And then have both mux/demux run by the CPU clock you already have. Or use the data bus pins while quiet to output the data to the lights with a few extra strobe signals. Could be even easier. > Neither the RAM nor the EPROM are critical > path. The RAM has to run in a clock, but it's built from 15 ns SRAMS, > because that's what I happened to have. So lots of room for updating a few 74LS373s with LEDs behind them. > The EPROM is known > to be slow, so the logic arranges that it gets three cycles for access. Must still be the fastest pdp8 in the world :-). > global write bus. This runs at about 10 MHz worst-case today (the timing > constraint on the clock said 8 MHz worst case). Still damn fast compared to the 5MHz of an pdp8/e. Oh and: cool project that pdp8/x I enjoyed the website. I am thinking of doing the same for an 11 when I find some copious free time. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, Mystic ###### From: "Jan Gray" Newsgroups: alt.sys.pdp8 References: <399F0CD7.FFE87768@jetnet.ab.ca> <6uog2nha89.fsf@chonsp.franklin.ch> Subject: Re: pdp8x, fpga code, and front panels Lines: 31 Organization: Gray Research LLC X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Message-ID: <_C3o5.4269$gM4.771829@dfiatx1-snr1.gtei.net> X-Trace: /bdhN7ltQomJK7e6rbWjzS3A5Y0exWnqdJ9SsFlZ3pGBG9RGxg4v4pwPcrFFHV9w4R9wQsAwCeN3!yDAUjva29pVlBvNnYa4vRE3gnB/SwQqqWSEJPNtmbftdgaTeoucaL6K0R5g5zoeUlJZ1uFj7wp9Y!b0eA X-Complaints-To: abuse@gte.net X-Abuse-Info: Please be sure to forward a copy of ALL headers X-Abuse-Info: Otherwise we will be unable to process your complaint properly NNTP-Posting-Date: Mon, 21 Aug 2000 06:03:38 GMT Distribution: world Date: Mon, 21 Aug 2000 06:03:38 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!isdnet!sunqbc.risq.qc.ca!cpk-news-hub1.bbnplanet.com!paloalto-snh1.gtei.net!news.gtei.net!dfiatx1-snr1.gtei.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp8:78 "Neil Franklin" wrote in message news:6uog2nha89.fsf@chonsp.franklin.ch... > > >> and in real life. Personally, I'm still fond of lights (they give > > >> you a wonderful quick peek at what's going on) > > Yes, ideal also to explain what is going on. Ideal for teaching. Where > else will todays students learn the basics we leared. Sure not from > playing with Windows. Don't laugh: consider a bitmapped bilevel VGA controller. Instead of watching 12 or 16 bits, you get to watch 2^18 bits. This assumes you have some spare gates, some spare RAM, some spare bandwidth to RAM, and 3-5 spare pins (/HSYNC, /VSYNC, RGB). If you don't have any spare RAM, you at least get to observe every last bit of RAM twiddling, refreshed at 60 Hz on your VGA monitor. (Indeed, this is a compelling teaching tool.) If you do have spare RAM, you can write front-panel code to paint "LEDs" (discretes or 7-segments or both) in a part of that RAM for display on your monitor. In the XSOC/xr16 system (pipelined RISC + SoC + VGA controller in an XC4005E/XL), I implemented the video timing and address generation and multiplexing in about 35 CLBs (~18% of an S10), so this could be a fairly low-cost, low-pinout solution. See www.fpgacpu.org/usenet/vga.html. Jan Gray Gray Research LLC ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp8 Subject: Re: pdp8x, fpga code, and front panels Date: 21 Aug 2000 23:08:59 +0200 Organization: My own Private Self Lines: 58 Message-ID: <6u66ouiaok.fsf@chonsp.franklin.ch> References: <399F0CD7.FFE87768@jetnet.ab.ca> <6uog2nha89.fsf@chonsp.franklin.ch> <_C3o5.4269$gM4.771829@dfiatx1-snr1.gtei.net> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 966892139 812 10.0.3.2 (21 Aug 2000 21:08:59 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 21 Aug 2000 21:08:59 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp8:81 "Jan Gray" writes: > "Neil Franklin" wrote in message > news:6uog2nha89.fsf@chonsp.franklin.ch... > > > > Yes, ideal also to explain what is going on. Ideal for teaching. Where > > else will todays students learn the basics we leared. Sure not from > > playing with Windows. > > Don't laugh: consider a bitmapped bilevel VGA controller. Instead of > watching 12 or 16 bits, you get to watch 2^18 bits. Not quite sure what you mean with "bilevel". And AFAIK all VGAs are bitmapped, 640x480x4bits in the standard mode (I am not counting the 80x25 char MDA/CGA emulation as VGA). > This assumes you have some spare gates, some spare RAM, some spare bandwidth > to RAM, and 3-5 spare pins (/HSYNC, /VSYNC, RGB). That would mean the video generator in the FPGA, using your emulated systems RAM as its frame buffer. > If you don't have any spare RAM, you at least get to observe every last bit > of RAM twiddling, refreshed at 60 Hz on your VGA monitor. (Indeed, this is > a compelling teaching tool.) Definitely. Reminds me of the operators of the Whirlwind (1953). That (tube-)computer system used electrostatic memory (essentially an oscilloscope tube with an synchronised video camera attached to it, to read it out and refresh the phosphors). They added an second second oscilloscope parallel to the one in the memory and could see all the program operating patterns. This was used for debugging. > If you do have spare RAM, you can write > front-panel code to paint "LEDs" (discretes or 7-segments or both) in a part > of that RAM for display on your monitor. A "GUI" frontpannel, like the Doug Jones pdp8/e emulator for Unix/X has, but from an hardware computer. Neat. > In the XSOC/xr16 system (pipelined RISC + SoC + VGA controller in an SoC? I have never met that acronym before. > low-cost, low-pinout solution. See www.fpgacpu.org/usenet/vga.html. Cool. A website for FGPA CPU building. Just what the doctor ordered. Aha, bilevel seems to mean 1 bit/pixel b&w. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, Mystic ###### Message-ID: <39A1BF40.9C118080@jetnet.ab.ca> Date: Mon, 21 Aug 2000 23:46:08 +0000 From: Ben Franchuk X-Mailer: Mozilla 4.73 [en] (X11; I; Linux 2.2.15 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp8 Subject: Re: pdp8x, fpga code, and front panels References: <399F0CD7.FFE87768@jetnet.ab.ca> <6uog2nha89.fsf@chonsp.franklin.ch> <_C3o5.4269$gM4.771829@dfiatx1-snr1.gtei.net> <6u66ouiaok.fsf@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 207.153.6.49 X-Trace: 21 Aug 2000 16:47:44 -0700, 207.153.6.49 Organization: OA Internet Lines: 26 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news.uni-stuttgart.de!logbridge.uoregon.edu!newsfeed.direct.ca!look.ca!west2.newsfeed.sprint-canada.net!news.oanet.com!207.153.6.49 Xref: chonsp.franklin.ch alt.sys.pdp8:82 Neil Franklin wrote: > > Cool. A website for FGPA CPU building. Just what the doctor > ordered. Aha, bilevel seems to mean 1 bit/pixel b&w. Looking at a schematic of the development board ( pdf file) you have a simple D/A converter going to the VGA board. They use two bits per RGB values,thus colors something like the cga cards of years back. Since I am rusty on A/D converters I just can't say if that is 3 or 4 levels of color. That is a great idea for lab type work.How ever the clock on my card is fixed at 4Mhz, not a good frequency for video out, thus I can't use that idea. (I can't complain - still 2x as fast as my TTL design). This also reminds me of the adding 2- 8 bit D/A converters to the address lines and and watching the program run on a oscilloscope. Ben. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Octal Computers:Where a step backward is two steps forward!" http://www.jetnet.ab.ca/users/bfranchuk/index.html ###### From: aek@spies.com (Al Kossow) Newsgroups: alt.sys.pdp8 Subject: Re: pdp8x, fpga code, and front panels Date: Mon, 21 Aug 2000 17:04:51 -0700 Organization: Apple Computer, Inc. Lines: 13 Message-ID: References: <399F0CD7.FFE87768@jetnet.ab.ca> <6uog2nha89.fsf@chonsp.franklin.ch> <_C3o5.4269$gM4.771829@dfiatx1-snr1.gtei.net> <6u66ouiaok.fsf@chonsp.franklin.ch> <39A1BF40.9C118080@jetnet.ab.ca> NNTP-Posting-Host: haxrus.apple.com X-Trace: news.apple.com 966902672 8031 17.205.21.66 (22 Aug 2000 00:04:32 GMT) X-Complaints-To: usenet@news.apple.com NNTP-Posting-Date: 22 Aug 2000 00:04:32 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news.uni-stuttgart.de!uni-erlangen.de!newsfeeds.belnet.be!news.belnet.be!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!paloalto-snf1.gtei.net!news.gtei.net!forum.apple.com!news.apple.com!haxrus.apple.com!user Xref: chonsp.franklin.ch alt.sys.pdp8:92 In article <39A1BF40.9C118080@jetnet.ab.ca>, Ben Franchuk wrote: > This also reminds me of the adding 2- 8 bit D/A converters to the > address lines and and watching the program run on a oscilloscope. published in a late 70's Byte article by Steve Ciarcia... This was also one of the features of the HP 1600A logic analyzer. -- The eBay Curse: "May you find everything you're looking for.." ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp8 Subject: Re: pdp8x, fpga code, and front panels Date: 22 Aug 2000 21:54:53 +0200 Organization: My own Private Self Lines: 20 Message-ID: <6u7l99oyuq.fsf@chonsp.franklin.ch> References: <399F0CD7.FFE87768@jetnet.ab.ca> <6uog2nha89.fsf@chonsp.franklin.ch> <_C3o5.4269$gM4.771829@dfiatx1-snr1.gtei.net> <6u66ouiaok.fsf@chonsp.franklin.ch> <39A1BF40.9C118080@jetnet.ab.ca> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 966974093 665 10.0.3.2 (22 Aug 2000 19:54:53 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 22 Aug 2000 19:54:53 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp8:99 Ben Franchuk writes: > Neil Franklin wrote: > > > ordered. Aha, bilevel seems to mean 1 bit/pixel b&w. > > They use two bits per RGB values,thus colors something like the > cga cards of years back. Since I am rusty on A/D converters > I just can't say if that is 3 or 4 levels of color. 4 levels. The formula is: levels = 2^bits. So here 4 = 2^2. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, Mystic