Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: alt.sys.pdp10 Subject: KA10 hardware surprise Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 16 Aug 2002 00:21:17 -0700 Message-ID: Lines: 89 User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: 209.66.107.17 X-Trace: 16 Aug 2002 00:42:09 -0700, 209.66.107.17 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!solnet.ch!newsfeed.freenet.de!newsfeed.wirehub.nl!logbridge.uoregon.edu!arclight.uoregon.edu!enews.sgi.com!news.spies.com!209.66.107.17 Xref: chonsp.franklin.ch alt.sys.pdp10:11747 I was just looking over some old DEC maintenance prints, specifically the two volume set "PDP10-0-MOD1" and "PDP10-0-MOD2", which are described as module replacement schematics. These were published in 1972, and contain schematics for all of the modules used in the KA10, KI10, and some of the peripherals. These prints do not give any wiring information for higher-level assemblies, so I have details of how the modules are actually used in the KA10. Perusing these, I learned something that surprised me very much. Everyone knows that the KA10 was built using B-, R-, and S- series modules with discrete transistors, and that the KI10 was the first PDP-10 to use TTL integrated circuits, right? Actually, wrong! It turns out that at least three types of B-series modules in the KA10 contained TTL integrated circuits! I was quite surprised. The module types are: B198 Protection Comparator appears to be an 8-bit magnitude comparator prints drawn 6-18-68, checked 6/21/68, eng. approval 7/2/68 5 74H00N 2 74H40N 4 74H50N 1 74H53N 2 74H55N B199 FM Address Decoder acts as a 4-to-16 decoder (similar to 74154), but requires both true and complement inputs prints drawn 3-2-67, checked 4/?/67, eng. approval 7/6/67 8 TI SN7440N or Fairchild U6A900959X B250 FM Module appears to be an 8-word by 3-bit memory prints drawn 3-2-67, checked 6/30/67, eng. approval 7/6/67 6 Fairchild U6A903059X (apparently a 4-bit memory chip) 13 TI SN7440N or Fairchild U6A900959X In order to interface TTL with DEC's negative logic, they used supply voltages of +1.8V and -3.0V. I expect that two B198 modules were needed for the KT10A dual protection/ relocation register option. The KM10 Fast Memory option presumably contained about 24 B250 modules, and at least one B199 decoder. Is anyone familiar with the Fairchild U6A9 series logic devices? Apparently they were TTL compatible. By comparison, the KI10 used several different kinds of RAM chips for the Fast Memory (accumulators) and the associative memory for the pager: M250 4 Bit 16 Word Memory prints drawn 11/12/70, checked 12/?/70, eng. approval 12-28-70 Uses one chip of type DEC9035, in a 36-pin DIP! The chip has 16 independent address lines, four data inputs, four data outputs, a chip select, and a write enable: address lines A0-A17 (octal) on pins 10-25 data inputs D0-D3 on pins 32-29 data outputs O0-O3 on pins 4, 5, 6, and 8 chip select on pin 26 write enable on pin 27 Vcc and GND on pins 28 and 9 M253 12 Bit 16 Word Memory prints drawn 1/4/71, checked ???, eng. approval ??? uses three DEC7489 16*4 RAM chips, appear to be normal SN7489 also uses one quarter of a DEC1074H00 quad NAND gate to invert the chip select, presumably this is a normal 74H00 M260 16 Word x 12 Bit Ass. Mem Cell prints drawn 1/9/71, checked 1-18-71, eng. approval 1/28/71 uses three DEC4102 chips (24-pin DIP), which are apparently a 16 word by four bit associative memory: D0-D3 inputs on pins 5-2 MAT0-3 outputs (open collector?) on pins 9-6 O0-O3 outputs on pins 13, 11, 14, and 15 MSK0-3 inputs on pins 20-23 A0-A3 inputs on pins 16-19 WR EN on pin 1 VCC, GND on pins 24, 12 pins 10 is no-connect? If anyone has information on the DEC9035, DEC4102, or Fairchild U6A903059X, I'd be very interested to hear about it. I'm especially curious as to whether the DEC9035 and DEC4102 had any industry equivalents, or whether they were custom made by or for DEC. ###### Message-ID: <3D5D7AF5.3EC1F8B0@nktelco.net> From: Chuck Dickman X-Mailer: Mozilla 4.78 [en] (X11; U; Linux 2.4.7-10 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10 Subject: Re: KA10 hardware surprise --- TTL Logic Families References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 17 Date: Fri, 16 Aug 2002 18:21:41 -0400 NNTP-Posting-Host: 63.238.117.229 X-Trace: news.uswest.net 1029536502 63.238.117.229 (Fri, 16 Aug 2002 17:21:42 CDT) NNTP-Posting-Date: Fri, 16 Aug 2002 17:21:42 CDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed.news.qwest.net!news.uswest.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:11740 My employer was experimenting with TTL in '68 and '69 for industrial controls. I have some chips to prove it. :-) Not surprising to hear that DEC snuck a few in. Eric Smith wrote: > 5 74H00N > 2 74H40N > 4 74H50N > 1 74H53N > 2 74H55N Can anyone provide info on the 74H00 family? I assume that it is the opposite of the 74L00 family, ie. smaller resistor values, therefore a little faster and a lot hotter. I have not seen any data sheets, so I am interested in substitution guidelines; something like: Faster than 7400 and slower than 74S00. My PDP-8/e has a few and I always wondered what to do if I toasted one. -chuck ###### Newsgroups: alt.sys.pdp10 Subject: Re: KA10 hardware surprise --- TTL Logic Families References: <3D5D7AF5.3EC1F8B0@nktelco.net> X-Newsreader: NN version 6.5.0 CURRENT #127 From: bugs@pu.net (Mark Hittinger) Message-ID: NNTP-Posting-Date: Fri, 16 Aug 2002 19:10:17 CDT Organization: Giganews.Com - Premium News Outsourcing Lines: 20 X-Trace: sv3-oCnw7eofwLgC+phlxvBQiZxVULKR82ZPB0X3dPmRZwMI207kQ/xsJnX37zVxrWB03+pFsUeQ4qq9DbP!t1RRlLQXjK+v35GRcFzhRZYss7iyMzdrsLPXtaktVB5Ga443NHPnFKiLyo+5TgNcONXtTXrqCXYM!+c93WFUWD3qjD3b23Q== X-Complaints-To: abuse@GigaNews.Com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.1 Date: Sat, 17 Aug 2002 00:10:18 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!snoopy.risq.qc.ca!newsfeed.news2me.com!border1.nntp.aus1.giganews.com!nntp.giganews.com!nntp3.aus1.giganews.com!bin3.nnrp.aus1.giganews.com.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:11752 Chuck Dickman writes: >Can anyone provide info on the 74H00 family? I assume that it is the opposite of >the 74L00 family, ie. smaller resistor values, therefore a little faster and a >lot hotter. I have not seen any data sheets, so I am interested in substitution >guidelines; something like: Faster than 7400 and slower than 74S00. My PDP-8/e >has a few and I always wondered what to do if I toasted one. max propogation power max input freq delay dissip current 74S 125mhz 3ns 19mW 50uA 74H 50mhz 6ns 22mW 50uA 74 35mhz 10ns 10mW 40uA The pinouts are the same. I'd bet an "S" part would work. The "LS" part has a max frequency of 45mhz so the "LS" are just a bit short of the "H". Later Mark Hittinger bugs@pu.net ###### From: Ben Franchuk Newsgroups: alt.sys.pdp10 Subject: Re: KA10 hardware surprise --- TTL Logic Families Date: Fri, 16 Aug 2002 22:21:48 -0600 Organization: Posted via Supernews, http://www.supernews.com Message-ID: User-Agent: Mozilla/5.0 (Windows; U; Win 9x 4.90; en-US; rv:1.1b) Gecko/20020721 X-Accept-Language: en,ja MIME-Version: 1.0 References: <3D5D7AF5.3EC1F8B0@nktelco.net> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: newsabuse@supernews.com Lines: 27 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!nntp-out.monmouth.com!newspeer.monmouth.com!cpk-news-hub1.bbnplanet.com!cambridge1-snf1.gtei.net!news.gtei.net!bos-service1.ext.raytheon.com!cyclone.swbell.net!newsfeed1.easynews.com!easynews.com!easynews!sn-xit-02!sn-xit-01!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:11746 Mark Hittinger wrote: > Chuck Dickman writes: > >>Can anyone provide info on the 74H00 family? I assume that it is the opposite of >>the 74L00 family, ie. smaller resistor values, therefore a little faster and a >>lot hotter. I have not seen any data sheets, so I am interested in substitution >>guidelines; something like: Faster than 7400 and slower than 74S00. My PDP-8/e >>has a few and I always wondered what to do if I toasted one. > > > max propogation power max input > freq delay dissip current > 74S 125mhz 3ns 19mW 50uA > 74H 50mhz 6ns 22mW 50uA > 74 35mhz 10ns 10mW 40uA > > The pinouts are the same. I'd bet an "S" part would work. The "LS" part has > a max frequency of 45mhz so the "LS" are just a bit short of the "H". > > Later > > Mark Hittinger > bugs@pu.net Looking on the web to find just what the specs are for the 74Hxx chips I found this site that may still have some in stock. http://www.unicornelectronics.com/74H.html ###### From: Paul Repacholi Newsgroups: alt.sys.pdp10 Subject: Re: KA10 hardware surprise Date: 19 Aug 2002 18:20:14 +0800 Organization: iQnet Lines: 17 Sender: prep@k9 Message-ID: <87it272lr5.fsf@prep.synonet.com> References: NNTP-Posting-Host: news-01.core.usertools.net Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: nnrp.waia.asn.au 1029765130 21970 202.154.80.9 (19 Aug 2002 13:52:10 GMT) X-Complaints-To: usenet@nnrp.waia.asn.au NNTP-Posting-Date: Mon, 19 Aug 2002 13:52:10 +0000 (UTC) User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.2 Cache-Post-Path: angelina!unknown@p001.qv1-01.dial.usertools.net X-Cache: nntpcache 2.3.3 (see http://www.nntpcache.org/) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!howland.erols.net!nntp-out.news.gblx.net.MISMATCH!nntp1.phx1.gblx.net!nntp.gblx.net!nntp.gblx.net!newsfeed.news2me.com!skynet.be!skynet.be!newsfeed.iinet.net.au!nntp.waia.asn.au!nnrp.waia.asn.au!127.0.0.1!nobody Xref: chonsp.franklin.ch alt.sys.pdp10:11759 Eric Smith writes: > M253 12 Bit 16 Word Memory > prints drawn 1/4/71, checked ???, eng. approval ??? > uses three DEC7489 16*4 RAM chips, appear to be normal SN7489 > also uses one quarter of a DEC1074H00 quad NAND gate to > invert the chip select, presumably this is a normal 74H00 I suspect the DEC1074H00 is a selected chip, like the ones used in the 11/40 that are there to prevent glitches. -- Paul Repacholi 1 Crescent Rd., +61 (08) 9257-1001 Kalamunda. West Australia 6076 Raw, Cooked or Well-done, it's all half baked. EPIC, The Architecture of the future, always has been, always will be. ###### Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: alt.sys.pdp10 Subject: Re: KA10 hardware surprise References: <87it272lr5.fsf@prep.synonet.com> Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 19 Aug 2002 08:47:12 -0700 Message-ID: Lines: 5 User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: 209.66.107.17 X-Trace: 19 Aug 2002 09:08:40 -0700, 209.66.107.17 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!zen.net.uk!news.teledanmark.no!uninett.no!uio.no!logbridge.uoregon.edu!arclight.uoregon.edu!enews.sgi.com!news.spies.com!209.66.107.17 Xref: chonsp.franklin.ch alt.sys.pdp10:11760 Paul Repacholi writes: > I suspect the DEC1074H00 is a selected chip, like the ones used in the > 11/40 that are there to prevent glitches. Some 74H00 NAND gates produce glitches??? How do they manage to do that? ###### From: Paul Repacholi Newsgroups: alt.sys.pdp10 Subject: Re: KA10 hardware surprise Date: 20 Aug 2002 23:55:19 +0800 Organization: iQnet Lines: 22 Sender: prep@k9 Message-ID: <87wuql1q54.fsf@prep.synonet.com> References: <87it272lr5.fsf@prep.synonet.com> NNTP-Posting-Host: news-01.core.usertools.net Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: nnrp.waia.asn.au 1029859112 26584 202.154.80.9 (20 Aug 2002 15:58:32 GMT) X-Complaints-To: usenet@nnrp.waia.asn.au NNTP-Posting-Date: Tue, 20 Aug 2002 15:58:32 +0000 (UTC) User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.2 Cache-Post-Path: angelina!unknown@p196.qv1-01.dial.usertools.net X-Cache: nntpcache 2.3.3 (see http://www.nntpcache.org/) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!feedme.news.mediaways.net!news.belwue.de!fu-berlin.de!news.maxwell.syr.edu!news1.optus.net.au!optus!news.uwa.edu.au!nntp.waia.asn.au!nnrp.waia.asn.au!127.0.0.1!nobody Xref: chonsp.franklin.ch alt.sys.pdp10:11763 Eric Smith writes: > Paul Repacholi writes: > > I suspect the DEC1074H00 is a selected chip, like the ones used in the > > 11/40 that are there to prevent glitches. > Some 74H00 NAND gates produce glitches??? How do they manage to do that? No, one (at least) of the 11/40 chips is selected for max metastable time, so a glitch condition does not occur. There are notes in the parts lists, and on the drawing to not use a standard 74 series chip, but to only use the 2-5-2 partnumbered one. I do not think it was a 7400 type in this case. I'd guess that the 74H00 is selected for some parameter. Not ness the same as the 40 chip, but a `don't use standard 74xx here' case again. -- Paul Repacholi 1 Crescent Rd., +61 (08) 9257-1001 Kalamunda. West Australia 6076 Raw, Cooked or Well-done, it's all half baked. EPIC, The Architecture of the future, always has been, always will be.