From: "David G. Conroy" Newsgroups: alt.sys.pdp10 Subject: an architectural question Organization: Used only for posts to newsgroups X-Newsreader: Microsoft Outlook Express Macintosh Edition - 4.5 (0410) Mime-version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Lines: 12 Message-ID: Date: Tue, 06 Nov 2001 05:29:55 GMT NNTP-Posting-Host: 64.171.4.17 X-Complaints-To: abuse@verio.net X-Trace: sea-read.news.verio.net 1005024595 64.171.4.17 (Tue, 06 Nov 2001 05:29:55 GMT) NNTP-Posting-Date: Tue, 06 Nov 2001 05:29:55 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!HSNX.atgi.net!sjc-peer.news.verio.net!news.verio.net!sea-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7382 I have PDP10 architectural question which I am sure one of the manuals answers, but I can't find it. If a program's dstream changes the contents of a memory location, what must it do to guarantee that the change is visible by the program's istream (and does the possibility of block operations make the rule different in cached and uncached parts of memory). dgc ###### From: jmfbahciv@aol.com Newsgroups: alt.sys.pdp10 Subject: Re: an architectural question Date: Tue, 06 Nov 01 11:48:25 GMT Organization: UltraNet Communications, Inc. Lines: 35 Message-ID: <9s8pik$c2t$8@bob.news.rcn.net> References: X-Trace: UmFuZG9tSVbcLyQ4NvNf+/VHenJMMkAmWxfjjvyN//EsJlauAyNeF9R+z6/fN6Kb X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 6 Nov 2001 13:45:56 GMT X-Newsreader: News Xpress Version 1.0 Beta #4 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!207-172-255-136 Xref: chonsp.franklin.ch alt.sys.pdp10:7379 In article , "David G. Conroy" wrote: >I have PDP10 architectural question which I am sure one of the manuals >answers, but I can't find it. I'm not sure I'll be able to help you. > >If a program's If you're talking about a program rather than an operating system, then you don't have to worry (unless you're BLTing). > ....dstream changes the contents of a memory >location, what must it do to guarantee that the change is visible by >the program's istream I don't know what you mean by dstream and istream. I read it as d[ata]stream and i[nput]stream but that didn't make any sense to me. > ...(and does the possibility of >block operations make the rule different in cached and uncached >parts of memory). On a PDP-10 (KL processor) TOPS-10 had to worry about that especially when there were two CPUs. I'd point you at source code but I'm pretty sure that the software level you're thinking of is above the software level that had to worry about the lack of a write-thru cache. /BAH Subtract a hundred and four for e-mail. ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: an architectural question Date: 06 Nov 2001 21:24:35 +0100 Organization: My own Private Self Lines: 62 Message-ID: <6un11zr6kc.fsf@chonsp.franklin.ch> References: <9s8pik$c2t$8@bob.news.rcn.net> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1005078275 429 10.0.3.2 (6 Nov 2001 20:24:35 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 6 Nov 2001 20:24:35 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:7388 jmfbahciv@aol.com writes: > In article , > "David G. Conroy" wrote: > > >I have PDP10 architectural question which I am sure one of the manuals > >answers, but I can't find it. Not seen it either so far. So I am assuming the worst: make sure it works, no matter what the software thier to screw up. > > ....dstream changes the contents of a memory > >location, what must it do to guarantee that the change is visible by > >the program's istream > > I don't know what you mean by dstream and istream. I read it > as d[ata]stream and i[nput]stream but that didn't make any > sense to me. Data and instruction streams. If I understand hin right, he is asking, what happens if an program writes to an memory word and then short after executes that word. Examples would be self-modifying code, or writing code into fast registers to then execute it. Given that Proc166, KA-10 and KI-10 had no cache (and the first two no instruction pipelining) I would assume that losts of code (particularly that doing code in registers) is oblivious to the existance of such effects. So caching (and pipelining) hardware will have to make sure that changes to memory are reflected in cache reloads. Same I suspect that writing memory that has already been prefectched by the instruction pipeline will have to lead to an pipeline flush. That translates to 80x86 style "worst case" semantics. No MIPS-like "the compiler will save us" luxury. > > ...(and does the possibility of > >block operations make the rule different in cached and uncached > >parts of memory). Most likely same strict "maintain illusion of sequential memory accesses" semantics. > I'd point you at source > code but I'm pretty sure that the software level you're thinking > of is above the software level that had to worry about the > lack of a write-thru cache. No. More likely way underneed that level. Seems that DGC is thinking on FPGA hardware designing. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### Newsgroups: alt.sys.pdp10 Subject: Re: an architectural question References: Organization: Chez Inwap From: inwap@best.com (Joe Smith) Lines: 42 Message-ID: Date: Wed, 07 Nov 2001 03:18:42 GMT NNTP-Posting-Host: 206.184.139.134 X-Complaints-To: abuse@verio.net X-Trace: sea-read.news.verio.net 1005103122 206.184.139.134 (Wed, 07 Nov 2001 03:18:42 GMT) NNTP-Posting-Date: Wed, 07 Nov 2001 03:18:42 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!newsfeed01.sul.t-online.de!t-online.de!newsfeed.media.kyoto-u.ac.jp!sjc-peer.news.verio.net!news.verio.net!sea-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7400 In article , David G. Conroy wrote: >I have PDP10 architectural question which I am sure one of the manuals >answers, but I can't find it. Please remember that the PDP-10 was designed back when computers used core instead of semiconductors for memory. Back when cache was not common. >If a program's dstream changes the contents of a memory >location, what must it do to guarantee that the change is visible by >the program's istream The PDP-10 has a single cache, not separate I and D caches. Any word written to memory is immediately available for instruction fetch by the PC. [Some processor designs that came after the KL gave up on optimizing self-modifying code in the accumulators. If an accumulator was modified, and then the PC fetched it as an instruction, it would work correctly, although there may be a 2x to 3x performance hit.] >(and does the possibility of block operations make the rule different >in cached and uncached parts of memory). From the single-CPU point of view, there is no difference between cached and uncached pages other than speed. From a multi-processor point of view, caching makes a big difference to other processors (which may be another KL, the RH20 disk/tape controller, etc). That is, the KL does not have cache coherency between processors; no address snooping. The KL has instructions to flush the entire cache and to flush a single page. But since it is known that the KL has four-way associative memory, there is a way to make sure a single location has been flushed to external memory. If the memory location is at xxxyyy, and read-only references are made to cached locations to zzzyyy, zzzyyy+1000, zzzyyy+2000 and zzzyyy+3000, then the last four locations will be pulled into cache. As a side effect, the data at zzzyyy will have been shoved out into external memory. -Joe -- See http://www.inwap.com/ for PDP-10 and "ReBoot" pages. ###### From: "David G. Conroy" Newsgroups: alt.sys.pdp10 Subject: Re: an architectural question References: Organization: Used only for posts to newsgroups X-Newsreader: Microsoft Outlook Express Macintosh Edition - 4.5 (0410) Mime-version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-transfer-encoding: 7bit Lines: 4 Message-ID: <2E3G7.3446$Le.84561@sea-read.news.verio.net> Date: Wed, 07 Nov 2001 05:28:30 GMT NNTP-Posting-Host: 66.123.170.93 X-Complaints-To: abuse@verio.net X-Trace: sea-read.news.verio.net 1005110910 66.123.170.93 (Wed, 07 Nov 2001 05:28:30 GMT) NNTP-Posting-Date: Wed, 07 Nov 2001 05:28:30 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newscore.univie.ac.at!194.25.134.126.MISMATCH!newsfeed01.sul.t-online.de!t-online.de!fr.clara.net!heighliner.fr.clara.net!news.tele.dk!small.news.tele.dk!144.212.100.101!newsfeed.mathworks.com!cyclone.swbell.net!easynews!sjc-peer.news.verio.net!news.verio.net!sea-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:7399 Thank you all. Mark actually answered the question I was asking, which (essentially) was "could software ever observe the presence or absence of prefetch buffers". I thought the answer was "no", but I thought I would check.