Message-ID: <3A866359.38EDF560@mail.bcpl.net> From: Ken McMonigal X-Mailer: Mozilla 4.61 [en] (Win98; I) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.sys.pdp10 Subject: warning - long post - Re: was interrupt processing; now - interest in multi-processing ? emulator & FPGA References: <3A764A09.8FEE136B@digiweb.com> <3A78E586.8864B7C7@MA.UltraNet.Com> <3A7D0848.29678A56@mail.bcpl.net> <95lkti$15d3$1@nntp1.ba.best.com> <95lun5$204$1@bob.news.rcn.net> <3A859F62.4E6D22B@MA.UltraNet.Com> <3A85EC42.D2118443@MA.UltraNet.Com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 307 Date: Sun, 11 Feb 2001 05:03:05 -0500 NNTP-Posting-Host: 207.19.142.55 X-Complaints-To: abuse@bcpl.net X-Trace: news.abs.net 981885600 207.19.142.55 (Sun, 11 Feb 2001 05:00:00 EST) NNTP-Posting-Date: Sun, 11 Feb 2001 05:00:00 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!newsfeed.mathworks.com!feeder.qis.net!nntp.abs.net!news.abs.net!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2931 "Alan H. Martin" wrote: > > Eric Smith wrote: > > > > "Alan H. Martin" writes: > > >... Could someone take a look at the list of 7.04 ANF monitor > > > source files at: > > > > > > http://pdp-10.trailing-edge.com/pdp-10/TOPS10_704_MONITORANF_BB-X140C-SB.HTML > > > > > > and *please* tell me where all the SMP code lives? ... > > > > It lives in SMPSER.MAC, which was unbundled. > > AFAIK, no one has turned up a copy. :-( > > Dang, that sucks. > /AHM/THX > -- > Alan Howard Martin AMartin@MA.UltraNet.Com *** I apologize in advance for this long & complicated post - too much cola/caffeine keeping me up *** To all interested: Is this line of thought due to a desire to have a repository of -10 software that is fairly complete over the product life cycle? Or is it that there is an interest in having this software available for some of the new projects that could be developed once the emulator is released? (note - see my thoughts on a huge simulated -10 multiprocessor system configured as a torus) Are there are very many dual-processor hardware systems out there running? I don't know if Barb is the one that knows this, but what kinds & how many systems shipped that had multiple processors? And what models were there besides the DECSystem-10's noted in my earlier post - the model 1055 (2 KA-10's) & the model 1077 (2 KI10's) ? I assume there were DECSystem-20's (?) for the KL/KS. Model numbers, please? Were there any weird or large configurations that went out? I know that Barb had mentioned that the Rpxx (?) hard drive limitation had resulted in DEC not being able to quote a job for a big insurance company, IIRC. But did DEC send out any large/unique multi-processor systems to the big government labs or those D.C. government agencies that went by initials (and may be monitoring newsgroups as we "speak" - interesting sidebar later) ? I realize the system boxes themselves had the "limitation" of 2 processors, but did any systems ship that used some communication technique that allowed for multiple systems to be connected via Decnet or whatever? In my limited reference book, I see that there is a communications control unit on the back bus of the master processor that could be linked to up to 127 terminals. Was something like this device ever used to hang another -10 box that communicated in serial to the first box? ------------------------------------------------------------------------------------------ Software Thoughts ------------------------------------------------------------------------------------------ A) Emulation thread thoughts: 1) With Mr. Stark's emulator, one could possible have an emulated -10 that runs much faster than 1 MIPS (which was the spec for one of the processors, IIRC). Will the emulator be throttled back to more accurately reflect the actual speed of the original machine? 2) As I'm thinking, I realize that although I have very little any-nix OS experience, I could see Mr. Stark running more than one emulated -10 in different "windows" (excuse me - the equivalent in Unix). Am I wrong on this? I know that that would be way down the road from where the group is now. But since I have seen a fair amount of discussion/interest in -10 SMP recently by several people, I thought that I would ramble a bit on the subject. And this could lead to multiple setups in which multiple dual-processors could communicate over emulated (internal) Decnet/Telnet to each other (I'm just spit-balling this). Could one have multiple -10's run (under emulation) on Mr. Stark's Unix box at the same time? If it was to be a true emulation, as I have seen suggested in other posts, then the -10 would be a 1 MIPS machine (approximately). If Mr. Stark's Unix box runs at say 500 MHZ, this might allow for possibly as many as 100 Dec-10's running inside his box. I admit that I very little knowledge of emulators other than conceptual, but could the emulator be re-entrant or essentially a time-sharing system where the emulator is a pseudo-main-frame that services multiple -10's, that are inferior emulator jobs, on a time-slice basis? IIRC, Unix has provisions in the OS/kernel for this. Yes? When I worked on the -10, I essentially only ran one "process" at a time. Well, it's late & my Tenex manual is a little weak on describing some things, but it did mention in Telnet that you could create an inferior EXEC under Telnet. Forgive my brain/memory lapse, but you folks all know all about the -10 having the ability to create inferior jobs/forks/etc. So, I would envision the Unix box, with a possibly modified emulator, running a main process & then having equal inferior processes that represent the 100 emulated Dec-10's communicating through emulated Decnets (or whatever). (Discussion of I/O bottlenecks much later) This could allow for some interesting new projects when Mr. Stark releases the emulator (no pressure). One could devise multiple Dec-10's that would never have been possible due to cost. One could set up tests with extensions to the emulator that would evaluate the fastest/best configurations possible. One could possibly set up those 100 emu-10's (I'm going to copyright this phrase & everyone owes me a nickel per use of the phrase) as a torus as is typical in large multi-processor systems. ( Wait - they had that vaxen phrase which I hate(d) (sorry), so maybe I'll call the torus the "EmulaTen" (vs. emulation), ala Tenex) ------------------------------------------------------------------------------- Mr. Stark, is there a website/FAQ/status system for this project? I think you are doing a great job & this really cheers me up to see the -10 come back to life, so to speak (even if it's only a virtual reality). But if I can have a system that runs on my box that looks like a -10 ... well it's like if I could get back my dad's '65 Mustang convertible or having my old baseball card collection back. (Pardon my sentimentality) ------------------------------------------------------------------------------------------ Hardware Thoughts ------------------------------------------------------------------------------------------ B) FPGA project Since this is hardware, there are actual costs beyond the investments in our own PC's. I thought that I had read that there was a possibility of having more than one FPGA chip on the project board. Would this be a PCI board or what? So if one had 3 PCI slots available, what would be the maximum number of chips that would be possible? If there was more than one chip per board, would each chip be able to talk to another chip on that board, or would every chip only talk to the Pentium? I believe that there is a bus limitation of five PCI slots, as per the design specs/limitations, in the clones, IIRC. Yes? Is there a website/FAQ/status system for this project with someone having overall responsibility ala Linus Torvald that we can e-mail (infrequently)? ------------------------------------------------------------------------------------ For Paul Repacholi & the other FPGA posters: Keep up the good work (you & other team members). I was unfamiliar with company that implemented the -10 in FPGA & think it is an interesting concept. You have provided many good posts covering the chip-design software, as well as hardware considerations for the FPGA, that make the learning curve on this project much easier for those of us with little experience in this area. While I did hardware design using 8085/8086's & burned proms & used a system/bus analyzer, I've never designed/fused FPGA's. ((I assume they are the "glue" that is in some of the chips inside my box that route data around. Yes? I'm thinking of the "CHIPS" company that designed some "glue", IIRC, as well as SVGA controllers. Are some of their "glue" chips "FPGA"? And what is the difference with them & PAL's? Pardon all my questions/ignorance. )) I don't think that I would be able to contribute much, but I am very interested in the progress of this project. I have worked with suppliers to get quotes on batches of boards ranging from 10 to 100. Sometimes you can get the salesman to agree to give the discount rate for "n" boards/chips at whatever the breakpoint is,and take delivery of only a few periodically for cash flow purposes, as long as you agree to purchase the total number of items within the agreed upon period of time. But I'm sure you are probably aware of this. For my own edification, at some point could you briefly discuss the number of transistors in the AMD 2901 vs. the number of fuses (is that right nomenclature) in the FPGA that you are using? I'm assuming that the ultimate product will be smaller than the AMD2901. Yes? Is there a formula that relates "n" transistors to "m" fuses to understand the equivalent number of transistors in the FPGA? If you have already discussed this, could you give me a small hint & I will look it up on www.deja.com ? Thanks. Are there any preliminary specs on this chip/board ? What is the clock rate and MIPS? Any projections? Is the FPGA the latest generation or are you using one based on it just being the right size that you need (as I believe you posted earlier). So, is it an earlier generation chip that is slower than the state-of- th-art & cheaper as well ? Just wondering. ----------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------- I'd like to thank any readers for taking the time to wade through this rather long post. I hope I structured it enough that it made some sense. My intent was to just try to get some thoughts/juices flowing for myself & others on some of these projects. I feel a lot of frustration because my experiences don't overlap very much with a lot of the technical stuff discussed here. I wish I could dig out some of my old -10 stuff & am kicking my self because I'm pretty sure that I threw out one of those big telephone-book Fortran manuals with the light blue cover. The yellow one was for the -10 overview, IIRC. Yes? And I wish that I could be sitting here & reach up & look at some of the source code like Barb does. Unfortunately, my time is somewhat limited. So, I'll just end here & go into the bunker hoping that noone starts taking shots at me because I said something dumb or offensive. Sincerely, Ken (Logout?) ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: warning - long post - Re: was interrupt processing; now - interest in multi-processing ? emulator & FPGA Date: 12 Feb 2001 00:15:22 +0100 Organization: My own Private Self Lines: 278 Message-ID: <6usnlkolpx.fsf@chonsp.franklin.ch> References: <3A764A09.8FEE136B@digiweb.com> <3A78E586.8864B7C7@MA.UltraNet.Com> <3A7D0848.29678A56@mail.bcpl.net> <95lkti$15d3$1@nntp1.ba.best.com> <95lun5$204$1@bob.news.rcn.net> <3A859F62.4E6D22B@MA.UltraNet.Com> <3A85EC42.D2118443@MA.UltraNet.Com> <3A866359.38EDF560@mail.bcpl.net> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 981933322 1795 10.0.3.2 (11 Feb 2001 23:15:22 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 11 Feb 2001 23:15:22 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2944 Ken McMonigal writes: > Is this line of thought due to a desire to have a repository of > -10 software that is fairly complete over the product life cycle? > > Or is it that there is an interest in having this software available > for some of the new projects that could be developed once the emulator > is released? I assume both, depends on who is wanting the software. > And what models were there besides the DECSystem-10's noted in my > earlier post - > the model 1055 (2 KA-10's) & the model 1077 (2 KI10's) ? > > I assume there were DECSystem-20's (?) for the KL/KS. Model numbers, > please? There definitely existed dual-KLs. From: http://www.inwap.com/pdp10/models.txt 1050 KA10, multi user 1055 Dual processor (1050) system, master/slave configuration 1070 KI10, multi user 1077 Dual processor 1070, master/slave or symmetrical multiprocessing 1080 KL10-A(PA) running TOPS-10 1088 Dual processor (1080) system, SMP 1090 KL10-B(PA) or KL10-D(PV) running TOPS-10 1099 Multi processor (1090) system, SMP, TRI-SMP, QUAD-SMP Interestingly, these are alle DECsystem-10s. All mentioned -20s are single processor. Did TOPS-20 not support multi-processor?! Or are they simply missing? > I realize the system boxes themselves had the "limitation" of 2 > processors, > but did any systems ship that used some communication technique that > allowed > for multiple systems to be connected via Decnet or whatever? 1099 seems to habe had official 3 and 4 processor versions. IIRC someone said that Jupiter should have gone up to 16 processors (hmm, that may have been an large later PDP-11 discussion). > 1) With Mr. Stark's emulator, one could possible have an emulated > -10 that runs much faster than 1 MIPS (which was the spec for one of > the processors, IIRC). Will the emulator be throttled back to more > accurately reflect the actual speed of the original machine? IIRC Timothy once gave 1.7MIPS for his emulator on an PentiumII-800, after getting rid of all the system calls from the main loop. > experience, I could see Mr. Stark running more than one emulated -10 in > different "windows" (excuse me - the equivalent in Unix). At the price of them becoming slower (2 get 1/2 PC CPU, 3 get 1/3, ...). That is unless the Linux box running them has SMP. Dito for an SMP-PDP-10 emulator, that would need Linux SMTP and libpthreads (gulp!) programming. > I know that that would be way down the road from where the group is > now. Nope. Just start multiple TS-10s. Linux does the rest, grinding at 100% processor load. > Could one have multiple -10's run (under emulation) on Mr. Stark's Unix > box at the same time? You can, but you do not gain performance, unless you are using SMP Linux. That 1.7MIPS is an 800MHz PC running one TS-10 flat out, doing nothing else. > the -10 would be a 1 MIPS machine (approximately). If Mr. Stark's Unix > box > runs at say 500 MHZ, this might allow for possibly as many as 100 > Dec-10's > running inside his box. Nope. You have an massive loss in speed in emulators. The PC Processor is spending most of its time running the emulator, figuring out what to do. Only a small part (about 3-10%) of that is executiong the actual emulated PDP-10 data transformations, at multiple PC instructions for one PDP-10 instruction. I once wrote an 1MHZ 6502 emulator that just about filled an 25MHz 68040 processor: http://neil.franklin.ch/Projects/Soft64/ The Z80mu emulator ran an emulater Z80 at about 1/4MHz on an 4.77MHz 8088, despite being written in assembler. > but could the emulator be re-entrant or essentially a time-sharing > system where the emulator is a pseudo-main-frame that services multiple > -10's, that are inferior emulator jobs, on a time-slice basis? Normal Linux operation is to run each Emulator in one Linux Process. That gives automatic reentrancy to any program (by remapping the address space differently using the virtual memory system). So Timothy will surely not waste his time (and processor speed) duplicating reentrancy. > So, I would envision the Unix box, with a possibly modified emulator, > running a main process & then having equal inferior processes that > represent the 100 emulated Dec-10's communicating through emulated > Decnets (or whatever). Just start multiple TS-10s with some communication over TCP/IP (telnet->DZ11 converter). > One could possibly set up those 100 emu-10's (I'm going to copyright > this phrase > & everyone owes me a nickel per use of the phrase) as a torus as is > typical > in large multi-processor systems. Copyrighting only forbids people from copying your text verbatim. To prevent them using the idea you would need to get an patent on it (read: get the USPTO in Washington issue one to you, for about 10-20k$) and that will also only be valid in the U.S. Of course ring networks (remember IBM TokenRing?) and networked multi-computers (see Beowulf under Linux) are prior art, so if you try to enforce the patent you may get it declared invalid (depends on an law suit). > But if I can have a system that runs on my box that looks > like a -10 Look like an PDP-10? I suspect TS-10 to look like your typical PC (which it runs on). No blinkenlights there :-). [FPGA] > Since this is hardware, there are actual costs beyond the investments in > our own PC's. At precent ->estimate<- VGA monitor, PS/2 keyboard, about $300 processor/IO/tools (FPGA board), unknown for RAM, unknown for IDE or SCSI harddisk. Not to mention time soldering :-). > I thought that I had read that there was a possibility of having more > than > one FPGA chip on the project board. Would this be a PCI board or what? Presently I am aiming for an single-FPGA standalone boards (cheapest and good enough). Multi-processor (when I do it) will require an bigger FPGA or an multi-FPGA board. I prefer the former (no pin limitations, sharing some resources). > So if one had 3 PCI slots available, PCI seems to be an bitch to implement, so it is unlikely that I will ever do it. Also I have far more interest in doing Ethernet (possibly with an telnet->DZ11 hack) first. > Is there a website/FAQ/status system for this project http://neil.franklin.ch/Projects/PDP-10/ > with someone having > overall responsibility ala Linus Torvald that we can e-mail > (infrequently)? Me. And I also read this group, like Timothy does. :-) > ((I assume they are the "glue" that is in some of the chips inside my > box that route data around. Yes? PC chipsets are usually ASICs, not FPGAs. FPGA is used for smaller volumes where higher per-exemplar manufacturing cost does not matter relative to the per-exemplar share of development cost. PCs are outside that range. > I'm thinking of the "CHIPS" company that designed some "glue", IIRC, as > well as SVGA controllers. Are some of their "glue" chips "FPGA"? I assume you mean Chips&Technologies Inc. They are ASICs. My 386 PC is based on them, and has an broken CTI 82C206 chip in it :-(. > And what is the difference with them & PAL's? That is a big question. An short answer: PALs use an single grid of switch transistors, driving many-input AND gates followed by constant (8-16) input OR gates. Usually 4-20 OR gates. CPLDs are multi-grid (2-50 grids of each 16-20 ORs) PALs. FPGAs use an large array (8x8 to 150x150) of logic blocks, that each have 2 to 8 4-input universal logic elements (16 bit of ROM or RAM and an 16:1 MUX selecting by the 4 inputs), together with lots of "programmable circuit board" on chip to connect the blocks. ASCIs are an even larger (100-1000x100-1000) array of groups of 4 transistors that get wired in the last step of chip manufacture. That is why the user needs to work together with the production firm and must order batches from 1000 or even 10000 on upwards. > For my own edification, at some point could you briefly discuss the > number > of transistors in the AMD 2901 vs. the number of fuses (is that right > nomenclature) > in the FPGA that you are using? The XC2S200 chip I am presently aiming at uses an 28x42 array of blocks with each 2x2 logic elements (so 56x84=4704). It uses about 1000 "fuses" (actually SRAM bits) per block. Add to that 14 4kBit on-chip SRAMs. > I'm assuming that the ultimate product will be smaller than the AMD2901. > Yes? One PQ208 TQFP chip case, plus a bit of auxillary stuff (chip configuration at power up). I do not have the size handy. AMD2901 I have never seen, so I can not compare. But I think you need multiple of them to make an PDP-10 (KS-10 uses them) and lots of external logic (microcode store for one). > Is there a formula that relates "n" transistors to "m" fuses > to understand the equivalent number of transistors in the FPGA? In an SRAM based FPGA the dominant chip usage is the programmable interconnects at 6 transistors per interconnect point, so ca 900x6 x 28x42 = ca 6.3 mio. For SRAMs add 14 x 4096 x 6 = 340'000. Then add I/O and debugging, so I expect XC2S200 to be about 7-7.5mio transistors. > Are there any preliminary specs on this chip/board ? Chip: http://www.xilinx.com/partinfo/ds001.pdf (main page, follow links) Board: http://www.burched.com.au/bedspartan2.html (also follow CPU-IO link) > What is the clock rate and MIPS? Any projections? I am aiming for 30MHz (initially) to 100MHz (later). I expect that to give about 5-30 MIPS. > Is the FPGA the latest generation or are you using one based on it just > being the right size that you need (as I believe you posted earlier). About 5 year old technology, at its optimum price/performance point. I can work up to 4 times larger chips, but thats 10 times more expensive. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### From: inwap@best.com (Joe Smith) Newsgroups: alt.sys.pdp10 Subject: Re: warning - long post - Re: was interrupt processing; now - interest in multi-processing ? emulator & FPGA Date: 12 Feb 2001 10:28:07 GMT Organization: Chez Inwap Lines: 14 Message-ID: <968drn$2qp6$1@nntp1.ba.best.com> References: <3A764A09.8FEE136B@digiweb.com> <3A85EC42.D2118443@MA.UltraNet.Com> <3A866359.38EDF560@mail.bcpl.net> <6usnlkolpx.fsf@chonsp.franklin.ch> NNTP-Posting-Host: shell3.ba.best.com X-Trace: nntp1.ba.best.com 981973687 92966 206.184.139.134 (12 Feb 2001 10:28:07 GMT) X-Complaints-To: abuse@best.com NNTP-Posting-Date: 12 Feb 2001 10:28:07 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news.uni-stuttgart.de!rz.uni-karlsruhe.de!schlund.de!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!news.tele.dk!4.1.16.34!cpk-news-hub1.bbnplanet.com!news.gtei.net!feed2.news.rcn.net!rcn!news2.best.com!nntp1.ba.best.com!inwap Xref: chonsp.franklin.ch alt.sys.pdp10:2956 In article <6usnlkolpx.fsf@chonsp.franklin.ch>, Neil Franklin wrote: >Interestingly, these are alle DECsystem-10s. All mentioned -20s are >single processor. Did TOPS-20 not support multi-processor?! Or are >they simply missing? TOPS-20 never supported multiple CPUs sharing a single memory box. Instead, they had CFS, the Clustered File System. (Decades before Beowulf). I never used it, but I believe it was possible to have a job run on one CPU in the cluster, get swapped out, and resume on another processor. -Joe -- See http://www.inwap.com/ for PDP-10 and "ReBoot" pages. ###### Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: alt.sys.pdp10 Subject: Re: warning - long post - Re: was interrupt processing; now - interest in multi-processing ? emulator & FPGA References: <3A764A09.8FEE136B@digiweb.com> <3A78E586.8864B7C7@MA.UltraNet.Com> <3A7D0848.29678A56@mail.bcpl.net> <95lkti$15d3$1@nntp1.ba.best.com> <95lun5$204$1@bob.news.rcn.net> <3A859F62.4E6D22B@MA.UltraNet.Com> <3A85EC42.D2118443@MA.UltraNet.Com> <3A866359.38EDF560@mail.bcpl.net> X-Disclaimer: Everything I write is false. Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 12 Feb 2001 12:36:19 -0800 Message-ID: Lines: 157 User-Agent: Gnus/5.0807 (Gnus v5.8.7) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: ruckus.brouhaha.com X-Trace: 12 Feb 2001 12:37:02 -0800, ruckus.brouhaha.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!Amsterdam.Infonet!News.Amsterdam.UnisourceCS!skynet.be!newsfeed.direct.ca!look.ca!newshub2.rdc1.sfba.home.com!news.home.com!enews.sgi.com!news.spies.com!ruckus.brouhaha.com Xref: chonsp.franklin.ch alt.sys.pdp10:2970 Ken McMonigal writes: > Are there are very many dual-processor hardware systems out there > running? DECsystem-10s? Not any more. > I don't know if Barb is the one that knows this, but what kinds & how > many > systems shipped that had multiple processors? There were dual KA, KI, and KL machines. There were field-upgraded systems with three CPUs, maybe more. There were strange hybrids with multiple different CPU types, like the 166-KA-KL combo at Stanford. There were aftermarket mods to run multiprocessor KS systems. > And what models were there besides the DECSystem-10's noted in my > earlier post - > the model 1055 (2 KA-10's) & the model 1077 (2 KI10's) ? Except as a matter of historical interest, what DEC offered as standard and supported configurations mattered a lot less than what customers actually ran. Information on "sold" configurations is at: http://www.inwap.com/pdp10/models.txt > I assume there were DECSystem-20's (?) for the KL/KS. Model numbers, > please? See above. > Were there any weird or large configurations that went out? Yes. > I know that Barb had mentioned that the Rpxx (?) hard drive limitation > had resulted in DEC not being able to quote a job for a big insurance > company, > IIRC. Your point? On a single-processor KL, you could reasonably put up to 56 Massbus disk drives. Beyond that, if you had a KL with external I/O and memory busses, you could use external RH10s for more Massbus channels. There were also products from DEC and third parties to interface to IBM bus/tag disks. > I realize the system boxes themselves had the "limitation" of 2 > processors, I'm not sure about the 166, but I think the KA was the only processor that supported multiprocessing but was limited to two processors (due to only two settings for the vector offset). The KI and the external-memory KL could support as many processors as there were ports on the memory (typically four or eight). I'm not sure what the maximum number of processors supported by TOPS-10 was. > but did any systems ship that used some communication technique that > allowed > for multiple systems to be connected via Decnet or whatever? Yes. > In my limited reference book, I see that there is a communications > control > unit on the back bus of the master processor that could be linked to > up to 127 terminals. What "master procesor"? > Was something like this device ever used to hang another -10 box that > communicated > in serial to the first box? Until the CI20 and NIA20, serial was the ONLY way that loosely coupled -10s communicated. (Technically CI and ethernet are serial also, but you obviously weren't referring to those.) > 2) As I'm thinking, I realize that although I have very little any-nix > OS > experience, I could see Mr. Stark running more than one emulated -10 in > different "windows" (excuse me - the equivalent in Unix). > > Am I wrong on this? I can't imagine any reason why you couldn't run as many as you want, subject to resource limitations (host system memory, and disk space for drive images). > And this could lead to multiple setups in which multiple dual-processors > could > communicate over emulated (internal) Decnet/Telnet to each other > (I'm just spit-balling this). Simulating a dual-processor KL on a single-processor host is only interesting as an intellectual exercise; the performance would be lower than simulating a single-processor KL. On the other hand, it can be argued that ANY simulation of a PDP-10 is only interesting as an intellectual exercise. > Could one have multiple -10's run (under emulation) on Mr. Stark's Unix > box at the same time? I can't imagine why not. > If it was to be a true emulation, as I have seen suggested in other > posts, then the -10 would be a 1 MIPS machine (approximately). If > Mr. Stark's Unix box runs at say 500 MHZ, this might allow for > possibly as many as 100 Dec-10's running inside his box. You're suggesting a simulator that runs on commodity PC hardware and simulates more than one PDP-10 MIP per five native MHz, I think you're off by more than an order of magnitude. > I admit that I very little knowledge of emulators other than conceptual, > but could the emulator be re-entrant or essentially a time-sharing > system where the emulator is a pseudo-main-frame that services multiple > -10's, that are inferior emulator jobs, on a time-slice basis? > > IIRC, Unix has provisions in the OS/kernel for this. Yes? Most (all?) Unix variant allow the same executable to be shared between multiple independent processes, so that the memory footprint is shared. Is this what you're talking about? > Well, it's late & my Tenex manual is a little weak > on describing some things, but it did mention in Telnet that you > could create an inferior EXEC under Telnet. > > Forgive my brain/memory lapse, but you folks all know all about the -10 > having the ability to create inferior jobs/forks/etc. TOPS-20 is derived from Tenex and supports such things. Unix has similar concepts. Under TOPS-10, the closest approximation is the use of PTYs (e.g., OPSER). > B) FPGA project > > I'm assuming that the ultimate product will be smaller than the AMD2901. > Yes? Smaller in what sense? Certainly not in transistor count, gates, die size, or cost! > So, is it an earlier generation chip that is slower than the state-of- > th-art & cheaper as well ? Just wondering. Generally not. The older chips are built with larger process geometries. To a first approximation, chip cost is a function of die size. The cost of a newer chip implementing an equivalent function is less because it is smaller than the older chip it replaces. There are other factors that can outweigh this in the short run. But e.g., Xilinx Spartan II chips are fairly new (about a year old), yet much cheaper than older Xilinx parts that were less functional. ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: warning - long post - Re: was interrupt processing; now - interest in multi-processing ? emulator & FPGA Date: 13 Feb 2001 21:32:01 +0100 Organization: My own Private Self Lines: 36 Message-ID: <6uzofqcoji.fsf@chonsp.franklin.ch> References: <3A764A09.8FEE136B@digiweb.com> <3A78E586.8864B7C7@MA.UltraNet.Com> <3A7D0848.29678A56@mail.bcpl.net> <95lkti$15d3$1@nntp1.ba.best.com> <95lun5$204$1@bob.news.rcn.net> <3A859F62.4E6D22B@MA.UltraNet.Com> <3A85EC42.D2118443@MA.UltraNet.Com> <3A866359.38EDF560@mail.bcpl.net> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 982096321 612 10.0.3.2 (13 Feb 2001 20:32:01 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 13 Feb 2001 20:32:01 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2978 Eric Smith writes: > Ken McMonigal writes: > > > B) FPGA project > > > > I'm assuming that the ultimate product will be smaller than the AMD2901. > > Yes? > > Smaller in what sense? Certainly not in transistor count, gates, die > size, or cost! I agree with transistor count, gates and die size. But cost? Was a set (9?) of AMD2901s cheaper than $45 (what an XC2S200 costs)? > > So, is it an earlier generation chip that is slower than the state-of- > > th-art & cheaper as well ? Just wondering. > > Generally not. The older chips are built with larger process geometries. > To a first approximation, chip cost is a function of die size. The cost > of a newer chip implementing an equivalent function is less because it is > smaller than the older chip it replaces. There are other factors that > can outweigh this in the short run. But e.g., Xilinx Spartan II chips > are fairly new (about a year old), yet much cheaper than older Xilinx parts > that were less functional. Actually Spartan-II are process-reengineered versions of the lower end size Virtex chips. So about 4 years old. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### From: Arthur Krewat Newsgroups: alt.sys.pdp10 Subject: Re: warning - long post - Re: was interrupt processing; now - interest in multi-processing ? emulator & FPGA Organization: Kilonet.net Lines: 26 Message-ID: <3A89A184.C692DDC1@bartek.dontspamme.net> References: <3A764A09.8FEE136B@digiweb.com> <3A78E586.8864B7C7@MA.UltraNet.Com> <3A7D0848.29678A56@mail.bcpl.net> <95lkti$15d3$1@nntp1.ba.best.com> <95lun5$204$1@bob.news.rcn.net> <3A859F62.4E6D22B@MA.UltraNet.Com> <3A85EC42.D2118443@MA.UltraNet.Com> <3A866359.38EDF560@mail.bcpl.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7 [en] (X11; I; SunOS 5.8 i86pc) X-Accept-Language: en Date: Tue, 13 Feb 2001 21:05:49 GMT NNTP-Posting-Host: 167.206.68.16 X-Trace: news02.optonline.net 982098349 167.206.68.16 (Tue, 13 Feb 2001 16:05:49 EST) NNTP-Posting-Date: Tue, 13 Feb 2001 16:05:49 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!newshub2.rdc1.sfba.home.com!news.home.com!news-out.usenetserver.com!news-out.usenetserver.com!news01.optonline.net!news02.optonline.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2987 Rich Alderson wrote: > > >> Forgive my brain/memory lapse, but you folks all know all about the -10 > >> having the ability to create inferior jobs/forks/etc. > > > TOPS-20 is derived from Tenex and supports such things. Unix has similar > > concepts. Under TOPS-10, the closest approximation is the use of PTYs (e.g., > > OPSER). > > Tops-10 eventually supported user-accessible multi-forking (up to four per job) > at release 7.04; the impression I got was that it was not available any earlier > than that. The quickest and dirtiest way to do forks/threads was to run everything in a shareable high-seg and start up "children" by logging in a PTY, running the program and detaching. IIRC, there were other ways to launch other jobs, but the easiest (for me, at the time) was to use a PTY and DETACH it. This was under 6.03 TOPS-10. This allowed you to run as many threads as you needed. They all communicated using the shareable high-seg, and kept their private memory in the low-seg. I employed this method while developing WINDOW - a home-grown networking daemon. It used to bug the operator when he did a SYSTAT, too many WINDOWs! art k. ###### From: Rich Alderson Newsgroups: alt.sys.pdp10 Subject: Re: warning - long post - Re: was interrupt processing; now - interest in multi-processing ? emulator & FPGA Date: 13 Feb 2001 14:51:40 -0500 Organization: Systems Administration, XKL LLC, Redmond WA 98052 Lines: 26 Sender: alderson+news@panix3.panix.com Message-ID: References: <3A764A09.8FEE136B@digiweb.com> <3A85EC42.D2118443@MA.UltraNet.Com> <3A866359.38EDF560@mail.bcpl.net> <6usnlkolpx.fsf@chonsp.franklin.ch> <968drn$2qp6$1@nntp1.ba.best.com> NNTP-Posting-Host: panix3.panix.com X-Trace: news.panix.com 982093900 23612 166.84.0.228 (13 Feb 2001 19:51:40 GMT) X-Complaints-To: abuse@panix.com NNTP-Posting-Date: 13 Feb 2001 19:51:40 GMT X-Newsreader: Gnus v5.7/Emacs 20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!newsxfer.eecs.umich.edu!panix!news.panix.com!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2986 inwap@best.com (Joe Smith) writes: > TOPS-20 never supported multiple CPUs sharing a single memory box. > Instead, they had CFS, the Clustered File System. (Decades before Beowulf). > I never used it, but I believe it was possible to have a job run on > one CPU in the cluster, get swapped out, and resume on another processor. Actual name was "Common File System". 576-bit/sector RA81's, an HSC-50 or two, a star coupler, and a CI20 interface (took up two RH slots) on each KL. Came out with Tops-20 v6.0; we field tested that release at LOTS (3 2065 systems, and eventually a CI in the SC-30M). Each KL could have local disks as well as CFS; these could be configured to allow access from other KLs in the cluster, but that suffered the same problems as NFS version 1: No such thing as a soft mount--remote host dies, you hang till it comes back, and since Tops-20 hates hung systems, you die too. GALAXY had a new member added, called NEBULA. This allowed GALAXY to communi- cate around the cluster; I know that print requests were possible, but don't remember about batch--we didn't do a lot of batch on the heavily-loaded LOTS systems, too unfair to the students. -- Rich Alderson alderson+news@panix.com "You get what anybody gets. You get a lifetime." --Death, of the Endless ###### From: Rich Alderson Newsgroups: alt.sys.pdp10 Subject: Re: warning - long post - Re: was interrupt processing; now - interest in multi-processing ? emulator & FPGA Date: 13 Feb 2001 14:56:58 -0500 Organization: Systems Administration, XKL LLC, Redmond WA 98052 Lines: 18 Sender: alderson+news@panix3.panix.com Message-ID: References: <3A764A09.8FEE136B@digiweb.com> <3A78E586.8864B7C7@MA.UltraNet.Com> <3A7D0848.29678A56@mail.bcpl.net> <95lkti$15d3$1@nntp1.ba.best.com> <95lun5$204$1@bob.news.rcn.net> <3A859F62.4E6D22B@MA.UltraNet.Com> <3A85EC42.D2118443@MA.UltraNet.Com> <3A866359.38EDF560@mail.bcpl.net> NNTP-Posting-Host: panix3.panix.com X-Trace: news.panix.com 982094218 23612 166.84.0.228 (13 Feb 2001 19:56:58 GMT) X-Complaints-To: abuse@panix.com NNTP-Posting-Date: 13 Feb 2001 19:56:58 GMT X-Newsreader: Gnus v5.7/Emacs 20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!isdnet!grolier!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsxfer.eecs.umich.edu!panix!news.panix.com!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2988 Eric Smith writes: > Ken McMonigal writes: >> Forgive my brain/memory lapse, but you folks all know all about the -10 >> having the ability to create inferior jobs/forks/etc. > TOPS-20 is derived from Tenex and supports such things. Unix has similar > concepts. Under TOPS-10, the closest approximation is the use of PTYs (e.g., > OPSER). Tops-10 eventually supported user-accessible multi-forking (up to four per job) at release 7.04; the impression I got was that it was not available any earlier than that. -- Rich Alderson alderson+news@panix.com "You get what anybody gets. You get a lifetime." --Death, of the Endless