From: Hans B Pufal Newsgroups: alt.sys.pdp10 Subject: JRST instruction semantics Date: Sun, 07 Jan 2001 09:10:24 +0100 Organization: Wanadoo, l'internet avec France Telecom Lines: 57 Message-ID: <3A582470.459D97EC@digiweb.com> NNTP-Posting-Host: agrenoble-101-2-1-165.abo.wanadoo.fr Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: wanadoo.fr 978855140 5268 193.251.69.165 (7 Jan 2001 08:12:20 GMT) X-Complaints-To: abuse@wanadoo.fr NNTP-Posting-Date: 7 Jan 2001 08:12:20 GMT X-Mailer: Mozilla 4.75 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!newsfeed00.sul.t-online.de!newsfeed01.sul.t-online.de!t-online.de!fr.clara.net!heighliner.fr.clara.net!grolier!oleane.net!oleane!wanadoo.fr!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2460 First some background, I just had to do some hacking over the holiday period, so I downloaded Daniel Seagraves last release (thanks Daniel) and have done some restructuring of the code etc to the point where I can run the disgnostics programs in standalone mode. I use the SEQPARSE routine posted by Morton Reistad (thanks Morton) to load memory with the test code. I should admit (in shame) that I am developing under MShit Weeny-dows, but hopefully the code will port easily to other systems - I have separated out the system dependent stuff where ever I saw some. I found and corrected a number of problems and can now successfuly execute 10 out of the 13 basic test routines. Of the three that don't run, two are for the floating point instructions, most of wich are not yet implemented in Daniel's emulator (any volounters out there to to this?). The last test is the PI/APR/IOT test routine DSKAH.SEQ, which causes me a problem at the following instruction: 035267 254 00 1 00 035267 JRST @. ;LOOP The emulator loops trying to evaluate the effective address. As I, and the emulator, read this, the address is an indirect back to the instruction and so will loop, never completing the calulation of the effective address. Now, this instruction is in a test for interrupts and the comments seem to indicate that the intention is to put the processor into a "tight indirect loop" and to test wehther the processor can inerrupt out of that loop. My question is: Am I interpeting the instruction correctly? If so should interrupts be allowed during the effective address calculation? If they are what are the semantics? Is that instruction simply restarted form the top when the interrupt is dismissed? I have been unable to find any description in the Processor Reference Manual stating exactly when interrupts are allowed to occur. There are a few oblique references to allowing interrupts half way through instructions but nothing definitive. As usual all your help is greatly appreciated. Regards -- Hans P Pufal who has never seen nor used a PDP-10, but is looking forward to the day when he can. ###### From: rpw3@rigden.engr.sgi.com (Rob Warnock) Newsgroups: alt.sys.pdp10 Subject: Re: JRST instruction semantics Date: 7 Jan 2001 11:11:58 GMT Organization: Silicon Graphics Inc., Mountain View, CA Lines: 74 Message-ID: <939itu$mbguc$1@fido.engr.sgi.com> References: <3A582470.459D97EC@digiweb.com> NNTP-Posting-Host: rigden.engr.sgi.com X-Trace: fido.engr.sgi.com 978865918 23446476 163.154.34.115 (7 Jan 2001 11:11:58 GMT) X-Complaints-To: news@fido.engr.sgi.com NNTP-Posting-Date: 7 Jan 2001 11:11:58 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!fido.engr.sgi.com!rigden.engr.sgi.com!rpw3 Xref: chonsp.franklin.ch alt.sys.pdp10:2466 Hans B Pufal wrote: +--------------- | The last test is the PI/APR/IOT test routine DSKAH.SEQ, which causes me | a problem at the following instruction: | | 035267 254 00 1 00 035267 JRST @. ;LOOP | | The emulator loops trying to evaluate the effective address. As I, and | the emulator, read this, the address is an indirect back to the | instruction and so will loop, never | completing the calulation of the effective address. | | Now, this instruction is in a test for interrupts and the comments seem | to indicate that the intention is to put the processor into a "tight | indirect loop" and to test wehther the processor can inerrupt out of | that loop. | | My question is: Am I interpeting the instruction correctly? +--------------- If you mean should it be an infinite loop (if not interrupted), then "yes", that's correct. +--------------- | If so should interrupts be allowed during the effective address | calculation? +--------------- Yes. In fact, they must be allowed at *each* iteration (step) of an effective address calculation -- it is *not* enough to check for interrupts only once during the decode of an instuction. +--------------- | If they are what are the semantics? Is that instruction simply | restarted from the top when the interrupt is dismissed? +--------------- Exactly so... BUT... all side-effects must be supressed, to ensure that restartability. But actually, there's another more fundamental PDP-10 instruction set semantic constraint that helps here, namely, the rule that *NOTHING* an instruction does as a side-effect is allowed to affect its own effective address calculation. [Aside: Make sure your emulator obeys this for *all* instructions!!] This rule also comes in handy as a programmer when trying to remember exactly what instructions like "PUSHJ P,@(P)" or "POP P,-1(P)" or "AOBJN T2,@(T2)" do. ;-} ;-} IIRC, this constraint is mentioned only once, in passing, somewhere deep in the phonebook. At least, I'd been programming a PDP-10 for a couple of years before I saw it in writing and/or knew what it meant! ;-} +--------------- | I have been unable to find any description in the Processor Reference | Manual stating exactly when interrupts are allowed to occur. There are a | few oblique references to allowing interrupts half way through | instructions but nothing definitive. +--------------- I'm not 100% sure about before/during the fetch cycle [I *think* they're allowed there, too], but interrupts are definitely allowed between each step of an effective address calculation (where the addition of the address to the index register [of any] and the decision to indirect or not can all be considered one "step"), and between the last effective address calculation step and the "execute" step. -Rob ----- Rob Warnock, 31-2-510 rpw3@sgi.com SGI Network Engineering http://reality.sgi.com/rpw3/ 1600 Amphitheatre Pkwy. Phone: 650-933-1673 Mountain View, CA 94043 PP-ASEL-IA ###### From: Sean Case Newsgroups: alt.sys.pdp10 Subject: Re: JRST instruction semantics Organization: Marginal References: <3A582470.459D97EC@digiweb.com> User-Agent: MT-NewsWatcher/3.0 (PPC) Message-ID: Lines: 22 Date: Sun, 07 Jan 2001 22:22:29 +1100 NNTP-Posting-Host: 61.8.0.7 X-Complaints-To: news@pacific.net.au X-Trace: nostril.pacific.net.au 978866412 61.8.0.7 (Sun, 07 Jan 2001 22:20:12 EST) NNTP-Posting-Date: Sun, 07 Jan 2001 22:20:12 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!logbridge.uoregon.edu!newsxfer.interpacket.net!newsfeed.zip.com.au!61.8.0.119.MISMATCH!nostril.pacific.net.au!gsc Xref: chonsp.franklin.ch alt.sys.pdp10:2469 In article <3A582470.459D97EC@digiweb.com>, Hans B Pufal wrote: > should interrupts > be allowed during the effective address calculation? If they are what > are the semantics? Is that instruction simply restarted form the top > when the interrupt is > dismissed? Yes, that's it. Interrupts are allowed during effective address calculation, and the instruction is simply restarted from the beginning. The key to this is that effective address calculation never has any (user-visible) side effects, so it doesn't matter if you have to start over. Sean Case -- Sean Case gsc@zipworld.com.au Code is an illusion. Only assertions are real. ###### From: Hans B Pufal Newsgroups: alt.sys.pdp10 Subject: Re: JRST instruction semantics Date: Sun, 07 Jan 2001 12:46:57 +0100 Organization: Wanadoo, l'internet avec France Telecom Lines: 31 Message-ID: <3A585731.6EB3F0DA@digiweb.com> References: <3A582470.459D97EC@digiweb.com> NNTP-Posting-Host: agrenoble-101-2-1-165.abo.wanadoo.fr Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: wanadoo.fr 978868133 11144 193.251.69.165 (7 Jan 2001 11:48:53 GMT) X-Complaints-To: abuse@wanadoo.fr NNTP-Posting-Date: 7 Jan 2001 11:48:53 GMT X-Mailer: Mozilla 4.75 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!isdnet!195.25.12.36.MISMATCH!oleane.net!oleane!wanadoo.fr!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2461 Sean Case wrote: > > should interrupts > > be allowed during the effective address calculation? If they are what > > are the semantics? Is that instruction simply restarted form the top > > when the interrupt is > > dismissed? > > Yes, that's it. Interrupts are allowed during effective address > calculation, and the instruction is simply restarted from the beginning. > > The key to this is that effective address calculation never has any > (user-visible) side effects, so it doesn't matter if you have to start > over. Yes, I see that now. In writing my question, I clarified my own thinking and came up with the solution. Thanks also to Rob Warnock for his response. Well that seems to be working, now I have a different problem in the same test, the request flag is cleared and only one interrupt is invoked, the test expects to see 10 interrupts befroe exiting the loop. BTW I am willing to provide the emulator sources to anyone who wants to work on it, as I said earlier, it compiles under MS C++ under Weeny-Doze but should be relativly easy to modify for other compilers. I will do a full release once this test runs to completion and I have fixed a couple of UI glitches. -- Hans B Pufal ###### From: bugs@netcom.com (Mark Hittinger) Newsgroups: alt.sys.pdp10 Subject: Re: JRST instruction semantics Date: 7 Jan 2001 17:10:24 GMT Organization: MindSpring Enterprises Lines: 29 Message-ID: <93a7u0$i3p$1@slb2.atl.mindspring.net> References: <3A582470.459D97EC@digiweb.com> NNTP-Posting-Host: c7.ae.21.58 X-Newsreader: NN version 6.5.0 CURRENT #121 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!news-peer.gip.net!news.gsl.net!gip.net!news-out.usenetserver.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!news.mindspring.net!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:2476 Hans B Pufal writes: > Is that instruction simply restarted form the top >when the interrupt is >dismissed? Watch out here. You may want to research one of the processor status word bits (referred to in the documentation as "program flags". There is a bit called "first part done" that causes the instruction to not always restart from the beginning if there is an interrupt. The cases the documentation mentions are the byte pointer instructions where the byte pointer is incremented. I know there are other unmentioned cases, especially in the KL10 string (moan!) extended instructions that will be problematic. It isn't as easy as just restarting the instruction from the beginning during an interrupt. Now if you don't want to do true hardware emulation you can always just define when (most) interrupts are allowed to happen and never have to deal with the thorny issues. On the other hand there are cases like page faults, address breaks, and software induced interrupts which will have to cause interrupts within the intructions. I think these conditions will always occur immediately after the calculation of the effective address and the setting of the "first part done" flag. Later Mark Hittinger Earthlink bugs@netcom.com ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.sys.pdp10 Subject: Re: PDP-10 in an FPGA chip, starting (was Re: PC CRAP) Date: 07 Jan 2001 23:09:41 +0100 Organization: My own Private Self Lines: 56 Message-ID: <6uu27b6ml6.fsf@chonsp.franklin.ch> References: <3A3A338C.8DE7FFA5@bartek.net> <92h6pp$ql6$1@citadel.in.taronga.com> <92i6mi$ib$1@i4got.pechter.dyndns.org> <92i87u$1duf$1@citadel.in.taronga.com> <92jcoe$1nj$1@i4got.pechter.dyndns.org> <92kojt$csh$6@bob.news.rcn.net> <87r92p7wmq.fsf@k9.prep.synonet.com> <6un1dc9swv.fsf_-_@chonsp.franklin.ch> <871yuo2cck.fsf@k9.prep.synonet.com> <6u1yunntgs.fsf@chonsp.franklin.ch> <3A56EE3B.AC8B6336@jetnet.ab.ca> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 978905382 958 10.0.3.2 (7 Jan 2001 22:09:42 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 7 Jan 2001 22:09:42 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.sys.pdp10:2478 Ben Franchuk writes: > Neil Franklin wrote: > > > I am looking at fairly cheap 100'000 user gates chips for the > > beginning, particularly the XC2S200 at $50. > > That is 100'000 2 input gates I bet. Sure. To be more precise: for XC2S200 their marketing gives 200'000 (100'000 was a typo) 2-input (4 transistor) ASIC gate equivalents. Of these they calculate 63'000 gates for the core logic and the rest for the on-chip RAMs (14 * 256x16bit), IO stuff, ... > With what little I have > played with FPGA's a 4 input gate or bigger takes up 1 or more > logic blocks. Hard technical data is: An XC2S200 has 56x84 (= 4704) logic blocks of each: - 4-input LUT (= 16bit SRAM) - section of carry / long AND/OR chain (1 AND + 4 Muxes + 1 XOR) - direct input selector (1 Mux) - LUT combiner (1 Mux), allows paring LUTs to 5-input and 6-input - Flip-Flop for sequential logic - diverse routing resources to connect to other logic blocks An 1bit wide ADD/SUB/AND/OR 4-function ALU fits in 1 one logic block. Or an 1bit wide slice of 16 registers also, or in 2 logic blocks if you want dual read out for single cycle read-calc-write. Or 1bit of program counter with address incrementor. So they seem to be calculating about 60'000/4700 = 13 4-transistor gate-equivalents of average usage per logic block. Seems to be naming the upper limit of the realistic range. > A 10,000 gate chip (400 logic blocks) > would give you 100 12 input nand gates. Large NANDs can be had in XC2S200 at cost of adding inputs in steps of 4. So 1 12-input = 3 4-inputs -> 133 in an 400 logic block chip, or 1330 in an XC2S200. As I once said in this thread: logic to burn and not enough RAM for microcode. So that is why I am going for an KI, not an KL, initially. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### From: jmfbahciv@aol.com Newsgroups: alt.sys.pdp10 Subject: Re: JRST instruction semantics Date: Mon, 08 Jan 01 11:50:28 GMT Organization: UltraNet Communications, Inc. Lines: 32 Message-ID: <93cdm4$69j$6@bob.news.rcn.net> References: <3A582470.459D97EC@digiweb.com> X-Trace: UmFuZG9tSVYRqy+gWLvDr2SOMc251cDl6gqT+tvZSdVo76ABOHTZ0Hw0EEB9iCrj X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 8 Jan 2001 13:00:52 GMT X-Newsreader: News Xpress Version 1.0 Beta #4 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newscore.univie.ac.at!194.25.134.126.MISMATCH!newsfeed01.sul.t-online.de!t-online.de!newsfeed.germany.net!news.tele.dk!4.1.16.34!cpk-news-hub1.bbnplanet.com!news.gtei.net!feed2.news.rcn.net!feed1.news.rcn.net!rcn!207-172-245-224 Xref: chonsp.franklin.ch alt.sys.pdp10:2486 In article , Ric Werme wrote: >Sean Case writes: > >>The key to this is that effective address calculation never has any >>(user-visible) side effects, so it doesn't matter if you have to start >>over. > >Never say never! One of my first TOPS-20 programs made an indirect >list wind through more virtual memory than the system had physical. >Then it referenced the chain. If the system resumed the effective address >calculation the instruction would have finished, starting from the >beginning meant that it could not. > >This was on a KI-10 at the mill that ran TOPS-20. Being a KI, it was >entertaining watching how far effective address calculation got. All >in all, this was a highly user-visible side effect of a design >decision. :-) You always were a diabolical programmer. JMF marveled at your coroutine package. > >That particular system was being used by PC board designers >(PC=printed circuit, not personal computer!) working on automated >layout. Hah! I'd forgotten that flavor of PC. /BAH Subtract a hundred and four for e-mail. ###### From: inwap@best.com (Joe Smith) Newsgroups: alt.sys.pdp10 Subject: Re: JRST instruction semantics Date: 8 Jan 2001 06:12:01 GMT Organization: Chez Inwap Lines: 37 Message-ID: <93blnh$30ff$1@nntp1.ba.best.com> References: <3A582470.459D97EC@digiweb.com> NNTP-Posting-Host: shell3.ba.best.com X-Trace: nntp1.ba.best.com 978934321 98799 206.184.139.134 (8 Jan 2001 06:12:01 GMT) X-Complaints-To: abuse@best.com NNTP-Posting-Date: 8 Jan 2001 06:12:01 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!isdnet!howland.erols.net!feed2.news.rcn.net!rcn!news2.best.com!nntp1.ba.best.com!inwap Xref: chonsp.franklin.ch alt.sys.pdp10:2496 In article <3A582470.459D97EC@digiweb.com>, Hans B Pufal wrote: >The emulator loops trying to evaluate the effective address. As I, and >the emulator, read this, the address is an indirect back to the >instruction and so will loop, never >completing the calulation of the effective address. > >Now, this instruction is in a test for interrupts and the comments seem >to indicate that the intention is to put the processor into a "tight >indirect loop" and to test wehther the processor can inerrupt out of >that loop. That is correct. >should interrupts be allowed during the effective address calculation? Yes, interrupts are allowed after each fetch of an indirect word. >If they are what are the semantics? Is that instruction simply restarted >form the top when the interrupt is dismissed? Yes. For BLT, first put the updated pointer back into the AC so that restarting the instruction will restart where the block transfer left off. Same for EXTENDed string moves. ILDB/IDPB are handed specially, by using the FirstPartDone flag. >I have been unable to find any description in the Processor Reference >Manual stating exactly when interrupts are allowed to occur. There are a >few oblique references to allowing interrupts half way through >instructions but nothing definitive. If you understand that interrupt are allowed in the middle of EA calc and in the middle of ILDB or IDPB, then no more details are required. -Joe -- See http://www.inwap.com/ for PDP-10 and "ReBoot" pages.