Newsgroups: comp.arch,alt.folklore.computers
Subject: Antiquity of Byte-Word addressing?
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I'm under the impression that, with the notable exception of the 7030
STRETCH, IBM S/360 was the first line of machines to address memory by
the byte, but to also have a word (and halfword and double word) 
structure.  Was there anything earlier?

All the earlier machines I'm aware of were either word addressed, and
used some subsidiary mechanism to pick characters out of words, or were
character addressed and "variable word length" having no fixed word
concept.  (Although there may have been memory words of large than one
character, hidden from the programmer.)

######

From: jmfbahciv@aol.com
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Subject: Re: Antiquity of Byte-Word addressing?
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[spit]

In article <3E57531C.F30E88B1@yahoo.com>,
   Peter Flass <peter_flass@yahoo.com> wrote:
>Glen Herrmannsfeldt wrote:
>> > The IBM 1620 was also "byte" oriented (then, they were called decimal
>> > digits, as the machine as a BCD --- binary coded decimal machine).
>> >
>> > The IBM 14xx computer series were also of the same addressing type.
>> 
>> I thought both the 1620 and 14xx were variable word length machines.  I
>> don't know if I have a book that says it, though.
>> 
>> Before S/360 there were scientific (word addressed) and commercial 
(variable
>> length, likely decimal) machines.  S/360 was supposed to do both well, 
and
>> supplied fixed length binary operations and variable length decimal
>> operations.
>
>Right.  The 1620 and 14xx machines used a "word mark" bit to flag the
>character that was the end of the field.

Yea, but I don't remember being able to cross word boundaries;
I never thought of a 1620 as a byte-addressing machine.

<snip>

/BAH

Subtract a hundred and four for e-mail.

######

From: jmfbahciv@aol.com
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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[spit]

In article <uvfzcl86o.fsf@dtpq.com>,
   cstacy@dtpq.com (Christopher C. Stacy) wrote:
>The PDP-10 is word-addressed machine, but it has what are called 
>"byte pointers", which are not an addressing mode, but which are
>used with several instructions

One instruction.  

> ... to load bytes into registers.

There was also an instruction that deposit a byte from a
register to memory.

>A byte pointer can specify an arbitrary width byte and an offset
>into a word.  The most useful instruction is ILDB, which will
>increment the byte pointer to point to the next byte and load
>that byte into a register.  (There are also instructions for
>loading without incrementing, adjusting without loading, etc.)
>
And the parallel depositing instructions.

/BAH

Subtract a hundred and four for e-mail.

######

From: jmfbahciv@aol.com
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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In article <85ptpjfct8.fsf@junk.nocrew.org>,
   Lars Brinkhoff <lars.spam@nocrew.org> wrote:
>jmfbahciv@aol.com writes:
>> Christopher C. Stacy wrote:
>> > The PDP-10 is word-addressed machine, but it has what are called
>> > "byte pointers", which are not an addressing mode, but which are
>> > used with several instructions
>> One instruction.  
>
>How about these five: LDB, DPB, ILDB, IDPB, IBP?  Six if you include
>ADJBP, which use the same opcode as IBP and wasn't in the original
>PDP-10.

Reread Stacy's post.  I merely meant to clarify that one did NOT
have to do several instructions in order to load one byte.  It
took an instruction at the beginning to establish the byte pointer;
then, after that, only one ILDB (or LDB) had to be executed in order
to get a byte into the register.

Another little piece of really useful stuff was that you could
also do indirection and indexing.  Now that was sexy :-).

>
>Then there are the string instructions, but let's not go there.
>
Whew!  We escaped!  ;-)

/BAH

Subtract a hundred and four for e-mail.

######

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Subject: Re: Antiquity of Byte-Word addressing?
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[spit]

In article <zPR5a.753$cD5.88031@newsread2.prod.itd.earthlink.net>,
   haynes@alumni.uark.edu (Jim Haynes) wrote:
>In article <3E57531C.F30E88B1@yahoo.com>,
>Peter Flass  <peter_flass@yahoo.com> wrote:
>>"Hybrids", like Univac, SDS/XDS, etc.  I think the Burroughs systems
>>(5500, etc.) were both byte and word addressable.  ISTR you could add
>The B5500 had two different architectures in the same machine.  It was
>basically word addressable; then there was a subsidiary mechanism to
>make it into a variable-field-length character machine.  But it didn't
>have what I'm asking about, which is a machine address to the byte level
>but which also recognizes things larger than a byte as words.
>
>The IBM 1620 fits my example of a variable field length machine in
>which there was a word more-or-less hidden from the programmer; its
>memory size was two characters wide but you didn't have to know this
>to program it.

I sure needed to know that (note that I didn't do much
progamming on the 1620--only student flavored stuff).  
My memory must be very decrepit.  I do recall that it was very
difficult to "convert" my instruction thinking from a 1620 to
a PDP-10 because a number no longer needed "two" places.

/BAH

Subtract a hundred and four for e-mail.

######

From: "GerardS" <GerardS@PrairieTech.Net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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| Jim Haynes wrote:
| I'm under the impression that, with the notable exception of the 7030
| STRETCH, IBM S/360 was the first line of machines to address memory by
| the byte, but to also have a word (and halfword and double word)
| structure.  Was there anything earlier?
|
| All the earlier machines I'm aware of were either word addressed, and
| used some subsidiary mechanism to pick characters out of words, or were
| character addressed and "variable word length" having no fixed word
| concept.  (Although there may have been memory words of large than one
| character, hidden from the programmer.)

The IBM 1620 was also "byte" oriented (then, they were called decimal
digits, as the machine as a BCD --- binary coded decimal machine).

The IBM 14xx computer series were also of the same addressing type.
____________________________________________________________Gerard S.

######

From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
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"GerardS" <GerardS@PrairieTech.Net> wrote in message
news:v5dtgeq9snuj67@corp.supernews.com...
> | Jim Haynes wrote:
> | I'm under the impression that, with the notable exception of the 7030
> | STRETCH, IBM S/360 was the first line of machines to address memory by
> | the byte, but to also have a word (and halfword and double word)
> | structure.  Was there anything earlier?
> |
> | All the earlier machines I'm aware of were either word addressed, and
> | used some subsidiary mechanism to pick characters out of words, or were
> | character addressed and "variable word length" having no fixed word
> | concept.  (Although there may have been memory words of large than one
> | character, hidden from the programmer.)
>
> The IBM 1620 was also "byte" oriented (then, they were called decimal
> digits, as the machine as a BCD --- binary coded decimal machine).
>
> The IBM 14xx computer series were also of the same addressing type.

I thought both the 1620 and 14xx were variable word length machines.  I
don't know if I have a book that says it, though.

Before S/360 there were scientific (word addressed) and commercial (variable
length, likely decimal) machines.  S/360 was supposed to do both well, and
supplied fixed length binary operations and variable length decimal
operations.

-- glen

######

From: "GerardS" <GerardS@PrairieTech.Net>
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| Glen Herrmannsfeldt wrote:
|> GerardS wrote:.
|>| Jim Haynes wrote:
|>| I'm under the impression that, with the notable exception of the 7030
|>| STRETCH, IBM S/360 was the first line of machines to address memory by
|>| the byte, but to also have a word (and halfword and double word)
|>| structure.  Was there anything earlier?
|>|
|>| All the earlier machines I'm aware of were either word addressed, and
|>| used some subsidiary mechanism to pick characters out of words, or were
|>| character addressed and "variable word length" having no fixed word
|>| concept.  (Although there may have been memory words of large than one
|>| character, hidden from the programmer.)
|>
|> The IBM 1620 was also "byte" oriented (then, they were called decimal
|> digits, as the machine as a BCD --- binary coded decimal machine).
|>
|> The IBM 14xx computer series were also of the same addressing type.
|
| I thought both the 1620 and 14xx were variable word length machines.  I
| don't know if I have a book that says it, though.

Yes, they are considered a variable word length machine.  The "word" was "byte" addressable, however, but a variable field or record
would be a
better description than "word", as we now tend to associate a word with a fixed width.  "Variable word length" and "byte
addressable" are not mutually exclusive.

I have my old college book "Basic Programming Concepts and the IBM 1620 Computer" by Daniel N. Leeson and Donald L. Dimitry (c)
1962.  The book was
written for the IBM 1620 model I.

It was the first computer that I cut my teeth on.  It was incredibly easy
to program and it took the IBM 360 quite a few years to suppass the amount
of sofware written for/on the IBM 1620. __________________________Gerard S.




| Before S/360 there were scientific (word addressed) and commercial variable
| length, likely decimal) machines.  S/360 was supposed to do both well, and
| supplied fixed length binary operations and variable length decimal
| operations.

######

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Glen Herrmannsfeldt wrote:
> > The IBM 1620 was also "byte" oriented (then, they were called decimal
> > digits, as the machine as a BCD --- binary coded decimal machine).
> >
> > The IBM 14xx computer series were also of the same addressing type.
> 
> I thought both the 1620 and 14xx were variable word length machines.  I
> don't know if I have a book that says it, though.
> 
> Before S/360 there were scientific (word addressed) and commercial (variable
> length, likely decimal) machines.  S/360 was supposed to do both well, and
> supplied fixed length binary operations and variable length decimal
> operations.

Right.  The 1620 and 14xx machines used a "word mark" bit to flag the
character that was the end of the field.  I'm trying to think of another
example.  Even after the 360, most machines remained word-addressable
with special instructions to access individual bytes within a word. 
"Hybrids", like Univac, SDS/XDS, etc.  I think the Burroughs systems
(5500, etc.) were both byte and word addressable.  ISTR you could add
two strings of ASCII characters.  Worked fine when both were numeric,
but would happily add alphameric data as well and produce odd-looking
results.

######

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The PDP-10 is word-addressed machine, but it has what are called 
"byte pointers", which are not an addressing mode, but which are
used with several instructions to load bytes into registers.
A byte pointer can specify an arbitrary width byte and an offset
into a word.  The most useful instruction is ILDB, which will
increment the byte pointer to point to the next byte and load
that byte into a register.  (There are also instructions for
loading without incrementing, adjusting without loading, etc.)

######

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Why the past tense?

I'm logged into a PDP-10 right now.
Running EMACS.
Written in TECO.

######

From: "GerardS" <GerardS@PrairieTech.Net>
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| jmfbahciv wrote:
|> Peter Flass wrote:
|>>Glen Herrmannsfeldt wrote:
|>>> The IBM 1620 was also "byte" oriented (then, they were called decimal
|>>> digits, as the machine as a BCD --- binary coded decimal machine).
|>>>
|>>> The IBM 14xx computer series were also of the same addressing type.
|>>
|>> I thought both the 1620 and 14xx were variable word length machines.  I
|>> don't know if I have a book that says it, though.
|>>
|>> Before S/360 there were scientific (word addressed) and commercial (variable
|>> length, likely decimal) machines.  S/360 was supposed to do both well, and
|>> supplied fixed length binary operations and variable length decimal
|>> operations.
|>
|> Right.  The 1620 and 14xx machines used a "word mark" bit to flag the
|> character that was the end of the field.
|
| Yea, but I don't remember being able to cross word boundaries;
| I never thought of a 1620 as a byte-addressing machine.
| <snip>

Well, a "word" (more correctly called a field within most 1620 books) is
never aligned on a boundry (like the IBM 360 words were).  A "word"
(or field) was addressable by its decimal location (in the IBM 1620).  It
was only called a word in a very general sense, that is, it was comprised
of two or more digits.  The IBM 1620 could move multiple words (or fields)
which were call records, and the TR (transmit record) instruction was
used to accomplish this.  There was also a TD (transmit digit) to handle
one digit (or byte, if you will).  Remember, the IBM 1620 was a BCD (binary
coded decimal) machine and each digit had 6 bits (internally), 4 for
the numerical digit (in decimal), a flag bit (to indicate the end of the
field), and a check bit (for parity).  The only bit that a programmer
could set/reset was the flag bit, the numerical bits were only changeable
by "storing/setting" all numeric bits in unison.  It should be noted that
the word "byte" was never used, instead, "position" or "location of field"
was used. ________________________________________________________Gerard S.

######

From: Terje Mathisen <terje.mathisen@hda.hydro.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Sat, 22 Feb 2003 21:41:47 +0100
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Peter Flass wrote:
> Glen Herrmannsfeldt wrote:
> 
>>>The IBM 1620 was also "byte" oriented (then, they were called decimal
>>>digits, as the machine as a BCD --- binary coded decimal machine).
>>>
>>>The IBM 14xx computer series were also of the same addressing type.
>>
>>I thought both the 1620 and 14xx were variable word length machines.  I
>>don't know if I have a book that says it, though.
>>
>>Before S/360 there were scientific (word addressed) and commercial (variable
>>length, likely decimal) machines.  S/360 was supposed to do both well, and
>>supplied fixed length binary operations and variable length decimal
>>operations.
> 
> 
> Right.  The 1620 and 14xx machines used a "word mark" bit to flag the
> character that was the end of the field.  I'm trying to think of another
> example.  Even after the 360, most machines remained word-addressable

The HP 8-bit lab computers (HP-85 and HP-87, around 1981) used a 
veriable length register: There were 64 (?) individual 8-bit registers, 
which could be addressed and used individually.

The first half contained implied boundaries between every pair of 
registers, the second half had those between every 8 registers.

The 'word' form of operations would start at the indicated register, and 
go on until the next boundary. All the asm code I saw and wrote for them 
used only 16 and 64-bit versions though.

Terje

-- 
- <Terje.Mathisen@hda.hydro.com>
"almost all programming can be viewed as an exercise in caching"

######

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In article <3E57531C.F30E88B1@yahoo.com>,
Peter Flass  <peter_flass@yahoo.com> wrote:
>"Hybrids", like Univac, SDS/XDS, etc.  I think the Burroughs systems
>(5500, etc.) were both byte and word addressable.  ISTR you could add
The B5500 had two different architectures in the same machine.  It was
basically word addressable; then there was a subsidiary mechanism to
make it into a variable-field-length character machine.  But it didn't
have what I'm asking about, which is a machine address to the byte level
but which also recognizes things larger than a byte as words.

The IBM 1620 fits my example of a variable field length machine in
which there was a word more-or-less hidden from the programmer; its
memory size was two characters wide but you didn't have to know this
to program it.

######

From: "GerardS" <GerardS@PrairieTech.Net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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| Jim Haynes wrote:
|> Peter Flass yahoo.com> wrote:
|>> Hybrids wrote:
| I think the Burroughs systems
| (5500, etc.) were both byte and word addressable.  ISTR you could add
| The B5500 had two different architectures in the same machine.  It was
| basically word addressable; then there was a subsidiary mechanism to
| make it into a variable-field-length character machine.  But it didn't
| have what I'm asking about, which is a machine address to the byte
| level but which also recognizes things larger than a byte as words.
|
| The IBM 1620 fits my example of a variable field length machine in
| which there was a word more-or-less hidden from the programmer; its
| memory size was two characters wide but you didn't have to know this
| to program it.

No, the word size wasn't two characters wide.  You're confusing the fact
that a character (to be punched, printed, etc) was two decimal digits.
There was nothing in the IBM 1620 instruction set that handled anything
two characters wide as a primative.  Nothing was hidden from the
programmer as it was a very simple machine architecture wise.  It was
very easy to program for that reason. _______________________Gerard S.

######

From: "Edward A. Feustel" <efeustel@erols.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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"Christopher C. Stacy" <cstacy@dtpq.com> wrote in message
news:uvfzcl86o.fsf@dtpq.com...
> The PDP-10 is word-addressed machine, but it has what are called
> "byte pointers", which are not an addressing mode, but which are
> used with several instructions to load bytes into registers.
> A byte pointer can specify an arbitrary width byte and an offset
> into a word.  The most useful instruction is ILDB, which will
> increment the byte pointer to point to the next byte and load
> that byte into a register.  (There are also instructions for
> loading without incrementing, adjusting without loading, etc.)
>
As I recall:
The Burroughs B5000 line of machines had descriptors that could address a
group
of words or characters and an index instruction that would take an integer
index and
fetch, store, etc. the ith word or character.
I can look it up in the manual if it is important.
Ed

######

From: Peter da Silva <peter@abbnm.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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Glen Herrmannsfeldt wrote:
> I thought both the 1620 and 14xx were variable word length machines.  I
> don't know if I have a book that says it, though.

Leeson and Dimitry, _Basic Programming Concepts and the IBM 1620 
Computer_

"Each core storage position in the 1620 has a unique address and 
can store one digit of information. Each digit is a binary coded 
decimal (BCD) form represented by a 6-bit numeric code...

[explanation of what a 'bit' is deleted]

"The six [bits] are dvided into three groups: one check bit (C 
bit), one flag bit (F bit) and four numeric bits [...]

"The flag bit is used three ways:

"1. Field definition: the high-order position of a numeric field 
is defined by the presence of a flag [bit]. Thus the number 457 
would appear in storage with a flag bit in the core position 
containing the 5. A flag is denoted by a horizontal line above a 
digit [which I can't type, so I'll use braces], {5}37.

"2. Sign control: The presence of a flag in the units position of 
a numeric field indicates that the field is negative. If no flag 
is present in the units position of a feld, the field is taken to 
be positive. The number -537 woudl appear in storage as {5}3{7}.

"3. carries. Flags present in certain positions of the addition 
table are interpretedas carries in arithmetic operations."
-- 
`-_-'   Ar rug tú barróg ar do mhactíre inniu?
  'U`    Peter da Silva

######

From: Marco S Hyman <marc@snafu.org>
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"Edward A. Feustel" <efeustel@erols.com> writes:

> > The PDP-10 is word-addressed machine, but it has what are called
> > "byte pointers", which are not an addressing mode, but which are

> As I recall:
> The Burroughs B5000 line of machines had descriptors that could address a
> group

The format of a data descriptor for a 6700/6800/6900 (and possibly
earlier and later machines is  (n:m means m bits starting at bit n)

   bit 47       presence bit (in memory or on disk)
       46       copy bit (copy of another descriptor)
       45       indexed bit (see below)
       44       segmented bit
       43       read only bit
       42:3     size field
       39:20    length field
       19:20    address field

The size field indicated the type of data (word, bcl, etc.)
If the indexed bit was set then the length field was the word offset
and the address field was the <type> offset.

Program control used a different format that addressed to the
code "syllable".   A syllable is 8 bits.

How did this differ from the earlier 5000?

// marc

######

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In article <v5fqsdcugnrk7a@corp.supernews.com>,
GerardS <GerardS@PrairieTech.Net> wrote:
>No, the word size wasn't two characters wide.  You're confusing the fact
>that a character (to be punched, printed, etc) was two decimal digits.
No, what I'm talking about is that the memory was physically two characters
wide.  It was a 12-bit core stack, 4 for the digit, one for the field
mark, and one for parity, and the memory word held two of those things.
But hidden from the programmer.  You could think of it as one character
wide if you wanted to.  Although there was a bit of oddity too - as I recall
you couldn't have a one-digit field because the field mark over the units
digit was used as a sign bit.  But that wasn't inherent in the memory
word length.

######

From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Newsgroups: comp.arch,alt.folklore.computers
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"Jim Haynes" <haynes@alumni.uark.edu> wrote in message news:KNU5a.905
(snip regarding the 1620)

> No, what I'm talking about is that the memory was physically two
characters
> wide.  It was a 12-bit core stack, 4 for the digit, one for the field
> mark, and one for parity, and the memory word held two of those things.
> But hidden from the programmer.  You could think of it as one character
> wide if you wanted to.  Although there was a bit of oddity too - as I
recall
> you couldn't have a one-digit field because the field mark over the units
> digit was used as a sign bit.  But that wasn't inherent in the memory
> word length.

Many machines have a different memory path width than the width seem by the
programmer.  The question is, what is the smallest addressable boundary.
Is it one digit or two?  Even if it is two, that probably qualifies as
"byte" addressable, depending on the definition of byte.

-- glen

######

From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Newsgroups: comp.arch,alt.folklore.computers
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"Peter da Silva" <peter@abbnm.com> wrote in message
news:b38vpn$r0q$1@jeeves.eng.abbnm.com...
> Glen Herrmannsfeldt wrote:
> > I thought both the 1620 and 14xx were variable word length machines.  I
> > don't know if I have a book that says it, though.
>
> Leeson and Dimitry, _Basic Programming Concepts and the IBM 1620
> Computer_
>
> "Each core storage position in the 1620 has a unique address and
> can store one digit of information. Each digit is a binary coded
> decimal (BCD) form represented by a 6-bit numeric code...
>
> [explanation of what a 'bit' is deleted]
(even more snipped)

> "2. Sign control: The presence of a flag in the units position of
> a numeric field indicates that the field is negative. If no flag
> is present in the units position of a feld, the field is taken to
> be positive. The number -537 woudl appear in storage as {5}3{7}.

How does it know the length of the field, if the sign bit is stored in the
field mark?

-- glen

######

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The Manchester University Atlas (I think later sold as a commercial product
by Ferranti?) had a 48-bit word length which was addressable at the (6-bit)
byte level.  It had a single 24-bit address, of which the lowest 3 bits were
for halfword or characters.  That was 1960 or so.

I think that was comparable to the S/360 scheme.

-- 
Get ON with it!


Send eMail to ----> grenaud@acm.org.  For contact info, see:  
        http://home.earthlink.net/~sleepyjackal/contact.htm

######

From: "BERNARD W RULAND" <bruland@prodigy.net>
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I think the 1620 read 2 char from storage. It had to do this 2 be able to
read an alpha char and it also load instructions this way. You had a odd and
a even register that the chars ended up in.

Old 1620 ibm ce
"GerardS" <GerardS@PrairieTech.Net> wrote in message
news:v5fqsdcugnrk7a@corp.supernews.com...
> | Jim Haynes wrote:
> |> Peter Flass yahoo.com> wrote:
> |>> Hybrids wrote:
> | I think the Burroughs systems
> | (5500, etc.) were both byte and word addressable.  ISTR you could add
> | The B5500 had two different architectures in the same machine.  It was
> | basically word addressable; then there was a subsidiary mechanism to
> | make it into a variable-field-length character machine.  But it didn't
> | have what I'm asking about, which is a machine address to the byte
> | level but which also recognizes things larger than a byte as words.
> |
> | The IBM 1620 fits my example of a variable field length machine in
> | which there was a word more-or-less hidden from the programmer; its
> | memory size was two characters wide but you didn't have to know this
> | to program it.
>
> No, the word size wasn't two characters wide.  You're confusing the fact
> that a character (to be punched, printed, etc) was two decimal digits.
> There was nothing in the IBM 1620 instruction set that handled anything
> two characters wide as a primative.  Nothing was hidden from the
> programmer as it was a very simple machine architecture wise.  It was
> very easy to program for that reason. _______________________Gerard S.
>
>

######

From: Peter da Silva <peter@abbnm.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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Glen Herrmannsfeldt wrote:
> How does it know the length of the field, if the sign bit is stored in the
> field mark?

Someone else already answered that: you couldn't have a one-digit 
field.
-- 
`-_-'   Ar rug tú barróg ar do mhactíre inniu?
  'U`    Peter da Silva

######

From: Terje Mathisen <terje.mathisen@hda.hydro.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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Peter da Silva wrote:
> "1. Field definition: the high-order position of a numeric field is 
> defined by the presence of a flag [bit]. Thus the number 457 would 

Interesting typo, '537' must have been intended, instead of '457'. :-)

> appear in storage with a flag bit in the core position containing the 5. 
> A flag is denoted by a horizontal line above a digit [which I can't 
> type, so I'll use braces], {5}37.
> 
> "2. Sign control: The presence of a flag in the units position of a 
> numeric field indicates that the field is negative. If no flag is 
> present in the units position of a feld, the field is taken to be 
> positive. The number -537 woudl appear in storage as {5}3{7}.

This obviously means that at least negative numbers had to be at least 
two digits long.

Terje.

-- 
- <Terje.Mathisen@hda.hydro.com>
"almost all programming can be viewed as an exercise in caching"

######

From: Lars Brinkhoff <lars.spam@nocrew.org>
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jmfbahciv@aol.com writes:
> Christopher C. Stacy wrote:
> > The PDP-10 is word-addressed machine, but it has what are called
> > "byte pointers", which are not an addressing mode, but which are
> > used with several instructions
> One instruction.  

How about these five: LDB, DPB, ILDB, IDPB, IBP?  Six if you include
ADJBP, which use the same opcode as IBP and wasn't in the original
PDP-10.

Then there are the string instructions, but let's not go there.

-- 
Lars Brinkhoff          http://lars.nocrew.org/     Linux, GCC, PDP-10,
Brinkhoff Consulting    http://www.brinkhoff.se/    HTTP programming

######

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Peter Flass  <peter_flass@yahoo.com> wrote:
+---------------
| Right.  The 1620 and 14xx machines used a "word mark" bit to flag the
| character that was the end of the field...
+---------------

IIRC, in the 1410 (at least) the word mark bit flagged the *beginning*
of the field, and the end was the last character without a wordmark on
it, that is, fields were terminated by the start of the *next* field.

More trivia: Each character had 7 bits plus parity. The bits were named
1, 2, 4, 8, A, B, C (parity), and word mark. Word mark was printed
(at least, on the Selectric typewriter that was used as the console) 
as an inverted caret over the character. [There was another thingy
called "group mark", but that was just a particular (albeit magical)
character with all of 1248AB set, IIRC. So you could have a "group
mark/word mark" character, often used as a tape record delimiter.]

I even remember the sequence (you had to type it in manually) to
boot the 1410 from magtape (the "v"s over the top are word marks):

	v         v
	L%B000012$N

This was a read-and-wait from tape #0, one record, ignoring/overwriting
any group marks/word marks that happened to be in memory, putting the
data into memory starting at address 12 [note: 1410 addressing was 1-based,
not 0-based!], followed by a "no-op" [in location 11, note]. The CPU would
fetch the no-op (the "N"), but then hang waiting for the tape read to
complete, whereupon it would execute the no-op and then fetch and execute
the code that had just been read in. At which point, you're off & running...


-Rob

-----
Rob Warnock, PP-ASEL-IA		<rpw3@rpw3.org>
627 26th Avenue			<URL:http://rpw3.org/>
San Mateo, CA 94403		(650)572-2607

######

From: "GerardS" <GerardS@PrairieTech.Net>
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Subject: Re: Antiquity of Byte-Word addressing?
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| Glen Herrmannsfeldt wrote:
|> Jim Haynes wrote:
| (snip regarding the 1620)
|
| > No, what I'm talking about is that the memory was physically two
| characters
| > wide.  It was a 12-bit core stack, 4 for the digit, one for the field
| > mark, and one for parity, and the memory word held two of those things.
| > But hidden from the programmer.  You could think of it as one character
| > wide if you wanted to.  Although there was a bit of oddity too - as I
| recall
| > you couldn't have a one-digit field because the field mark over the units
| > digit was used as a sign bit.  But that wasn't inherent in the memory
| > word length.
|
| Many machines have a different memory path width than the width seem by the
| programmer.  The question is, what is the smallest addressable boundary.
| Is it one digit or two?  Even if it is two, that probably qualifies as
| "byte" addressable, depending on the definition of byte.

The IBM 1620 had addressability to the digit. ______________________Gerard S.

######

From: "GerardS" <GerardS@PrairieTech.Net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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| Glen Herrmannsfeldt wrote:
|| Peter da Silva wrote:
|> Glen Herrmannsfeldt wrote:
|>> I thought both the 1620 and 14xx were variable word length machines.  I
|>> don't know if I have a book that says it, though.
|>
|> Leeson and Dimitry, _Basic Programming Concepts and the IBM 1620
|> Computer_
|>
|> "Each core storage position in the 1620 has a unique address and
|> can store one digit of information. Each digit is a binary coded
|> decimal (BCD) form represented by a 6-bit numeric code...
|>
|> [explanation of what a 'bit' is deleted]
| (even more snipped)
|
|> "2. Sign control: The presence of a flag in the units position of
|> a numeric field indicates that the field is negative. If no flag
|> is present in the units position of a feld, the field is taken to
|> be positive. The number -537 woudl appear in storage as {5}3{7}.
|
| How does it know the length of the field, if the sign bit is stored in the
| field mark?

If the flag bit (you call it a sign mit) is on the first digit, the
number is negative.

The flag bit on any other digit (other than the first digit) signifies
the length of the field (number).  It is this requirment that makes it
impossible to have a one-digit field (for a number). ________Gerard S.

######

From: "GerardS" <GerardS@PrairieTech.Net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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| BERNARD W RULAND wrote:
| I think the 1620 read 2 char from storage. It had to do this 2 be able to
| read an alpha char and it also load instructions this way. You had a odd and
| a even register that the chars ended up in.            Old 1620 ibm ce

No, it didn't.  The IBM 1620 (model I) didn't even have registers.  There was
no LOAD instruction, as there was no place to LOAD a number into.   Even if
there was, where would you load a 33,456 digit number into ?

There was no need to "read" an alphabetic character.  If you were doing I/O,
the character(s)  [two-digit decimal numbers] were transferred to the IO
gear (controller) directly.  I/O was VERY simple on the IBM 1620.  To print
a line, you issued:

  39 xxxxx 0yy00

(39 happened to be a write alphabetic) ---  xxxxx was the address of the
field to start writing from,  and   yy    was one of:
  01  --- typewriter
  02  --- paper tape punch
  03  --- paper tape reader
  04  --- card punch
  05  --- card reader

There was also a method to return the carriage on the typewrite, tab, or
write a space.

My book doesn't specify what the code was for writting to a printer (or
plotter), and we did have both of those.  Later, IBM disk drives (1311s?)
were added.   This was all on an IBM 1620 (model I) way back in 1967.
The first 1620 I used only had a typewriter and a card reader/punch for
I/O.

The IBM 1620-II did have index registers, however.  Addresses were always
five digits and may be negative, in which case, that address pointed to an
address to be used (which can also be negative).  This was called
indirect addressing). _____________________________________________Gerard S.



|> GerardS wrote:
|>| Jim Haynes wrote:
|>|> Peter Flass yahoo.com> wrote:
|>|>> Hybrids wrote:
|>| I think the Burroughs systems
|>| (5500, etc.) were both byte and word addressable.  ISTR you could add
|>| The B5500 had two different architectures in the same machine.  It was
|>| basically word addressable; then there was a subsidiary mechanism to
|>| make it into a variable-field-length character machine.  But it didn't
|>| have what I'm asking about, which is a machine address to the byte
|>| level but which also recognizes things larger than a byte as words.
|>|
|>| The IBM 1620 fits my example of a variable field length machine in
|>| which there was a word more-or-less hidden from the programmer; its
|>| memory size was two characters wide but you didn't have to know this
|>| to program it.
|> No, the word size wasn't two characters wide.  You're confusing the fact
|> that a character (to be punched, printed, etc) was two decimal digits.
|> There was nothing in the IBM 1620 instruction set that handled anything
|> two characters wide as a primative.  Nothing was hidden from the
|> programmer as it was a very simple machine architecture wise.  It was
|> very easy to program for that reason. _______________________Gerard S.

######

From: "GerardS" <GerardS@PrairieTech.Net>
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| Terje Mathisen wrote:
|> Peter da Silva wrote:
|> "1. Field definition: the high-order position of a numeric field is
|> defined by the presence of a flag [bit]. Thus the number 457 would
|
|Interesting typo, '537' must have been intended, instead of '457'. :-)
|
|> appear in storage with a flag bit in the core position containing the 5.
|> A flag is denoted by a horizontal line above a digit [which I can't
|> type, so I'll use braces], {5}37.
|>
|> "2. Sign control: The presence of a flag in the units position of a
|> numeric field indicates that the field is negative. If no flag is
|> present in the units position of a feld, the field is taken to be
|> positive. The number -537 woudl appear in storage as {5}3{7}.
|
| This obviously means that at least negative numbers had to be at least
| two digits long.

Not just negative numbers, all numbers. ________________________Gerard S.

######

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In article <3E5828B5.E261C23E@earthlink.net>,
Gary and the Samoyeds  <sleepyjackal@earthlink.net> wrote:
>The Manchester University Atlas (I think later sold as a commercial product
>by Ferranti?) had a 48-bit word length which was addressable at the (6-bit)
>byte level.  It had a single 24-bit address, of which the lowest 3 bits were
>for halfword or characters.  That was 1960 or so.

At last!  After everything was cussed and discussed we have an answer to
the original question.  Thank you.

######

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On Sun, 23 Feb 2003 05:45:15 -0600, rpw3@rpw3.org (Rob Warnock) wrote:

>Peter Flass  <peter_flass@yahoo.com> wrote:
>+---------------
>| Right.  The 1620 and 14xx machines used a "word mark" bit to flag the
>| character that was the end of the field...
>+---------------
>
>IIRC, in the 1410 (at least) the word mark bit flagged the *beginning*
>of the field, and the end was the last character without a wordmark on
>it, that is, fields were terminated by the start of the *next* field.
1401,1440,1460,1410,7010 are the ones that I know of.
>
>More trivia: Each character had 7 bits plus parity. The bits were named
>1, 2, 4, 8, A, B, C (parity), and word mark. Word mark was printed
Usually referred to in this order: CBA8421W
>(at least, on the Selectric typewriter that was used as the console) 
>as an inverted caret over the character. [There was another thingy
>called "group mark", but that was just a particular (albeit magical)
>character with all of 1248AB set, IIRC. So you could have a "group
>mark/word mark" character, often used as a tape record delimiter.]
A GMWM was used to delimit the end of an I/O buffer (tape/disk and
card/print on some machines)  I don't think that it was actually
possible to read or write a GMWM as it's presence stopped the I/O
operation.
>
>I even remember the sequence (you had to type it in manually) to
>boot the 1410 from magtape (the "v"s over the top are word marks):
>
>	v         v
>	L%B000012$N
>
>This was a read-and-wait from tape #0, one record, ignoring/overwriting
>any group marks/word marks that happened to be in memory, putting the
>data into memory starting at address 12 [note: 1410 addressing was 1-based,
>not 0-based!], followed by a "no-op" [in location 11, note]. The CPU would
>fetch the no-op (the "N"), but then hang waiting for the tape read to
>complete, whereupon it would execute the no-op and then fetch and execute
>the code that had just been read in. At which point, you're off & running...
I wouldn't say any of those systems were 1-based.  It's just that
location 0 was reserved, and couldn't be used by a user program.  I
think that location 0 (on some systems) might have been used as a 1
char buffer for some operations.


-- 
Arargh (at arargh dot com)    http://www.arargh.com
To reply by email, change the domain name, and remove the garbage.
(Enteract can keep the spam, they are gone anyway)

######

From: D.C.Wood@ukc.ac.uk (dcw)
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Subject: Re: Antiquity of Byte-Word addressing?
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In article <Qfa6a.2570$cD5.246128@newsread2.prod.itd.earthlink.net>,
Jim Haynes <jhaynes@alumni.uark.edu> wrote:
>In article <3E5828B5.E261C23E@earthlink.net>,
>Gary and the Samoyeds  <sleepyjackal@earthlink.net> wrote:
>>The Manchester University Atlas (I think later sold as a commercial product
>>by Ferranti?) had a 48-bit word length which was addressable at the (6-bit)
>>byte level.  It had a single 24-bit address, of which the lowest 3 bits were
>>for halfword or characters.  That was 1960 or so.
>
>At last!  After everything was cussed and discussed we have an answer to
>the original question.  Thank you.

The hardware could address 48-bit reals and 24-bit integers directly, but
it ignored the bottom two bits of the address.  There were built-in routines
that used those bits to access 6-bit characters.

	David

######

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On Sat, 22 Feb 2003 03:51:29 GMT in alt.folklore.computers,
haynes@alumni.uark.edu (Jim Haynes) wrote:

>I'm under the impression that, with the notable exception of the 7030
>STRETCH, IBM S/360 was the first line of machines to address memory by
>the byte, but to also have a word (and halfword and double word) 
>structure.  Was there anything earlier?
>
>All the earlier machines I'm aware of were either word addressed, and
>used some subsidiary mechanism to pick characters out of words, or were
>character addressed and "variable word length" having no fixed word
>concept.  (Although there may have been memory words of large than one
>character, hidden from the programmer.)

To clarify what others have misinterpreted, you are asking
whether there was a byte addressable, fixed word length machine
earlier than the IBM 360? 

Thanks. Take care, Brian Inglis 	Calgary, Alberta, Canada
-- 
Brian.Inglis@CSi.com 	(Brian dot Inglis at SystematicSw dot ab dot ca)
    fake address		use address above to reply
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abuse@yahoo.com abuse@cadvision.com abuse@shaw.ca abuse@telus.com 
abuse@ibsystems.com uce@ftc.gov				spam traps

######

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<ararghNOSPAM@NOT.AT.enteract.com> wrote:
+---------------
| rpw3@rpw3.org (Rob Warnock) wrote:
| >More trivia: Each character had 7 bits plus parity. The bits were named
| >1, 2, 4, 8, A, B, C (parity), and word mark. Word mark was printed...
|
| Usually referred to in this order: CBA8421W
+---------------

Oh, o.k., thanks.

+---------------
| >(at least, on the Selectric typewriter that was used as the console) 
| >as an inverted caret over the character. [There was another thingy
| >called "group mark", but that was just a particular (albeit magical)
| >character with all of 1248AB set, IIRC. So you could have a "group
| >mark/word mark" character, often used as a tape record delimiter.]
|
| A GMWM was used to delimit the end of an I/O buffer (tape/disk and
| card/print on some machines)  I don't think that it was actually
| possible to read or write a GMWM as it's presence stopped the I/O
| operation.
+---------------

Actually, that depended on the particular operation. In the bootstrap
instruction I mentioned:

+---------------
| >	v         v
| >	L%B000012$N
| >
| >This was a read-and-wait from tape #0, one record, ignoring/overwriting
| >any group marks/word marks that happened to be in memory...
+---------------

I think it was the "$" modifier that said "transfer EVERYTHING --
including GMWMs -- until end-of-record".

I know this was possible, since I used to carry around a small tape
that I used for playing around with machine-language programming.
(Given that the 1410 used decimal addressing, it was almost as easy to
code in machine language as assembler!) I kept several "core images"[1]
on the tape that contained the state of the machine from previous
experiments -- each "core image" being one large record! The above
bootstrap would read in an entire image in one gulp (including GMWMs).


-Rob

[1] Much like Lisp systems which let you save the state of the system
    in a "core image" and restart it later. Hmmm... Funny how things
    come around again... I've been doing some of *that* lately, too!  ;-}

    <http://cvs2.cons.org/ftp-area/cmucl/doc/cmu-user/extensions.html#toc43>
    Saving a Core Image
    A mechanism has been provided to save a running Lisp core image and
    to later restore it. This is convenient if you don't want to load
    several files into a Lisp when you first start it up.
    ...

-----
Rob Warnock, PP-ASEL-IA		<rpw3@rpw3.org>
627 26th Avenue			<URL:http://rpw3.org/>
San Mateo, CA 94403		(650)572-2607

######

From: Nick Spalding <spalding@iol.ie>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Mon, 24 Feb 2003 13:03:21 +0000
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Rob Warnock wrote, in <GmednS0MscCym8ejXTWc-g@speakeasy.net>:

> I think it was the "$" modifier that said "transfer EVERYTHING --
> including GMWMs -- until end-of-record".
> 
> I know this was possible, since I used to carry around a small tape
> that I used for playing around with machine-language programming.
> (Given that the 1410 used decimal addressing, it was almost as easy to
> code in machine language as assembler!) I kept several "core images"[1]
> on the tape that contained the state of the machine from previous
> experiments -- each "core image" being one large record! The above
> bootstrap would read in an entire image in one gulp (including GMWMs).

Yes.

<fixed pitch>

From:
IBM 1410 Principles of Operation
System/File No. 1410-01
Form A22-0526
Pages Revised 1/15/63

on p. 85

Read or Write Tape with Word Marks
Instruction Form:

                 Op   X-control
  Mnemonic      Code    Field   B-address   d-character
                  _
RTW or WTW        L      %Un      bbbbb       R or W
                  _
RTGW or WTEW      L      %Un      bbbbb       $ or X

Function: These two sets of instructions have the same functions as the
read or write tape instructions, except that word marks are written on tape
as word separators, and word separators are read into storage as word
marks.  In a write operation, a word separator is written on tape, one
position ahead of the associated character.  in a tape read operation, word
marks are associated with the next character read from the tape.

<end quote>

The crucial bit of information missing from this is what you point out,
that the use of the $ or X as the d-character will force the ability to
read/write GMWMs. 
 
The E in WTEW implies write to end of core, which makes me wonder why the
read uses RTGW.  Did you have to clear memory before reading your dump
tapes?

I was a 7010 person myself but have the 1410 PoO - I don't think they had
got around to printing one at the time I was involved with it in 1963.
They were lovely machines though why the 1410 lost the 1401's load button,
restored in the 7010, I never understood.  
-- 
Nick Spalding

######

From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
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"Brian Inglis" <Brian.Inglis@SystematicSw.ab.ca> wrote in message
news:dbkj5vche0lf3re6s5umbj8bg6uu1laag6@4ax.com...
> On Sat, 22 Feb 2003 03:51:29 GMT in alt.folklore.computers,
> haynes@alumni.uark.edu (Jim Haynes) wrote:
>
> >I'm under the impression that, with the notable exception of the 7030
> >STRETCH, IBM S/360 was the first line of machines to address memory by
> >the byte, but to also have a word (and halfword and double word)
> >structure.  Was there anything earlier?
> >
> >All the earlier machines I'm aware of were either word addressed, and
> >used some subsidiary mechanism to pick characters out of words, or were
> >character addressed and "variable word length" having no fixed word
> >concept.  (Although there may have been memory words of large than one
> >character, hidden from the programmer.)
>
> To clarify what others have misinterpreted, you are asking
> whether there was a byte addressable, fixed word length machine
> earlier than the IBM 360?

To clarify even more, bytes are not necessarily 8 bits, but must be too
small to use as a general purpose integer variable.   Would a 12 bit machine
with hardware support for a 24 bit data type qualify?

-- glen

######

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Glen Herrmannsfeldt wrote:
>  <Brian.Inglis@SystematicSw.ab.ca> wrote in message
> >
... snip ...
> >
> > To clarify what others have misinterpreted, you are asking
> > whether there was a byte addressable, fixed word length
> > machine earlier than the IBM 360?
> 
> To clarify even more, bytes are not necessarily 8 bits, but
> must be too small to use as a general purpose integer variable.
> Would a 12 bit machine with hardware support for a 24 bit data
> type qualify?

Not when it's a PDP8 with 4k of addressing :-)

-- 
Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net)
   Available for consulting/temporary embedded and systems.
   <http://cbfalconer.home.att.net>  USE worldnet address!

######

From: "BERNARD W RULAND" <bruland@prodigy.net>
Newsgroups: comp.arch,alt.folklore.computers
References: <5tC5a.1106$TR4.120765@newsread1.prod.itd.earthlink.net> <v5dtgeq9snuj67@corp.supernews.com> <7YC5a.208133$vm2.156455@rwcrnsc54> <3E57531C.F30E88B1@yahoo.com> <zPR5a.753$cD5.88031@newsread2.prod.itd.earthlink.net> <v5fqsdcugnrk7a@corp.supernews.com> <bJW5a.363$0C2.37589172@newssvr15.news.prodigy.com> <v5i4g0q6jfcta2@corp.supernews.com>
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I was trained to repair the 1620,1621, 1622 hardware in1962 at San Jose
Calif. I spent 6 mounths in the IBM school and I know that the 1620 read 2
chars out of memory per memory cycle and place them in an odd/ even
register. There wasn't a load address instruction but that doesn't mean that
the registers wern't there. We had 2 1620's at White Sands, 2 at Hollamon
AFB , 1 at Sac Peak , and 1 at the Spy scope at Cloudcroft NM that I
maintained until 1967.

Bernie
Old IBM 1620 repairman
"GerardS" <GerardS@PrairieTech.Net> wrote in message
news:v5i4g0q6jfcta2@corp.supernews.com...
> | BERNARD W RULAND wrote:
> | I think the 1620 read 2 char from storage. It had to do this 2 be able
to
> | read an alpha char and it also load instructions this way. You had a odd
and
> | a even register that the chars ended up in.            Old 1620 ibm ce
>
> No, it didn't.  The IBM 1620 (model I) didn't even have registers.  There
was
> no LOAD instruction, as there was no place to LOAD a number into.   Even
if
> there was, where would you load a 33,456 digit number into ?
>
> There was no need to "read" an alphabetic character.  If you were doing
I/O,
> the character(s)  [two-digit decimal numbers] were transferred to the IO
> gear (controller) directly.  I/O was VERY simple on the IBM 1620.  To
print
> a line, you issued:
>
>   39 xxxxx 0yy00
>
> (39 happened to be a write alphabetic) ---  xxxxx was the address of the
> field to start writing from,  and   yy    was one of:
>   01  --- typewriter
>   02  --- paper tape punch
>   03  --- paper tape reader
>   04  --- card punch
>   05  --- card reader
>
> There was also a method to return the carriage on the typewrite, tab, or
> write a space.
>
> My book doesn't specify what the code was for writting to a printer (or
> plotter), and we did have both of those.  Later, IBM disk drives (1311s?)
> were added.   This was all on an IBM 1620 (model I) way back in 1967.
> The first 1620 I used only had a typewriter and a card reader/punch for
> I/O.
>
> The IBM 1620-II did have index registers, however.  Addresses were always
> five digits and may be negative, in which case, that address pointed to an
> address to be used (which can also be negative).  This was called
> indirect addressing). _____________________________________________Gerard
S.
>
>
>
> |> GerardS wrote:
> |>| Jim Haynes wrote:
> |>|> Peter Flass yahoo.com> wrote:
> |>|>> Hybrids wrote:
> |>| I think the Burroughs systems
> |>| (5500, etc.) were both byte and word addressable.  ISTR you could add
> |>| The B5500 had two different architectures in the same machine.  It was
> |>| basically word addressable; then there was a subsidiary mechanism to
> |>| make it into a variable-field-length character machine.  But it didn't
> |>| have what I'm asking about, which is a machine address to the byte
> |>| level but which also recognizes things larger than a byte as words.
> |>|
> |>| The IBM 1620 fits my example of a variable field length machine in
> |>| which there was a word more-or-less hidden from the programmer; its
> |>| memory size was two characters wide but you didn't have to know this
> |>| to program it.
> |> No, the word size wasn't two characters wide.  You're confusing the
fact
> |> that a character (to be punched, printed, etc) was two decimal digits.
> |> There was nothing in the IBM 1620 instruction set that handled anything
> |> two characters wide as a primative.  Nothing was hidden from the
> |> programmer as it was a very simple machine architecture wise.  It was
> |> very easy to program for that reason. _______________________Gerard S.
>
>

######

From: Ron Hunsinger <newsreply1@erstesoft.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Message-ID: <240220031859453025%newsreply1@erstesoft.com>
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Xref: chonsp.franklin.ch alt.folklore.computers:130278

In article <x7znon99jh.fsf@hana.snafu.org>, Marco S Hyman
<marc@snafu.org> wrote:

> The format of a data descriptor for a 6700/6800/6900 (and possibly
> earlier and later machines is  (n:m means m bits starting at bit n)
> 
>    bit 47       presence bit (in memory or on disk)
>        46       copy bit (copy of another descriptor)
>        45       indexed bit (see below)
>        44       segmented bit
>        43       read only bit
>        42:3     size field
>        39:20    length field
>        19:20    address field
> 
> The size field indicated the type of data (word, bcl, etc.)
> If the indexed bit was set then the length field was the word offset
> and the address field was the <type> offset.

Almost right. The address field was always a word address, pointing to
the beginning of a block of memory. If the indexed bit was set, then
the 'length' field became an 'offset' field that selected a character
of the indicated size from within that block of memory.

The interpretation of the offset field depended on the setting of the
size field. If the size was was 0 (word) or 1 (double-word), then all
20 bits of the length field were available to provide a word offset
from the base address in the address field.

But if the size was 2 (hex), 3 (BCL = 6-bit), or 4 (EBCDIC = 8-bit),
then the length field split into:

        39:3      character offset
        36:17     word offset

The word offset plus the base address gave a word address; the
character offset then selected a character position within that word.

Note that this meant that although word-type descriptors (with a size
of 0 or 1) could reference a block of up to a million words, you
couldn't perform character operations on memory blocks over 128K words
in size.

-Ron Hunsinger

######

From: Ron Hunsinger <newsreply1@erstesoft.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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Xref: chonsp.franklin.ch alt.folklore.computers:130279

In article <v5i4g0q6jfcta2@corp.supernews.com>, "GerardS"
<GerardS@PrairieTech.Net> wrote:

> I/O was VERY simple on the IBM 1620.  To print
> a line, you issued:
> 
>   39 xxxxx 0yy00
> 
> (39 happened to be a write alphabetic) ---  xxxxx was the address of the
> field to start writing from,  and   yy    was one of:
>   01  --- typewriter
>   02  --- paper tape punch
>   03  --- paper tape reader
>   04  --- card punch
>   05  --- card reader
> 
> There was also a method to return the carriage on the typewrite, tab, or
> write a space.
> 
> My book doesn't specify what the code was for writting to a printer (or
> plotter), and we did have both of those.  Later, IBM disk drives (1311s?)
> were added.   This was all on an IBM 1620 (model I) way back in 1967.
> The first 1620 I used only had a typewriter and a card reader/punch for
> I/O.

If you have a FORTRAN IV manual of the same vintage, you might be able
to find the answer there. The FORTRAN compiler simply mapped the device
number to the hardware code. Thus:

   99 FORMAT (2I4)
      READ (5, 99) I, J
C -------- read from the card reader, using 37 xxxxx 00500

      K = I + J
      WRITE (2, 99) K
C -------- write on the paper tape punch, using 39 xxxxx 00200

-Ron Hunsinger

######

Message-ID: <3E5AC648.A55E40E0@yahoo.com>
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Glen Herrmannsfeldt wrote:
> "CBFalconer" <cbfalconer@yahoo.com> wrote in message
> > Glen Herrmannsfeldt wrote:
> > >  <Brian.Inglis@SystematicSw.ab.ca> wrote in message
> > > >
> > ... snip ...
> > > >
> > > > To clarify what others have misinterpreted, you are asking
> > > > whether there was a byte addressable, fixed word length
> > > > machine earlier than the IBM 360?
> > >
> > > To clarify even more, bytes are not necessarily 8 bits, but
> > > must be too small to use as a general purpose integer variable.
> > > Would a 12 bit machine with hardware support for a 24 bit data
> > > type qualify?
> >
> > Not when it's a PDP8 with 4k of addressing :-)
> 
> I thought we were discussing data operations, not addressing modes.
> Though I don't know that PDP8 supports 24 bit data, either.

It could have an extended arithmetic register.

-- 
Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net)
   Available for consulting/temporary embedded and systems.
   <http://cbfalconer.home.att.net>  USE worldnet address!

######

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"The hardware could address 48-bit reals and 24-bit integers directly, but
it ignored the bottom two bits of the address."

Which is just how the S/360 worked.  (OK, it gave an error if it were mis-
aligned, but close enough.)

"There were built-in routines that used those bits to access 6-bit characters."

Oh, it wasn't done in hardware?  Darn.  There goes My suggestion. 


All right, then.  Does it have to be all the way down to the Byte/Character
level?  Or does any sub-word unit count?

The EDSAC didn't have Byte addressing, but it DID have Halfword addressing, 
with the LSB of the address representing the halfword, and full-word 
addressing required an even address.  That's not QUITE as good as S/360, but 
the concept is there.

This was 1949.

-- 
Get ON with it!


Send eMail to ----> grenaud@acm.org.  For contact info, see:  
        http://home.earthlink.net/~sleepyjackal/contact.htm

######

From: ararghNOSPAM@NOT.AT.enteract.com
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Mon, 24 Feb 2003 21:23:31 -0600
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On Mon, 24 Feb 2003 05:46:55 -0600, rpw3@rpw3.org (Rob Warnock) wrote:

><ararghNOSPAM@NOT.AT.enteract.com> wrote:
>+---------------
>| rpw3@rpw3.org (Rob Warnock) wrote:
>| >More trivia: Each character had 7 bits plus parity. The bits were named
>| >1, 2, 4, 8, A, B, C (parity), and word mark. Word mark was printed...
>|
>| Usually referred to in this order: CBA8421W
>+---------------
>
>Oh, o.k., thanks.
>
>+---------------
>| >(at least, on the Selectric typewriter that was used as the console) 
>| >as an inverted caret over the character. [There was another thingy
>| >called "group mark", but that was just a particular (albeit magical)
>| >character with all of 1248AB set, IIRC. So you could have a "group
>| >mark/word mark" character, often used as a tape record delimiter.]
>|
>| A GMWM was used to delimit the end of an I/O buffer (tape/disk and
>| card/print on some machines)  I don't think that it was actually
>| possible to read or write a GMWM as it's presence stopped the I/O
>| operation.
>+---------------
>
>Actually, that depended on the particular operation. In the bootstrap
>instruction I mentioned:
>
>+---------------
>| >	v         v
>| >	L%B000012$N
>| >
>| >This was a read-and-wait from tape #0, one record, ignoring/overwriting
>| >any group marks/word marks that happened to be in memory...
>+---------------
>
>I think it was the "$" modifier that said "transfer EVERYTHING --
>including GMWMs -- until end-of-record".
Maybe it is specific to the 1410/7010.  That d-char is not documented
in any of the 1401/40/60 books that I checked.
>
>I know this was possible, since I used to carry around a small tape
>that I used for playing around with machine-language programming.
>(Given that the 1410 used decimal addressing, it was almost as easy to
>code in machine language as assembler!) 

IIRC, you didn't have to play the addressing games on a 1410 that you
had to on a 1401.  '99999' referred to the last possible address in a
1410, but for a 1401, it was 'I9I' to refer to location 15999,
assuming I remembered the encoding correctly.

<snip>

-- 
Arargh (at arargh dot com)    http://www.arargh.com
To reply by email, change the domain name, and remove the garbage.
(Enteract can keep the spam, they are gone anyway)

######

From: "GerardS" <GerardS@PrairieTech.Net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Mon, 24 Feb 2003 22:15:57 -0600
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| Ron Hunsinger wrote:
|> GerardS wrote:
|> I/O was VERY simple on the IBM 1620.  To print
|> a line, you issued:
|>
|>   39 xxxxx 0yy00
|>
|> (39 happened to be a write alphabetic) ---  xxxxx was the address of the
|> field to start writing from,  and   yy    was one of:
|>   01  --- typewriter
|>   02  --- paper tape punch
|>   03  --- paper tape reader
|>   04  --- card punch
|>   05  --- card reader
|>
|> There was also a method to return the carriage on the typewrite, tab, or
|> write a space.
|>
|> My book doesn't specify what the code was for writting to a printer (or
|> plotter), and we did have both of those.  Later, IBM disk drives (1311s?)
|> were added.   This was all on an IBM 1620 (model I) way back in 1967.
|> The first 1620 I used only had a typewriter and a card reader/punch for
|> I/O.
|
| If you have a FORTRAN IV manual of the same vintage, you might be able
| to find the answer there. The FORTRAN compiler simply mapped the device
| number to the hardware code. Thus:
|
|    99 FORMAT (2I4)
|       READ (5, 99) I, J
| C -------- read from the card reader, using 37 xxxxx 00500
|
|       K = I + J
|       WRITE (2, 99) K
| C -------- write on the paper tape punch, using 39 xxxxx 00200

We didn't have Fortran IV back in 1966 (for the IBM 1620 computer).  We
did, however, have the Kingston Fortran II, but that fortran (back then,
it was FORTRAN) didn't have READ/WRITE statements like Fortran IV (and
later fortrans) had.

For reading, there was:

  ACCEPT  n,list      (for the typewriter)
  READ    n,list      (for cards)
  REREAD  n,list      (buffer)
  ACCEPT TAPE n,list  (for paper tape)

for writing, there was:
  TYPE    n,list      (for the typewriter)
  PUNCH   n,list      (for cards)
  PRINT   n,list      (for the printer)
  PUNCH TAPE n,list   (for paper tape)
  EDIT    n,list      (for the buffer)

Magnetic tape wasn't supported in the third edition of Kingston
FORTAN II.  (I don't know about later versions).

For plotting,  it was CALL PLOT someargs...
(also CALL PLOTP to the printer).

DISK I/O wasn't allowed, but you were permitted to CALL fortran
programs already compiled  (and put on the [IBM 1311?) disk drive(s)
by the Kingston monitor program ("operating system, but properly
called a monitor).

There were two forms,    CALL,   and     CALL CALL.

The later performed an overlay of the calling program, the former
allowed you to return to the invoker.

Note that reading paper tape was via the ACCEPT TAPE command instead
of READ TAPE ... I found that interesting.

Also noteworth was that the Kingston FORTRAN II had some features that
FORTRAN IV didn't have.

It had logical IFs (as well as arithmetic IFs).

Full mixed mode, you could ouput a REAL variable using the  I  format
and it would automajically convert the REAL to an integer before
formatting.   You could also use REAL numbers in DO loops, as well
as hollerith codes:   DO 7 I=1HA,1HZ     for instance.

Also, literal strings were allowed in the form of:
nnnHyyyyyy   (the usual horerith code)
 --or--
@yyyyyy@

There was a varierty of FORMAT specifications:

  Iw
  Fw.d
  Ew.d
  Gw.s
  N         (free-form numeric input, seps were blanks and/or commas)
  R         (list directed input/output)
  nnHxxx    (Hollerith)
  @xxx@     (literals)
  /
  Aw
  wX
  Tw        ("column" pointer)
  *         (dynamic variable numeric for a format specification)
  U         (dynamic conversion type  for a format specification)

Some of these were only implemented (later) in PL/I.  I never did
see a later versin of Fortran that could do all of the above.


----- ahh, what a trip down memory lane. ____________________Gerard S.

######

From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Newsgroups: comp.arch,alt.folklore.computers
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"Gary and the Samoyeds" <sleepyjackal@earthlink.net> wrote in message
news:3E5ACC81.84A4C51A@earthlink.net...
> "The hardware could address 48-bit reals and 24-bit integers directly, but
> it ignored the bottom two bits of the address."
>
> Which is just how the S/360 worked.  (OK, it gave an error if it were mis-
> aligned, but close enough.)
>
> "There were built-in routines that used those bits to access 6-bit
characters."
>
> Oh, it wasn't done in hardware?  Darn.  There goes My suggestion.

Well, techinically it wasn't hardware on the 360's, either.

All machines (that I can think of) with a memory bus width less than 32 were
microprogrammed, so technically software.  Higher machines had wider
memories.

> All right, then.  Does it have to be all the way down to the
Byte/Character
> level?  Or does any sub-word unit count?
>
> The EDSAC didn't have Byte addressing, but it DID have Halfword
addressing,
> with the LSB of the address representing the halfword, and full-word
> addressing required an even address.  That's not QUITE as good as S/360,
but
> the concept is there.
>
> This was 1949.

Somehow halfword addressing isn't quite as convincing as quarter words.

-- glen

######

From: bfranchuk@jetnet.ab.ca
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Mon, 24 Feb 2003 22:46:02 -0700
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Glen Herrmannsfeldt wrote:

> Somehow halfword addressing isn't quite as convincing as quarter words.
Only if you want to market bigger numbers of memory size.
I have yet to see a good reason for bytes 8 bits wide.
Ben.

######

From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
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<bfranchuk@jetnet.ab.ca> wrote in message
news:3E5B031A.8070605@jetnet.ab.ca...
> Glen Herrmannsfeldt wrote:
>
> > Somehow halfword addressing isn't quite as convincing as quarter words.
> Only if you want to market bigger numbers of memory size.
> I have yet to see a good reason for bytes 8 bits wide.

Well, there are other sizes that have been used, though not always directly
addressable.

CDC machines with 60 bit words, and instruction in, if I remember, groups of
15 bits.  Text data was in units of either 6 or 12 bits (a mixed code, like
UTF8).

The PDP-10, with word addressable 36 bit words (and instructions) stored
five 7 bit characters per word for text data.

It is a little convenient to have the byte size a power of 2, and 8 is big
enough to hold upper and lower cases letters, digits, and useful punctuation
characters.  Six bit codes are from the upper case only days.

-- glen

######

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Nick Spalding  <spalding@iol.ie> wrote:
+---------------
| Rob Warnock wrote, in <GmednS0MscCym8ejXTWc-g@speakeasy.net>:
| > I think it was the "$" modifier that said "transfer EVERYTHING --
| > including GMWMs -- until end-of-record".
| 
| Yes.
...
| Read or Write Tape with Word Marks
| Instruction Form:
|                  Op   X-control
|   Mnemonic      Code    Field   B-address   d-character
| RTW or WTW        L      %Un      bbbbb       R or W
| RTGW or WTEW      L      %Un      bbbbb       $ or X
...
| The crucial bit of information missing from this is what you point out,
| that the use of the $ or X as the d-character will force the ability to
| read/write GMWMs. 
|  
| The E in WTEW implies write to end of core, which makes me wonder why the
| read uses RTGW.  Did you have to clear memory before reading your dump
| tapes?
+---------------

No, clearing core was not required. The bootstrap operation read one
record, however long that was. For the standard operating system, it
wasn't very long, maybe even just one card-image (since the O/S could
also be booted off the card reader!). For my "core image" tapes, it was
a full memory image (as you might have guessed).

+---------------
| I was a 7010 person myself but have the 1410 PoO - I don't think they had
| got around to printing one at the time I was involved with it in 1963.
| They were lovely machines though why the 1410 lost the 1401's load button,
| restored in the 7010, I never understood.  
+---------------

The full boot procedure on the 1410 *was* a bit more complicated than I
bothered to bo into before. What follows is clipped from a comp.arch posting
of mine from 2001 (based on some 1992 email):

...the bootstrapping procedure for the IBM 1410 computer, a BCD "character"
machine with a Selectric for a console device. In order to do a cold boot,
one had to "Alter" memory starting at location 0 to type in the "shoelace".
In order to "Alter" an area, the 1410 hardware required you to "Display" a
full line of it first, which could take quite a while, since the Selectric
had a wide carriage and typing some strange BCD characters required several
overstrikes. So impatient operators and programmers quickly learned that you
could do the following:

1. Hit <RESET> button.

2. Turn mode switch to <DISPLAY>, type address "00000".

3. Machine begins typing out core [yes, I mean *CORE*] starting
   at location 0.

4. Reach under the top of the Selectric's case, grasp the
   "margin-return bail" with the tip of a finger or two and
   pull it up briefly (and quickly, or the bouncing bar will
   chew your fingers!). An experienced operator could do this
   before it had typed ~15% of a line.

5. The carriage will return, JUST AS IF THE CARRIAGE HAD HIT
   THE RIGHT MARGIN, and continue typing on the next line.

6. Turn mode switch to <ALTER>, begin typing in the shoelace
   [given in the earlier article: ^L%B000012$^N].

7. Turn mode switch to <NORMAL>, hit <RESET>, <START>, and away we go...


-Rob

-----
Rob Warnock, PP-ASEL-IA		<rpw3@rpw3.org>
627 26th Avenue			<URL:http://rpw3.org/>
San Mateo, CA 94403		(650)572-2607

######

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Glen Herrmannsfeldt <gah@ugcs.caltech.edu> wrote:
+---------------
| The PDP-10, with word addressable 36 bit words (and instructions)
| stored five 7 bit characters per word for text data.
+---------------

And six 6-bit characters per word for file names and names of
operating system calls.

And four 9-bit characters per word when somebody tried to write a
C compiler for it...  ;-}  ;-}

The PDP-10 called *all* of those sizes "bytes", by the way, and
the native "LoaD Byte" (LDB) and "DePosit Byte" (DPB) instructions
could deal with any byte size from 0 to 36 bits. [Yes, 0. An LDB
using a byte pointer that specified 0-bit bytes resulted in all
zeroes in the target register, and a DPB of the same thing was
a no-op. Quite useful, occasionally...]

You could even mix byte sizes within the same word (though couldn't
easily use the auto-increment features of ILDB & IDPB in that case),
which when combined with the fact that byte pointers (the kind of
descriptors that LDB & DPB operated on) could specify index registers
to add to the target word address allowed an *extremely* dense packing
of character attributes for lexical parsing. Think of C's "ctype" table, 
only with many, many more "bit strips" involved...


-Rob

-----
Rob Warnock, PP-ASEL-IA		<rpw3@rpw3.org>
627 26th Avenue			<URL:http://rpw3.org/>
San Mateo, CA 94403		(650)572-2607

######

From: Sander Vesik <sander@haldjas.folklore.ee>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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In comp.arch bfranchuk@jetnet.ab.ca wrote:
> Glen Herrmannsfeldt wrote:
> 
> Only if you want to market bigger numbers of memory size.
> I have yet to see a good reason for bytes 8 bits wide.

It is probably the best 2^n size for bytes, unless you worship UTF-16. For
the general case, 2^n sized bytes are better than non-2^n sized bytes.

> Ben.

-- 
	Sander

+++ Out of cheese error +++

######

From: "Rupert Pigott" <roo@dark-try-removing-this-boong.demon.co.uk>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Tue, 25 Feb 2003 16:54:07 -0000
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"Robert A Duff" <bobduff@shell01.TheWorld.com> wrote in message
news:wccsmuce4ex.fsf@shell01.TheWorld.com...
> Sander Vesik <sander@haldjas.folklore.ee> writes:
>
> > It is probably the best 2^n size for bytes, unless you worship UTF-16.
For
> > the general case, 2^n sized bytes are better than non-2^n sized bytes.
>
> Why?
>
> Another question:  Why have bit-addressable machines never caught on?
> It would save a lot of shifting and masking if I could load, say, any
> power-of-2 sized bitfield into a register.

[SNIP]

> If the above questions are stupid, it's because I'm a software guy.  ;-)

I got a chance to ask microprocessor designers
directly... They looked at me a bit funny asked
what was wrong with shift/or/and. :)

Cheers,
Rupert

######

From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Newsgroups: comp.arch,alt.folklore.computers
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Subject: Re: Antiquity of Byte-Word addressing?
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"Rupert Pigott" <roo@dark-try-removing-this-boong.demon.co.uk> wrote in
message news:1046192047.679588@saucer.planet.gong...
> "Robert A Duff" <bobduff@shell01.TheWorld.com> wrote in message
> news:wccsmuce4ex.fsf@shell01.TheWorld.com...
> > Sander Vesik <sander@haldjas.folklore.ee> writes:
(snip)
> > > For the general case, 2^n sized bytes are better than
> > >non-2^n sized bytes.
> >
> > Why?

If all you need to do are word operations, like many numerical analysis
routines, then you don't care about byte size, and it doesn't make much
difference what the word size is.   The popular 32 and 64 bit floating point
types are likely not optimal sizes.  Often 32 isn't quite enough, but 64 is
much more than needed.

For character operations, you want a data type big enough to hold every
character in the character set, but not much more.

The one time it matters is if you do want to do bit operations, like bit
mapped graphics.

Similarly for 2**n bytes/word, so that you can address bytes using low bits
of a word address.

> > Another question:  Why have bit-addressable machines never caught on?
> > It would save a lot of shifting and masking if I could load, say, any
> > power-of-2 sized bitfield into a register.

Well, there was the CM-2.

> [SNIP]
>
> > If the above questions are stupid, it's because I'm a software guy.  ;-)
>
> I got a chance to ask microprocessor designers
> directly... They looked at me a bit funny asked
> what was wrong with shift/or/and. :)

For high performance, the memory bus should be wide, and aligned operations
are then easy to do.  Unaligned operations require a complicated logic block
to rearrange the bits, and possibly multiple memory cycles.  This logic is
in the critical path between memory (or cache) and the processor registers.

-- glen

######

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Subject: Re: Antiquity of Byte-Word addressing?
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From: haynes@alumni.uark.edu (Jim Haynes)
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IBM 7030 (STRETCH) was addressable to the bit level - but then it was a
research project.  Some features of STRETCH showed up in S/360, but bit
addressing was one that didn't make it.  My guess is that three additional
address bits (to get from 8-bit bytes to 1-bit bytes) perhaps wasted more
space in programs than it saved by making it easy to pack things into 
bytes of any 2^N size.

Then in modern times we have so much memory that there is a lot less need
to pack things at all.

I believe STRETCH was the first IBM machine to have powers-of-2 data sizes.
Someone asked why 8-bit bytes; and I would say that it sorta falls out when
you consider everything.  6 bits is not enough if you want to have an upper
and lower case alphabet.  Once you go to 8 bits you can also use it to
pack two 4-bit decimal digits into a byte.  One could argue that packed
decimal was a mistake on IBMs part, but then they were working with
ideas of small memories at the low end of the line that were to prove
unrealistic.

The Burroughs B-1700 is the other machine I'm aware of addressable to the
bit level.  It was well liked for what it did, but not a design that could
easily be scaled up to a high-performance machine.

######

From: Sander Vesik <sander@haldjas.folklore.ee>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Tue, 25 Feb 2003 20:18:43 +0000 (UTC)
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In comp.arch Robert A Duff <bobduff@shell01.theworld.com> wrote:
> Sander Vesik <sander@haldjas.folklore.ee> writes:
> 
>> It is probably the best 2^n size for bytes, unless you worship UTF-16. For
>> the general case, 2^n sized bytes are better than non-2^n sized bytes.
> 
> Why?
> 
> Another question:  Why have bit-addressable machines never caught on?
> It would save a lot of shifting and masking if I could load, say, any
> power-of-2 sized bitfield into a register.

Will the added complexity make teh ned reuslt faster or slower?

> 
> A related question: It seems to me infeasible to have a word-size that
> is not a power of 2 times the addressable-unit size.  Are there any
> machines that violate that?  (Other than the weird variable-word-sized
> ones folks have been talking about.)

Well, no, AFAIK, as 1 == 2^0 - but why would it be infeasible? 

> 
> If the above questions are stupid, it's because I'm a software guy.  ;-)
> 
> - Bob

-- 
	Sander

+++ Out of cheese error +++

######

From: Sander Vesik <sander@haldjas.folklore.ee>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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In comp.arch Glen Herrmannsfeldt <gah@ugcs.caltech.edu> wrote:
> 
> For high performance, the memory bus should be wide, and aligned operations
> are then easy to do.  Unaligned operations require a complicated logic block
> to rearrange the bits, and possibly multiple memory cycles.  This logic is
> in the critical path between memory (or cache) and the processor registers.
> 

Well, if the addressable unit was say 8 bits and the word was 24 bits (3 bytes),
you could have 96 bit memory interface 8-)

> -- glen
> 
> 
> 
> 

-- 
	Sander

+++ Out of cheese error +++

######

From: aek@spies.com (Al Kossow)
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Tue, 25 Feb 2003 20:28:22 +0000 (UTC)
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From article <D4Q6a.1216$M85.122922@newsread2.prod.itd.earthlink.net>, by haynes@alumni.uark.edu (Jim Haynes):
> IBM 7030 (STRETCH) was addressable to the bit level - but then it was a
> research project.
> 
> The Burroughs B-1700 is the other machine I'm aware of addressable to the
> bit level.

TI 34010 and 20 graphics processors are also bit addressable.

######

From: bfranchuk@jetnet.ab.ca
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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Sander Vesik wrote:
> Well, if the addressable unit was say 8 bits and the word was 24 bits (3 bytes),
> you could have 96 bit memory interface 8-)

The real advantage of a power of 2 for short data is to calculate word 
to byte
addresses. Quickly what 6321(octal) / 3 and mod 3 :)
Ben.

######

From: Peter da Silva <peter@abbnm.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Tue, 25 Feb 2003 14:42:40 -0600
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Robert A Duff wrote:
> Another question:  Why have bit-addressable machines never caught on?

It took a while for byte-addressible machines to catch on as it 
is, because you blow a couple of address bits that could be used 
to run larger programs or fit more instructions or registers in a 
word.

Bit-addressible would blow another three bits.

A 32-bit bit-addressible machine would have run out of address 
space on commodity PCs already.
-- 
`-_-'   Ar rug tú barróg ar do mhactíre inniu?
  'U`    Peter da Silva

######

From: Peter da Silva <peter@abbnm.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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Robert A Duff wrote:
> But that point-of-view says machines should be word addressable.

Yes, and? Machines probably would be word-addressible if it didn't 
  make the overall system faster because we do so much text 
hacking these days.

> Machines are (I presume) 8-bit-byte addressable because it makes
> loading and storing 8-bit bytes more efficient.  So why not go all the
> way and make loaded and stores of 4-bit and 1-bit quentities efficient,
> too?

Would the overall system speed be improved by adding 3 new 
adressing modes and cutting the available address space by a 
factor of 8, if you could access smaller objects directly?

> Lots of data is characters, but that doesn't really explain it.  After
> all, characters were 7 bits, or 6 bits, back when 8-bit-byte
> addressability started becoming popular.

The IBM-360, the first big-time byte banger, had 8-bit characters.
-- 
`-_-'   Ar rug tú barróg ar do mhactíre inniu?
  'U`    Peter da Silva

######

From: Nick Spalding <spalding@iol.ie>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Tue, 25 Feb 2003 22:16:15 +0000
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Peter da Silva wrote, in <b3gkjd$59d$1@jeeves.eng.abbnm.com>:

> Robert A Duff wrote:
> > Another question:  Why have bit-addressable machines never caught on?
> 
> It took a while for byte-addressible machines to catch on as it 
> is, because you blow a couple of address bits that could be used 
> to run larger programs or fit more instructions or registers in a 
> word.
> 
> Bit-addressible would blow another three bits.
> 
> A 32-bit bit-addressible machine would have run out of address 
> space on commodity PCs already.

And the 360, where 8-bit bytes came into the mainstream, was only 24-bit
addressable.  Those 3 bits certainly couldn't be spared there.
-- 
Nick Spalding

######

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Sander Vesik wrote:
> 
> In comp.arch bfranchuk@jetnet.ab.ca wrote:
> > Glen Herrmannsfeldt wrote:
> >
> > Only if you want to market bigger numbers of memory size.
> > I have yet to see a good reason for bytes 8 bits wide.
> 
> It is probably the best 2^n size for bytes, unless you worship UTF-16. For
> the general case, 2^n sized bytes are better than non-2^n sized bytes.

Why? What's wrong with 9-bit bytes on a system with 36-bit words?

######

Message-ID: <3E5BEC57.726CFD0E@yahoo.com>
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Rupert Pigott wrote:
> >
> > Another question:  Why have bit-addressable machines never caught on?
> > It would save a lot of shifting and masking if I could load, say, any
> > power-of-2 sized bitfield into a register.
> 
> [SNIP]
> 
> > If the above questions are stupid, it's because I'm a software guy.  ;-)
> 
> I got a chance to ask microprocessor designers
> directly... They looked at me a bit funny asked
> what was wrong with shift/or/and. :)

In general, probably nothing, but trying to move a n-bit (greater than
2xregister size, e.g.) unaligned bit field to another with a different
alignment is a nightmare.

######

From: mccalpin@gmp246.austin.ibm.com (McCalpin)
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Tue, 25 Feb 2003 22:31:16 +0000 (UTC)
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In article <D4Q6a.1216$M85.122922@newsread2.prod.itd.earthlink.net>,
Jim Haynes <jhaynes@alumni.uark.edu> wrote:
>
>The Burroughs B-1700 is the other machine I'm aware of addressable to the
>bit level.  

Don't forget the CDC Cyber 200 series (and its follow-on the ETA-10).

Bit addressible, with bit vectors (up to length 65535) as a native 
data type.

Of course, instructions that worked on larger data types were 
restricted to aligned data.   Still bit-addressed, but the bottom
bits had to be zero for FP and such.

-- 
John D. McCalpin, Ph.D.           mccalpin@austin.ibm.com
Senior Technical Staff Member     IBM POWER Microprocessor Development
    "I am willing to make mistakes as long as
     someone else is willing to learn from them."

######

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Peter da Silva wrote:
> 
> Robert A Duff wrote:
> > Another question:  Why have bit-addressable machines never caught on?
> 
> It took a while for byte-addressible machines to catch on as it
> is, because you blow a couple of address bits that could be used
> to run larger programs or fit more instructions or registers in a
> word.
> 
> Bit-addressible would blow another three bits.
> 
> A 32-bit bit-addressible machine would have run out of address
> space on commodity PCs already.

I'd be happy with a few bit instructions similar to the character
instructions on word-oriented machines.  Load source and destination
byte (word) address, source and destination bit indices, number if bits,
and fire up a move, compare, AND, OR, or whatever.

######

From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Newsgroups: comp.arch,alt.folklore.computers
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"Robert A Duff" <bobduff@shell01.TheWorld.com> wrote in message
news:wccfzqcovaj.fsf@shell01.TheWorld.com...
>
(snip regarding bit/byte addressability)
>
> Yes, 1=2^0, so I'm assuming that is one feasible alternative (i.e. word
> addressing).  I say it's infeasible to have word-size not a power-or-2
> times addressable-unit size, because I presume modern proecessors need
> to quickly detect unaligned memory accesses.  (True?)  I mean, they all
> either trap on that, or do something slower on that, so I assume they
> want to detect it by looking at the low-order bits (not by dividing by 3
> or some such).

It isn't that they do it to test the alignment, but to actually load the
data.

The memory might return a fullword when given an address.  The processor
must decide which address to give to memory.   I would expect a binary
machine with three bytes per word to address them as multiples of four, such
that every fourth byte does not exist.  This would be a little inconvenient
to use, but the hardware isn't hard.  Then again, on a trinary machine...

-- glen

######

From: "Peter \"Firefly\" Lund" <firefly@diku.dk>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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On Tue, 25 Feb 2003, Robert A Duff wrote:

> I don't agree.  Packing things reduces caches misses.

The first meaningful thing you have said in this thread :)

-Peter

"Algol 60 was not only an improvement on its predecessors,
 but also on nearly all its successors."
  -- C.A.R. Hoare

######

From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
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"Nick Spalding" <spalding@iol.ie> wrote in message
news:mmqn5vc5p430608lpcc3p0cu3o3lmbanls@4ax.com...
> Peter da Silva wrote, in <b3gkjd$59d$1@jeeves.eng.abbnm.com>:
>
> > Robert A Duff wrote:
> > > Another question:  Why have bit-addressable machines never caught on?
> >
> > It took a while for byte-addressible machines to catch on as it
> > is, because you blow a couple of address bits that could be used
> > to run larger programs or fit more instructions or registers in a
> > word.
> >
> > Bit-addressible would blow another three bits.
> >
> > A 32-bit bit-addressible machine would have run out of address
> > space on commodity PCs already.
>
> And the 360, where 8-bit bytes came into the mainstream, was only 24-bit
> addressable.  Those 3 bits certainly couldn't be spared there.

Two megabytes was big for a 360.  Those bytes are all magnetic cores with
wires through them!   Most models didn't have 24 bits of physical address,
and no virtual memory yet.

I think the high end 370's (before the 303x series) had a maximum of 8MB
physical memory, though 16MB virtual, and now monolithic memory.

-- glen

######

From: Peter da Silva <peter@abbnm.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Tue, 25 Feb 2003 16:53:44 -0600
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Robert A Duff wrote:
> I don't know.  As a software guy, I'm asking just that question.  Where
> is the added complexity (in the hardware) that makes loading (say) a
> 2-bit "byte" into a register any more difficult than loading an 8-bit
> quantity?

You need to widen the instruction field that indictes it's loading 
a word, halfword, or byte by 3 bits.

You need to widen the instruction field that contains the address 
by 3 bits.

You need to decide what to do about the instructions that no 
longer fit into the ABI.
-- 
`-_-'   Ar rug tú barróg ar do mhactíre inniu?
  'U`    Peter da Silva

######

From: Peter da Silva <peter@abbnm.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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Robert A Duff wrote:
> Why didn't, for example, the Alpha provide bit-level addresses.

Because it was a word addr... oh, you noticed.
-- 
`-_-'   Ar rug tú barróg ar do mhactíre inniu?
  'U`    Peter da Silva

######

From: D.C.Wood@ukc.ac.uk (dcw)
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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In article <fYN6a.257531$HN5.1105169@rwcrnsc51.ops.asp.att.net>,
Glen Herrmannsfeldt <gah@ugcs.caltech.edu> wrote:

>If all you need to do are word operations, like many numerical analysis
>routines, then you don't care about byte size, and it doesn't make much
>difference what the word size is.   The popular 32 and 64 bit floating point
>types are likely not optimal sizes.  Often 32 isn't quite enough, but 64 is
>much more than needed.

Long ago there was a tradition of 6/12/24/48-bit machines, at least in the UK
(Atlas has been mentioned before).  48 bits is a nice size for floating point.
But 6 bits isn't enough for a sensible character set, though 7 would have
been until recently.

	David

######

From: jmfbahciv@aol.com
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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Xref: chonsp.franklin.ch alt.folklore.computers:130417

In article <mddhear6h2w.fsf@panix5.panix.com>,
   Rich Alderson <news@alderson.users.panix.com> wrote:
>jmfbahciv@aol.com writes:
>
>> Reread Stacy's post.  I merely meant to clarify that one did NOT have to 
do
>> several instructions in order to load one byte.
>
>Umm, he could have written it a little more clearly, but I understood him 
to
>refer to several *different* instructions which allowed byte access, not 
to
>having to use several instructions to access a byte.
>
>But then, I like him.
>
Sigh!  Liking the man has nothing to do with it.  Teaching had everything
to do with my comment.  Yes, I knew what he meant.  How he wrote
it could have been interpreted at least two ways.  People who
grew up at DEC are used to correcting vague documentation.  And
everybody was allowed to do that.  

/BAH
 

Subtract a hundred and four for e-mail.

######

From: D.C.Wood@ukc.ac.uk (dcw)
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Wed, 26 Feb 03 12:05:13 GMT
Organization: University of Kent at Canterbury, UK.
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Sender: D.C.Wood@ukc.ac.uk
Message-ID: <8745@myrtle.ukc.ac.uk>
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Reply-To: D.C.Wood@ukc.ac.uk (dcw)
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Xref: chonsp.franklin.ch alt.folklore.computers:130549

In article <3E5C8A7C.5080309@yahoo.com>,
M. Ranjit Mathews <ranjit_mathews@yahoo.com> wrote:
>dcw wrote:
>> In article <fYN6a.257531$HN5.1105169@rwcrnsc51.ops.asp.att.net>,
>> Long ago there was a tradition of 6/12/24/48-bit machines, at least in the UK
>> (Atlas has been mentioned before).  48 bits is a nice size for floating point.
>> But 6 bits isn't enough for a sensible character set, though 7 would have
>> been until recently.
>
>12 bits would've worked quite nicely, though. That would've covered 
>(what are now) the first 4096 Unicode characters.

Since 7 bits is enough for an alphabetic script, 12 bits would allow for
32 different alphabets, which sounds like enough for most of us. (I don't
know how many Unicode contains.)  But it would leave Chinese/Japanese/
Korean in difficulties, at least.

	David

######

From: "Charlie Gibbs" <cgibbs@kltpzyxm.invalid>
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: 26 Feb 03 11:50:48 -0800
Organization: http://extra.newsguy.com
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Xref: chonsp.franklin.ch alt.folklore.computers:130452

In article <rj57a.354$0B.32254@news.uswest.net> russ@holsclaw.nyet
(Russ Holsclaw) writes:

>The System/360 used this idea in it's purest form, in that it
>made a whole line of computers with different bus widths appear
>identical from the programmer's perspective. It did so even to
>the point that the 8-bit implementation of the architecture, the
>Model 30, still enforced the boundary-alignment requirements of
>wider-bus machines when there was no logical reason for doing so,
>apart from ensuring upward-and-downward software compatibility
>among the models. It even pretended to use a 24-bit memory
>address, when all of its address registers were only 16 bits
>wide, limiting it to 64K. It generated a program-check interrupt
>when an address was specified with any high-order one-bits, even
>though it could never have used them ... all in the interest of
>compatibility.

It made life easier for third parties who decided to hang more
memory on it.  I heard of model 30s with as much as 512K, and
personally saw one with 128K.  The address register had an extra
switch and indicator added to the front panel.  It had a bit of
a home-brewed look to it, but it seemed to work just fine.

--
/~\  cgibbs@kltpzyxm.invalid (Charlie Gibbs)
\ /  I'm really at ac.dekanfrus if you read it the right way.
 X   Top-posted messages will probably be ignored.  See RFC1855.
/ \  HTML will DEFINITELY be ignored.  Join the ASCII ribbon campaign!

######

From: jmfbahciv@aol.com
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Thu, 27 Feb 03 10:17:09 GMT
Organization: UltraNet Communications, Inc.
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Xref: chonsp.franklin.ch alt.folklore.computers:130399

In article <85adgjdrq0.fsf@junk.nocrew.org>,
   Lars Brinkhoff <lars.spam@nocrew.org> wrote:
>jmfbahciv@aol.com writes:
>> Rich Alderson <news@alderson.users.panix.com> wrote:
>> >jmfbahciv@aol.com writes:
>> > > Reread Stacy's post.  I merely meant to clarify that one did NOT
>> > > have to do several instructions in order to load one byte.
>> > Umm, he could have written it a little more clearly, but I
>> > understood him to refer to several *different* instructions which
>> > allowed byte access, not to having to use several instructions to
>> > access a byte.  But then, I like him.
>> Sigh!  Liking the man has nothing to do with it.  Teaching had
>> everything to do with my comment.  Yes, I knew what he meant.  How
>> he wrote it could have been interpreted at least two ways.  People
>> who grew up at DEC are used to correcting vague documentation.  And
>> everybody was allowed to do that.
>
>And your clarification in turn needed clarification.  [emoticon
>running from den mother]

Cooommmeeee baaacccckkkk!!!  Of course it needed clarification; 
mine usually do.  That's one of the reasons this newsgroup is 
so good. :-)

/BAH


Subtract a hundred and four for e-mail.

######

From: mwilson@the-wire.com (Mel Wilson)
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Message-ID: <7F+W+ks/KfUD089yn@the-wire.com>
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In article <3E5B031A.8070605@jetnet.ab.ca>, bfranchuk@jetnet.ab.ca wrote:
>Glen Herrmannsfeldt wrote:
>
>> Somehow halfword addressing isn't quite as convincing as quarter words.
>Only if you want to market bigger numbers of memory size.
>I have yet to see a good reason for bytes 8 bits wide.

If they were 8 bits tall, listings would be much too thick.

        Regards.        Mel.


Sorry.  Been reading Hofstadter onsubjunctivity again.

######

From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Newsgroups: comp.arch,alt.folklore.computers
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<bfranchuk@jetnet.ab.ca> wrote in message
news:3E5C03DC.5080708@jetnet.ab.ca...
> Glen Herrmannsfeldt wrote:

> > The memory might return a fullword when given an address.  The processor
> > must decide which address to give to memory.   I would expect a binary
> > machine with three bytes per word to address them as multiples of four,
such
> > that every fourth byte does not exist.  This would be a little
inconvenient
> > to use, but the hardware isn't hard.  Then again, on a trinary
machine...
>
> I thought a trinary machine used -1,0,+1 logic like here.
> http://www.trinary.cc/

You would still want memory fields to come out in powers of three.  It the
low trit is zero, a shift right multiplies by three.

-- glen

######

From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Newsgroups: comp.arch,alt.folklore.computers
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"Peter da Silva" <peter@abbnm.com> wrote in message
news:b3gsb5$8ma$3@jeeves.eng.abbnm.com...
> Robert A Duff wrote:
> > Why didn't, for example, the Alpha provide bit-level addresses.
>
> Because it was a word addr... oh, you noticed.
> --

No, the Alpha is byte addressable.   Though the original architecture only
supported 32 bit and 64 bit aligned load/stores.   Even the PC had two
RAZ/IGN (read as zero/ignore) low bits.

There are load/store unaligned instructions which ignore the low three
address bits.  (Funny definition of unaligned).  Given a byte address, one
can load the quadword (64 bits) that contains the byte, extract or modify
the byte, and then write the quadword back.

So the unaligned load/store will ignore the low bits, and the byte
extract/insert/mask will ignore the high bits.

-- glen

######

From: Peter da Silva <peter@abbnm.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Tue, 25 Feb 2003 19:37:20 -0600
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Glen Herrmannsfeldt wrote:
> No, the Alpha is byte addressable.

I need to use more smileys.
-- 
`-_-'   Ar rug tú barróg ar do mhactíre inniu?
 'U`    Peter da Silva

######

From: Andrew Reilly <andrew@gurney.reilly.home>
Subject: Re: Antiquity of Byte-Word addressing?
Newsgroups: comp.arch,alt.folklore.computers
Reply-To: areilly@bigpond.net.au
Organization: just me
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On Wed, 26 Feb 2003 10:31:42 +1100, Robert A Duff wrote:
> So why not bit-addresses?  (Other than historical reasons?)

The TI340 graphics processor was a 32-bit core with bit-addressed memory.

--
Andrew

######

From: Terje Mathisen <terje.mathisen@hda.hydro.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Wed, 26 Feb 2003 08:25:38 +0100
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Peter Flass wrote:
> Rupert Pigott wrote:
> 
>>>Another question:  Why have bit-addressable machines never caught on?
>>>It would save a lot of shifting and masking if I could load, say, any
>>>power-of-2 sized bitfield into a register.
>>
>>[SNIP]
>>
>>
>>>If the above questions are stupid, it's because I'm a software guy.  ;-)
>>
>>I got a chance to ask microprocessor designers
>>directly... They looked at me a bit funny asked
>>what was wrong with shift/or/and. :)
> 
> In general, probably nothing, but trying to move a n-bit (greater than
> 2xregister size, e.g.) unaligned bit field to another with a different
> alignment is a nightmare.

I've found that N+1 can be OK, since that's the maximum size that won't 
ever span three words worth of memory.

You need two words just to handle any form of misalignement at all, 
going to three is lots tougher.

OTOH, I did exactly that on my Pentomino solver: I start with up to 84 
bits or so, loaded into three 32-bit registers.

As part of the board gets filled, the active area shrinks, so when it 
drops below 65 and 33 I switch to a two and one-register versions of the 
inner loop.

Terje
-- 
- <Terje.Mathisen@hda.hydro.com>
"almost all programming can be viewed as an exercise in caching"

######

From: Terje Mathisen <terje.mathisen@hda.hydro.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Wed, 26 Feb 2003 08:28:14 +0100
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Peter Flass wrote:
> I'd be happy with a few bit instructions similar to the character
> instructions on word-oriented machines.  Load source and destination
> byte (word) address, source and destination bit indices, number if bits,
> and fire up a move, compare, AND, OR, or whatever.

As others have written, this has been done on the PDPs previously.

Today, the cpu overhead of unpacking a few fields like this disappears 
in the noise compared with the cost of loading the data item (from RAM) 
in the first place.

Terje

-- 
- <Terje.Mathisen@hda.hydro.com>
"almost all programming can be viewed as an exercise in caching"

######

From: Terje Mathisen <terje.mathisen@hda.hydro.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Wed, 26 Feb 2003 08:29:20 +0100
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Robert A Duff wrote:
> haynes@alumni.uark.edu (Jim Haynes) writes:
> 
> 
>>Then in modern times we have so much memory that there is a lot less need
>>to pack things at all.
> 
> 
> I don't agree.  Packing things reduces caches misses.

My rule of thumb is that a program which is half as big (code+data) runs 
in half the time.

Terje

-- 
- <Terje.Mathisen@hda.hydro.com>
"almost all programming can be viewed as an exercise in caching"

######

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Subject: Re: Antiquity of Byte-Word addressing?
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In article <b3hqcg$b1k$3@vkhdsu24.hda.hydro.com>,
Terje Mathisen  <terje.mathisen@hda.hydro.com> wrote:

>My rule of thumb is that a program which is half as big (code+data) runs 
>in half the time.

Great, then we can all turn off unrolling in our compilers. Well, all
except the IA-64 guys, they have these rotating registers, see...

-- greg

######

From: Terje Mathisen <terje.mathisen@hda.hydro.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Wed, 26 Feb 2003 10:26:44 +0100
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Greg Lindahl wrote:
> In article <b3hqcg$b1k$3@vkhdsu24.hda.hydro.com>,
> Terje Mathisen  <terje.mathisen@hda.hydro.com> wrote:
> 
> 
>>My rule of thumb is that a program which is half as big (code+data) runs 
>>in half the time.
> 
> 
> Great, then we can all turn off unrolling in our compilers. Well, all

Greg, where did I say that?

 From all the posts I've made here (i.e. comp.arch, not a.f.c) over 
nearly 10 years, many of them shoving carefully unrolled/pipelined asm 
code, it should be clear that I know full well the value of getting 
those inner loops as fast as possible.

It is still true that if I can do the same task with less code, it 
nearly always (i.e. 'Rule of Thumb') turns out to be faster as well.

Terje

-- 
- <Terje.Mathisen@hda.hydro.com>
"almost all programming can be viewed as an exercise in caching"

######

From: Nick Spalding <spalding@iol.ie>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Wed, 26 Feb 2003 10:09:35 +0000
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Glen Herrmannsfeldt wrote, in
<iqS6a.260654$HN5.1109496@rwcrnsc51.ops.asp.att.net>:

> 
> "Nick Spalding" <spalding@iol.ie> wrote in message
> news:mmqn5vc5p430608lpcc3p0cu3o3lmbanls@4ax.com...
> > Peter da Silva wrote, in <b3gkjd$59d$1@jeeves.eng.abbnm.com>:
> >
> > > Robert A Duff wrote:
> > > > Another question:  Why have bit-addressable machines never caught on?
> > >
> > > It took a while for byte-addressible machines to catch on as it
> > > is, because you blow a couple of address bits that could be used
> > > to run larger programs or fit more instructions or registers in a
> > > word.
> > >
> > > Bit-addressible would blow another three bits.
> > >
> > > A 32-bit bit-addressible machine would have run out of address
> > > space on commodity PCs already.
> >
> > And the 360, where 8-bit bytes came into the mainstream, was only 24-bit
> > addressable.  Those 3 bits certainly couldn't be spared there.
> 
> Two megabytes was big for a 360.  Those bytes are all magnetic cores with
> wires through them!   Most models didn't have 24 bits of physical address,
> and no virtual memory yet.
> 
> I think the high end 370's (before the 303x series) had a maximum of 8MB
> physical memory, though 16MB virtual, and now monolithic memory.

More significant would be the effect on the 12-bit displacement field in
the instructions.  The scope of one base register would be reduced to 512
bytes.
-- 
Nick Spalding

######

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dcw wrote:
> In article <fYN6a.257531$HN5.1105169@rwcrnsc51.ops.asp.att.net>,
> Long ago there was a tradition of 6/12/24/48-bit machines, at least in the UK
> (Atlas has been mentioned before).  48 bits is a nice size for floating point.
> But 6 bits isn't enough for a sensible character set, though 7 would have
> been until recently.

12 bits would've worked quite nicely, though. That would've covered 
(what are now) the first 4096 Unicode characters.

######

From: Jouni Matti Juhani Osmala <josmala@timantti.hut.fi>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: 26 Feb 2003 13:36:16 +0200
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Robert A Duff <bobduff@shell01.TheWorld.com> writes:

> Peter da Silva <peter@abbnm.com> writes:
> 
> > Robert A Duff wrote:
> > > Another question:  Why have bit-addressable machines never caught on?
> > 
> > It took a while for byte-addressible machines to catch on as it is,
> > because you blow a couple of address bits that could be used to run
> > larger programs or fit more instructions or registers in a word.
> 
> OK, but with 32 bits of address space (say, in the late 70's, like the
> VAX), 4G of address space seemed like a lot.  Dividing that by 8 was no
> big deal (in those days).  And nowadays, we have 64-bit address space.
> So why not bit-addresses?  (Other than historical reasons?)
> 
> > Bit-addressible would blow another three bits.
> > 
> > A 32-bit bit-addressible machine would have run out of address space on
> > commodity PCs already.
> 
> Indeed.  Remember 640K? ;-)
> 
> Why didn't, for example, the Alpha provide bit-level addresses.
> I guess that's a bad example, since it didn't "really" do byte
> addressing either...
> 
> - Bob

Additional shifter in architecture, would slow ALL memory accesses.
Alpha didn't do real byte addressing exacly this reason.

Now how bit addressing would work, for WORD.
Get two words from cache. Then shift both correct amount to match word,
and give the result in next cycle.
Store needs to get those two words, shift the storing word to correct place,
and put the word back.
Now if you wanted to have BIT operations in memory.
Get 32, or 64 bit what ever width your cache bus is, and shift the bit to
proper place, mask unnecessary bits out, and give the result in next cycle.
Store gets the cache bus width of stuff back in and shift your bit to 
correct place and put it back to cache.

Now if you do it with byte addressing its somewhat faster because the 
delay of shifter depends somewhat how many bits you use. At time when
everything was logic limited that was linear, today, I don't know the
equation.

Now byte addressing for 64 bits thats 3 bit controls, and bit addressing 
doubles that. Now that increases to your L1 cache latency, somewhat. And
for misallingned accesses you still have to pay additional penalty for getting
another word from cache. So save one shift, add one extra cycle latency for
memory operation for doing the shift. And probably increase the pain in 
implementing, ooe memory operations. So the bit addressing is considered,
a net loss. 

Jouni Osmala
Helsinki University of Technology.
Electrical Engineering

######

From: Sander Vesik <sander@haldjas.folklore.ee>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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In comp.arch Jouni Matti Juhani Osmala <josmala@timantti.hut.fi> wrote:
> Robert A Duff <bobduff@shell01.TheWorld.com> writes:
> 
>> Peter da Silva <peter@abbnm.com> writes:
>> 
>> > Robert A Duff wrote:
>> > > Another question:  Why have bit-addressable machines never caught on?
>> > 
>> > It took a while for byte-addressible machines to catch on as it is,
>> > because you blow a couple of address bits that could be used to run
>> > larger programs or fit more instructions or registers in a word.
>> 
>> OK, but with 32 bits of address space (say, in the late 70's, like the
>> VAX), 4G of address space seemed like a lot.  Dividing that by 8 was no
>> big deal (in those days).  And nowadays, we have 64-bit address space.
>> So why not bit-addresses?  (Other than historical reasons?)
>> 
>> > Bit-addressible would blow another three bits.
>> > 
>> > A 32-bit bit-addressible machine would have run out of address space on
>> > commodity PCs already.
>> 
>> Indeed.  Remember 640K? ;-)
>> 
>> Why didn't, for example, the Alpha provide bit-level addresses.
>> I guess that's a bad example, since it didn't "really" do byte
>> addressing either...
>> 
>> - Bob
> 
> Additional shifter in architecture, would slow ALL memory accesses.
> Alpha didn't do real byte addressing exacly this reason.

No, you could build the cpu with two load units, one that didn't have
a shifter and one that did, and either burn a write port on it or
multiplex them. 

> Jouni Osmala
> Helsinki University of Technology.
> Electrical Engineering

-- 
	Sander

+++ Out of cheese error +++

######

From: Lars Brinkhoff <lars.spam@nocrew.org>
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Subject: Re: Antiquity of Byte-Word addressing?
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jmfbahciv@aol.com writes:
> Rich Alderson <news@alderson.users.panix.com> wrote:
> >jmfbahciv@aol.com writes:
> > > Reread Stacy's post.  I merely meant to clarify that one did NOT
> > > have to do several instructions in order to load one byte.
> > Umm, he could have written it a little more clearly, but I
> > understood him to refer to several *different* instructions which
> > allowed byte access, not to having to use several instructions to
> > access a byte.  But then, I like him.
> Sigh!  Liking the man has nothing to do with it.  Teaching had
> everything to do with my comment.  Yes, I knew what he meant.  How
> he wrote it could have been interpreted at least two ways.  People
> who grew up at DEC are used to correcting vague documentation.  And
> everybody was allowed to do that.

And your clarification in turn needed clarification.  [emoticon
running from den mother]

-- 
Lars Brinkhoff,         Services for Unix, Linux, GCC, PDP-10, HTTP
Brinkhoff Consulting    http://www.brinkhoff.se/

######

From: "Russ Holsclaw" <russ@holsclaw.nyet>
Newsgroups: alt.folklore.computers
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<jmfbahciv@aol.com> wrote in message
news:b3iald$msj$1@bob.news.rcn.net...
> <snip> People who
> grew up at DEC are used to correcting vague documentation.  And
> everybody was allowed to do that.

Ah! Now I understand where Microsoft's documentation traditions
began...
Thank you. :-)

Seriously, it's pretty clear to me that the original post had to
do with the concept of using the low-order bits of an address to
specify a "byte" out of the machine's full bus-width, while using
the remaining bits of the address in the conventional way: to
address a memory array.

The System/360 used this idea in it's purest form, in that it
made a whole line of computers with different bus widths appear
identical from the programmer's perspective. It did so even to
the point that the 8-bit implementation of the architecture, the
Model 30, still enforced the boundary-alignment requirements of
wider-bus machines when there was no logical reason for doing so,
apart from ensuring upward-and-downward software compatibility
among the models. It even pretended to use a 24-bit memory
address, when all of its address registers were only 16 bits
wide, limiting it to 64K. It generated a program-check interrupt
when an address was specified with any high-order one-bits, even
though it could never have used them ... all in the interest of
compatibility.

The model 40 implemented an 18-bit address, so it could be
expanded only as far as 256K.  Only the model 50 and up actually
implemented all 24 address bits in real hardware, although
expanding beyond 512K (19 bits) required externally-attached, and
slower, "LCS" core. In those days, even the very *idea* of 16MB
of memory seemed like an extravagant science-fictional dream.
...then Gordon Moore gave voice to his Law, and the rest, as they
say...

######

From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Newsgroups: comp.arch,alt.folklore.computers
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"Nick Spalding" <spalding@iol.ie> wrote in message
news:th4p5vclijubi6rufmc8cq5ha5fo3d2mfv@4ax.com...
(snip regarding bit addressability and S/360)

> More significant would be the effect on the 12-bit displacement field in
> the instructions.  The scope of one base register would be reduced to 512
> bytes.

Well, except that IBM didn't, until recently do what some others have done.
That is, make the displacement in units of the data being addressed.   Note
that relative branch instructions use two byte units, as instructions
addresses must be even.

There are architectures where index registers index in units of the size of
the data being addressed.

-- glen

######

From: ben franchuk <bfranchuk@jetnet.ab.ca>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Wed, 26 Feb 2003 11:15:06 -0700
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M. Ranjit Mathews wrote:
 > 12 bits would've worked quite nicely, though. That would've covered
 > (what are now) the first 4096 Unicode characters.

Well I am working on a home-brew 24/12 bit computer and I use signed
12 bit data for short ints. This gives me only 2048 unicode characters. :)
	I really wish  NAPLPS has been implimented instead of the weird coding
we have for characters and to have replaced HTML for web pages.

	If you ever want a a nice 24 bit computer to play with I can send the
schematics* once I finish them. The real problem with a 24 bit machine
is that you are limited to 16 meg adress space.
Ben.
* about 150 74LSXX chips not counting memory and serial I/O.
Note this computer while it will have da blinking lights, it not real
because I don't plan to put wheels on it.:D

######

From: Terje Mathisen <terje.mathisen@hda.hydro.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Wed, 26 Feb 2003 21:04:19 +0100
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Glen Herrmannsfeldt wrote:
> Well, except that IBM didn't, until recently do what some others have done.
> That is, make the displacement in units of the data being addressed.   Note
> that relative branch instructions use two byte units, as instructions
> addresses must be even.
> 
> There are architectures where index registers index in units of the size of
> the data being addressed.

Random size items (i.e. a general integer multiply in the addressing 
unit), or just some powers of two?

x86 has the latter for sizes 1, 2, 4 and 8 bytes, ARM has presumably any 
power since shifts are free.

Terje
-- 
- <Terje.Mathisen@hda.hydro.com>
"almost all programming can be viewed as an exercise in caching"

######

Message-ID: <3E5D1DA8.CB32F1DA@yahoo.com>
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ben franchuk wrote:
> M. Ranjit Mathews wrote:
> 
> > 12 bits would've worked quite nicely, though. That would've
> > covered (what are now) the first 4096 Unicode characters.
> 
> Well I am working on a home-brew 24/12 bit computer and I use
> signed 12 bit data for short ints. This gives me only 2048
> unicode characters. :)
>
> I really wish  NAPLPS has been implimented instead of the weird
> coding we have for characters and to have replaced HTML for web
> pages.
> 
> If you ever want a a nice 24 bit computer to play with I can
> send the schematics* once I finish them. The real problem with
> a 24 bit machine is that you are limited to 16 meg adress space.
> 
> * about 150 74LSXX chips not counting memory and serial I/O.
> Note this computer while it will have da blinking lights, it not
> real because I don't plan to put wheels on it.:D

Bow to progress and use PALs and GALs.

-- 
Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net)
   Available for consulting/temporary embedded and systems.
   <http://cbfalconer.home.att.net>  USE worldnet address!

######

From: Alex Colvin <alexc@std.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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>> Why didn't, for example, the Alpha provide bit-level addresses.

>Because it was a word addr... oh, you noticed.

Isn't the alpha byte-addressed (at least for data)? Regardless of whether
it supports byte accesses?


-- 
	mac the naïf

######

From: Alex Colvin <alexc@std.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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>There are architectures where index registers index in units of the size of
>the data being addressed.


Indeed, the Honeywell DPS6's were word-addresses for the base address, but
an index register offset by doubleword, word, byte, or bit. So with an
index you could bit-address, but only in a 64K range.
-- 
	mac the naïf

######

From: mwilson@the-wire.com (Mel Wilson)
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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In article <b3jc80$ehi$2@pcls4.std.com>, Alex Colvin <alexc@std.com> wrote:
>>There are architectures where index registers index in units of the size of
>>the data being addressed.
>
>Indeed, the Honeywell DPS6's were word-addresses for the base address, but
>an index register offset by doubleword, word, byte, or bit. So with an
>index you could bit-address, but only in a 64K range.

   In a way.  Index Registers were 18 bits wide, so index
modification could address within 262,144 bits .. offset
from the address set in an Address Register or Operand
Descriptor, which could in principle address any bit within
262,144 words.

   I guess I'm referring to the Extended Instruction Set,
which implemented a full slate of 2- nnd 3-operand
instructions on fields of 9, 6, 4 and 1 bit elements.  Index
modification of these instructions worked at the element
level, so (eg.) incrementing an index register went to the
next byte, character, nybble, or bit depending on the
instruction.

   The pre-Extended instruction set addressed 36-bit words,
with some special indirect pointer words that made it
possible to work with 9 and 6 bit characters.

        Regards.        Mel.

######

From: bfranchuk@jetnet.ab.ca
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Wed, 26 Feb 2003 15:30:45 -0700
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CBFalconer wrote:

> Bow to progress and use PALs and GALs.

I use computers, I don't worship them!

I have looked at GALS and come to the
conclusion they are not practical for
this Computer. Providing you have the
TTL chips you don't need fancy ( read
$$$ ) development software.Quad paper
works quite fine. While I plan to have
PCB's made TTL still is a good choice for
home brew-R&D as you can wire wrap the
stuff,find data sheets and the chips and
sockets still can be found cheap.
	The alu data path makes good use
of MSI chips. While the control logic uses
a LOT of gates the logic is too random
to make effective use of the limited
number of inputs on the GAL chips.Another
major factor is I don't have programmer.
Hard coded logic has the advantage of
NOT needing programing. I do however
plan to use flash memory for bootstrapping
the system but the good old lights and
switches front panel will be used for
system testing and data entry even if
I don't have a CPU installed.
Ben.

######

From: ranjit_mathews@yahoo.com (M. Ranjit Mathews)
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: 26 Feb 2003 15:59:32 -0800
Organization: http://groups.google.com/
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ben franchuk <bfranchuk@jetnet.ab.ca> wrote ...
> M. Ranjit Mathews wrote:
>  > 12 bits would've worked quite nicely, though. That would've covered
>  > (what are now) the first 4096 Unicode characters.
> Well I am working on a home-brew 24/12 bit computer and I use signed
> 12 bit data for short ints. This gives me only 2048 unicode characters. :)
> 	If you ever want a a nice 24 bit computer to play with I can send the
> schematics* once I finish them. The real problem with a 24 bit machine
> is that you are limited to 16 meg adress space.

Not necessarily. Was an 8086, a 16 bit machine, limited to 64 KB?

######

From: bfranchuk@jetnet.ab.ca
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Wed, 26 Feb 2003 17:13:53 -0700
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M. Ranjit Mathews wrote:
> Not necessarily. Was an 8086, a 16 bit machine, limited to 64 KB?

For all practical purposes you only had a 64k code segment and 64k data
segement.You also had a stack and extra segement segment but they are a 
pain to use.The MMU mapped addresses to 1 meg of memory.
IBM in its great wisdom gave us the 512kb limit of dos with the other
512 kb of upper memory filled with ROM, I/O, Ram and EMS page frames.
Ben.

######

Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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From: Tony Finch <dot@dotat.at>
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Robert A Duff <bobduff@shell01.TheWorld.com> wrote:
>
>Why didn't, for example, the Alpha provide bit-level addresses.

It might have something to do with the fact that the smallest
addressible type in C is the byte, and the performance implications
of having to multiply all size values by 8 when going from the
language level to the machine code level.

Tony.
-- 
f.a.n.finch  <dot@dotat.at>  http://dotat.at/
NORTH UTSIRE: SOUTH OR SOUTHEAST 3 OR 4. MAINLY FAIR. MODERATE OR GOOD.

######

From: Sander Vesik <sander@haldjas.folklore.ee>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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In comp.arch bfranchuk@jetnet.ab.ca wrote:
> M. Ranjit Mathews wrote:
>> Not necessarily. Was an 8086, a 16 bit machine, limited to 64 KB?
> 
> For all practical purposes you only had a 64k code segment and 64k data
> segement.You also had a stack and extra segement segment but they are a 
> pain to use.The MMU mapped addresses to 1 meg of memory.
> IBM in its great wisdom gave us the 512kb limit of dos with the other
> 512 kb of upper memory filled with ROM, I/O, Ram and EMS page frames.

Ahem -  8086 definately cannot be said to have had a MMU. And I at least
personally never saw machines that were limited to 512 k and not 640 k

> Ben.
> 

-- 
	Sander

+++ Out of cheese error +++

######

From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Newsgroups: alt.folklore.computers
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"Charlie Gibbs" <cgibbs@kltpzyxm.invalid> wrote in message
news:1442.187T2413T7105874@kltpzyxm.invalid...
> In article <rj57a.354$0B.32254@news.uswest.net> russ@holsclaw.nyet
> (Russ Holsclaw) writes:
>
(snip regarding the 360/30)

> It made life easier for third parties who decided to hang more
> memory on it.  I heard of model 30s with as much as 512K, and
> personally saw one with 128K.  The address register had an extra
> switch and indicator added to the front panel.  It had a bit of
> a home-brewed look to it, but it seemed to work just fine.

It probably voided the warranty, and I hope it wasn't leased.

-- glen

######

From: "Peter Dickerson" <p.dickerson@ntlworld.com>
Newsgroups: comp.arch,alt.folklore.computers
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Terje Mathisen wrote:
> Glen Herrmannsfeldt wrote:
>> Well, except that IBM didn't, until recently do what some others
>> have done. That is, make the displacement in units of the data being
>> addressed.   Note that relative branch instructions use two byte
>> units, as instructions addresses must be even.
>>
>> There are architectures where index registers index in units of the
>> size of the data being addressed.
>
> Random size items (i.e. a general integer multiply in the addressing
> unit), or just some powers of two?
>
> x86 has the latter for sizes 1, 2, 4 and 8 bytes, ARM has presumably
> any power since shifts are free.
>
> Terje

I was under the impression that shifts are not free on ARM, in clock cycles
at least. For example an added cycle on Xscale - Dennis is the expert on
that, I guess, but maybe it is to close to home for hime to comment.

--
Peter
Peter.Dickerson (at) ukonline (dot) co (dot) uk

######

From: Terje Mathisen <terje.mathisen@hda.hydro.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Thu, 27 Feb 2003 11:47:14 +0100
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Peter Dickerson wrote:
> Terje Mathisen wrote:
>>x86 has the latter for sizes 1, 2, 4 and 8 bytes, ARM has presumably
>>any power since shifts are free.
>>
>>Terje
> 
> 
> I was under the impression that shifts are not free on ARM, in clock cycles
> at least. For example an added cycle on Xscale - Dennis is the expert on
> that, I guess, but maybe it is to close to home for hime to comment.

OK, I remember someone posting that the latest ARM version(s) have had 
to add an extra cycle to instructions using the shift function, it did 
use to be free.

OTOH, many different x86 versions have also had a cycle penalty for some 
combination of [base + offset + scaled index] addressing.

With two-operand x86 instructions, the scaling performed in the 
addressing unit still saves a cycle and a scratch register compared to 
doing it manually with a MOV + SHL combination.

Terje

-- 
- <Terje.Mathisen@hda.hydro.com>
"almost all programming can be viewed as an exercise in caching"

######

From: Alex Colvin <alexc@std.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Thu, 27 Feb 2003 12:51:39 +0000 (UTC)
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>>>There are architectures where index registers index in units of the size of
>>>the data being addressed.

>>Indeed, the Honeywell DPS6's were word-addresses for the base address, but
>>an index register offset by doubleword, word, byte, or bit. So with an
>>index you could bit-address, but only in a 64K range.

>   In a way.  Index Registers were 18 bits wide, so index
>modification could address within 262,144 bits .. offset
>from the address set in an Address Register or Operand
>Descriptor, which could in principle address any bit within
>262,144 words.

Actually, you're probably thinking of the DPS8 mainframes from Phoenix,
originally by GE. They were word-addressed, then horribly extended.

I was thinking of the DPS6, aka Level 6, an unrelated and relatively clean
minicomputer put out by another group in Bellerica. We used one as the
front end to a DPS8.

> Regards.  Mel.

Say, you're not *the* Mel?

-- 
	mac the naïf

######

From: Keith R. Williams <krw@attglobal.net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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In article <3E5D4015.3000902@jetnet.ab.ca>, bfranchuk@jetnet.ab.ca 
says...
> CBFalconer wrote:
> 
> > Bow to progress and use PALs and GALs.
> 
> I use computers, I don't worship them!
> 
> I have looked at GALS and come to the
> conclusion they are not practical for
> this Computer. Providing you have the
> TTL chips you don't need fancy ( read
> $$$ ) development software.Quad paper
> works quite fine. While I plan to have
> PCB's made TTL still is a good choice for
> home brew-R&D as you can wire wrap the
> stuff,find data sheets and the chips and
> sockets still can be found cheap.

Use an FPGA.  Software is free for all but the largest (and expen$ive) 
parts.  You can get development boards for $100 or so.  TTL random 
logic has gone the way of the dodo.

> 	The alu data path makes good use
> of MSI chips. While the control logic uses
> a LOT of gates the logic is too random
> to make effective use of the limited
> number of inputs on the GAL chips.Another
> major factor is I don't have programmer.

No programmer needed with SRAM based FPGAs.  You can download the 
patterns or use flash.

> Hard coded logic has the advantage of
> NOT needing programing. I do however
> plan to use flash memory for bootstrapping
> the system but the good old lights and
> switches front panel will be used for
> system testing and data entry even if
> I don't have a CPU installed.

Hard wired logic has the disadvantage of being a PITA. ;-)

-- 
  Keith 

######

From: mwilson@the-wire.com (Mel Wilson)
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Message-ID: <NdhX+ks/KbNQ089yn@the-wire.com>
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Xref: chonsp.franklin.ch alt.folklore.computers:130426

In article <b3l1kr$cb7$1@pcls4.std.com>, Alex Colvin <alexc@std.com> wrote:
>>>>There are architectures where index registers index in units of the size of
>>>>the data being addressed.
>>>Indeed, the Honeywell DPS6's were word-addresses for the base address, [ ... ]
>>   In a way.  Index Registers were 18 bits wide, so index
>>modification could address within 262,144 bits [ ... ]

>Actually, you're probably thinking of the DPS8 mainframes from Phoenix,
>originally by GE. They were word-addressed, then horribly extended.

   Sorry, yes, I am.  (I rather liked the extensions.)  TVV
pointed out the gaffe, as well,
>
>I was thinking of the DPS6, aka Level 6, an unrelated and relatively clean
>minicomputer put out by another group in Bellerica. We used one as the
>front end to a DPS8.

   There were some of those connected to the corporate WAN
in Toronto, supporting a messaging system.  I could sit and
read ques.-and-ans. exchanges between DPS6 guys as far away
as Australia, and reflect that it would be neat to work on
6's.  That's as close as I got.
>
>> Regards.  Mel.
>
>Say, you're not *the* Mel?

   THE Mel would have remembered that the two computer lines
were different from the schematics.  Ah me.

######

From: Keith R. Williams <krw@attglobal.net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Thu, 27 Feb 2003 08:50:15 -0500
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In article <1046307753.454648@haldjas.folklore.ee>, 
sander@haldjas.folklore.ee says...
> In comp.arch bfranchuk@jetnet.ab.ca wrote:
> > M. Ranjit Mathews wrote:
> >> Not necessarily. Was an 8086, a 16 bit machine, limited to 64 KB?
> > 
> > For all practical purposes you only had a 64k code segment and 64k data
> > segement.You also had a stack and extra segement segment but they are a 
> > pain to use.The MMU mapped addresses to 1 meg of memory.
> > IBM in its great wisdom gave us the 512kb limit of dos with the other
> > 512 kb of upper memory filled with ROM, I/O, Ram and EMS page frames.
> 
> Ahem -  8086 definately cannot be said to have had a MMU. And I at least
> personally never saw machines that were limited to 512 k and not 640 k

Most PCs could use 704K, though it wasn't advertised. As long as one 
didn't have an EGA adapter the "A-segment" was available ("B" was the 
CGA/MCA buffer).  It took some mucking with BIOS, but it wasn't hard.

More than one code segment was pretty easy too.  Add "FAR" to the call 
and proc statements. I'm not sure what the issue is with the stack 
segment either.

-- 
  Keith

######

Message-ID: <3E5E3DFE.1213D5CF@yahoo.com>
From: CBFalconer <cbfalconer@yahoo.com>
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Subject: Re: Antiquity of Byte-Word addressing?
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"Keith R. Williams" wrote:
> 
> In article <3E5D4015.3000902@jetnet.ab.ca>, bfranchuk@jetnet.ab.ca
> says...
> > CBFalconer wrote:
> >
> > > Bow to progress and use PALs and GALs.
> >
> > I use computers, I don't worship them!
> >
> > I have looked at GALS and come to the
> > conclusion they are not practical for
> > this Computer. Providing you have the
> > TTL chips you don't need fancy ( read
> > $$$ ) development software.Quad paper
> > works quite fine. While I plan to have
> > PCB's made TTL still is a good choice for
> > home brew-R&D as you can wire wrap the
> > stuff,find data sheets and the chips and
> > sockets still can be found cheap.
> 
> Use an FPGA.  Software is free for all but the largest (and expen$ive)
> parts.  You can get development boards for $100 or so.  TTL random
> logic has gone the way of the dodo.
> 
> >       The alu data path makes good use
> > of MSI chips. While the control logic uses
> > a LOT of gates the logic is too random
> > to make effective use of the limited
> > number of inputs on the GAL chips.Another
> > major factor is I don't have programmer.
> 
> No programmer needed with SRAM based FPGAs.  You can download the
> patterns or use flash.
> 
> > Hard coded logic has the advantage of
> > NOT needing programing. I do however
> > plan to use flash memory for bootstrapping
> > the system but the good old lights and
> > switches front panel will be used for
> > system testing and data entry even if
> > I don't have a CPU installed.
> 
> Hard wired logic has the disadvantage of being a PITA. ;-)

I think he prefers to use Vero boards and discrete diodes and
transistors, with the odd resistor. :-)  Been there.

-- 
Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net)
   Available for consulting/temporary embedded and systems.
   <http://cbfalconer.home.att.net>  USE worldnet address!

######

From: bfranchuk@jetnet.ab.ca
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Thu, 27 Feb 2003 11:08:00 -0700
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Keith R. Williams wrote:

> Use an FPGA.  Software is free for all but the largest (and expen$ive) 
> parts.  You can get development boards for $100 or so.  TTL random 
> logic has gone the way of the dodo.

I have a FPGA, that is why I am going back to TTL the CPU just don't
fit in it - Altera 10K10. The main problem is getting a PROM burnt for
the system. FPGA $5, PROM $50, PROM PROGRAMMER $500. Anybody want
a FPGA protype system for a resonable price?

> No programmer needed with SRAM based FPGAs.  You can download the 
> patterns or use flash.

You still need a uP to boot up the FPGA.

> Hard wired logic has the disadvantage of being a PITA. ;-)

I find the development software a PITA that you have you spend
$$ every year and/or get a license update every few months
is a BIGGER PITA.
Who knows if the program I am running will be supported in
5 years from now. If I want to build  a new TTL computer I just
lay out a new PCB and take the chips out of the old boards.

As a side note what little I have seen of VHDL and VERLOG
I don't like, as well I have not figured how write hardware
discriptions in it at all. I have not seen any RTL software
for FPGA's. Note do to a limited budget I tend to use free
software.

I want to be hardware independant and open source with my
computer as /BAH is with living.
Ben.

######

Path: chonsp.franklin.ch!not-for-mail
From: Neil Franklin <neil@franklin.ch.remove>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: 27 Feb 2003 22:05:34 +0100
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bfranchuk@jetnet.ab.ca writes:

> Keith R. Williams wrote:
>
> > Use an FPGA.  Software is free for all but the largest (and expen$ive)
> > parts.  You can get development boards for $100 or so.  TTL random
> > logic has gone the way of the dodo.
>
> I have a FPGA, that is why I am going back to TTL the CPU just don't
> fit in it - Altera 10K10.

576 LEs. Seems to be an 24x24 grid, as far as the data sheet wants to
tell. Small. Actually smallest in the series (576 to 12160 LEs).

Today 5000 LEs is considered the place to start for general purpose
FPGA CPUs.

So that should give you about 10 times the space.


> The main problem is getting a PROM burnt for
> the system. FPGA $5, PROM $50, PROM PROGRAMMER $500. Anybody want
> a FPGA protype system for a resonable price?

Get larger FPGA for $30.

"PROM": Standard flash ROM (or battery backed SRAM) and small uC (or
even Basic stamp?) to move the date flash->FPGA, for a few $. One does
not need to use the over-expensive low-volume special PROM parts.

"Programmer": Do parallel port to the uC, the rest is software. Again
no over-expensive low-volume special stuff.

150 TTLs and their power supply will cost more (money and space). And
be slower.


> > No programmer needed with SRAM based FPGAs.  You can download the
> > patterns or use flash.
>
> You still need a uP to boot up the FPGA.

Is harmless. uCs cost nothing these days. Also program flash based
versions direct from the parallel port, no programmer.


> > Hard wired logic has the disadvantage of being a PITA. ;-)
>
> I find the development software a PITA that you have you spend
> $$ every year and/or get a license update every few months
> is a BIGGER PITA.

That is what the no-cost small-device time-unlimited hobbyist licenses
are for.


> Who knows if the program I am running will be supported in
> 5 years from now.

Under Wine and Linux that should not be a problem.


> As a side note what little I have seen of VHDL and VERLOG
> I don't like, as well I have not figured how write hardware
> discriptions in it at all.

There exist other languages, even if less known.

Worst case XDL (raw FPGA element programming), but that requires
Xilinx, AFAIK Altera has no equivalent.

XDL is actually the nearest to TTL style thinking. Work like you
had an grid of 74LS"cell" chips on an programmable PCB.

For an example of the designing style see:
http://neil.franklin.ch/Projects/PDP-10/pdp10.vv.html


> for FPGA's. Note do to a limited budget I tend to use free
> software.
>
> I want to be hardware independant and open source with my
> computer as /BAH is with living.

Reverse engineering of the FPGA tools? It is only a question of
time until it happens. Unless someone beats me, I will be doing it in
1 or 2 years.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith
- hardware runs the world, software controls the hardware
  code generates the software, have you coded today?

######

From: bfranchuk@jetnet.ab.ca
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Thu, 27 Feb 2003 16:27:07 -0700
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Neil Franklin wrote:

> 576 LEs. Seems to be an 24x24 grid, as far as the data sheet wants to
> tell. Small. Actually smallest in the series (576 to 12160 LEs).

The le's is not the problem, routing is. Anyhow this TTL design
uses 74LS670's dual port ram and that can't be emulated with this
FPGA.

> Today 5000 LEs is considered the place to start for general purpose
> FPGA CPUs.

Hardware bloat!

> So that should give you about 10 times the space.

Right now the config is about 16kb.Say 256kb for the
bigger chips do to more routing tables and easy numbers
to work  with. I plan to have 128k( 12 bits ) of memory
on the base machine. Some how having the CPU with more
memory than the computer don't feel right.

> "PROM": Standard flash ROM (or battery backed SRAM) and small uC (or
> even Basic stamp?) to move the date flash->FPGA, for a few $. One does
> not need to use the over-expensive low-volume special PARTS.

I would use CPLD's rather than a FPGA since they power up
pre-configured.

> 150 TTLs and their power supply will cost more (money and space). And
> be slower.

I am guessing at 5 amps for the power used so a
old AT power supply would be fine. Since this design is
"classic" computer design from about 1980 I don't plan to run
faster than 1 MHZ. I will use static ram and flash to emulate
good old core memory or dynamic ram/EEPROM.

> Under Wine and Linux that should not be a problem.
Sure and I need win/2010 to flush my toilet too.

If this was a commercial design, I would be using
state of the art tools and logic devices. Still
porting from TLL to other logic is fairly easy.
I am guessing I have about 32 levels of gate delay
so @ 3 ns per logic gate that is about 100 ns.
LS TTL looks to run at about 1000 ns.


> For an example of the designing style see:
> http://neil.franklin.ch/Projects/PDP-10/pdp10.vv.html

I never pass up a good URL.
Thanks.

######

From: ararghNOSPAM@NOT.AT.enteract.com
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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On Thu, 27 Feb 2003 08:50:15 -0500, Keith R. Williams
<krw@attglobal.net> wrote:

<snip>
>Most PCs could use 704K, though it wasn't advertised. As long as one 
>didn't have an EGA adapter the "A-segment" was available ("B" was the 
>CGA/MCA buffer).  It took some mucking with BIOS, but it wasn't hard.
>
>More than one code segment was pretty easy too.  Add "FAR" to the call 
>and proc statements. I'm not sure what the issue is with the stack 
>segment either.
If you only had a CGA card, memory address were available up to
segment B800.  At one time, I had an XT clone with usable addresses
of:
0000-B800, BC00-F400, + the HMA + extended memory.
But it took a while to get it all working.

The CGA card docs said it takes B800-C000, however the second half of
that range simply duplicates the first because of an incomplete
address decoding circuit.

Unfortunately, most VGA cards clobber all of A000-C800, even if you
use it only in mode 3(CGA compatible text mode).


-- 
Arargh (at arargh dot com)    http://www.arargh.com
To reply by email, change the domain name, and remove the garbage.
(Enteract can keep the spam, they are gone anyway)

######

From: Bernd Paysan <bernd.paysan@gmx.de>
Subject: Re: Antiquity of Byte-Word addressing?
Newsgroups: comp.arch,alt.folklore.computers
Followup-To: comp.arch
Date: Fri, 28 Feb 2003 11:29:34 +0100
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Xref: chonsp.franklin.ch alt.folklore.computers:130663

Neil Franklin wrote:

> bfranchuk@jetnet.ab.ca writes:
> 
>> Keith R. Williams wrote:
>>
>> > Use an FPGA.  Software is free for all but the largest (and expen$ive)
>> > parts.  You can get development boards for $100 or so.  TTL random
>> > logic has gone the way of the dodo.
>>
>> I have a FPGA, that is why I am going back to TTL the CPU just don't
>> fit in it - Altera 10K10.
> 
> 576 LEs. Seems to be an 24x24 grid, as far as the data sheet wants to
> tell. Small. Actually smallest in the series (576 to 12160 LEs).
> 
> Today 5000 LEs is considered the place to start for general purpose
> FPGA CPUs.

My b16 (http://www.jwdt.com/~paysan/b16.html) fits into ~700 LEs including 
external flash and SRAM access, and a 16 bit GPIO. Originally, I planned to 
use a 10K10, too, but it wasn't supported by the Quartus web edition, so I 
used a 10K30E. BTW: The Cyclones have a cheaper configuration device, and 
they start at ~3000LE.

-- 
Bernd Paysan
"If you want it done right, you have to do it yourself"
http://www.jwdt.com/~paysan/

######

From: Dave Daniels <dave_daniels@argonet.co.uk>
Subject: Re: Antiquity of Byte-Word addressing?
Newsgroups: alt.folklore.computers
Date: Fri, 28 Feb 2003 20:03:45 +0000 (GMT)
Message-ID: <4bcc00a91bdave_daniels@argonet.co.uk>
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Xref: chonsp.franklin.ch alt.folklore.computers:130716

In article <KRl7a.6116$EN3.48566@newsfep4-glfd.server.ntli.net>,
   Peter Dickerson <p.dickerson@ntlworld.com> wrote:
> I was under the impression that shifts are not free on ARM, in clock cycles
> at least. For example an added cycle on Xscale - Dennis is the expert on
> that, I guess, but maybe it is to close to home for hime to comment.

Register shifts by a fixed amount on non-Intel ARMs are free,
for example:

    ADD R1,R0,R0,LSL#2

executes in one clock cycle. If the shift amount is given by a
register then an extra cycle is required, for example:

    SUB R1,R0,R4,LSR R8

takes two cycles. I do not know how long the Xscale takes.

Dave Daniels

######

Path: chonsp.franklin.ch!not-for-mail
From: Neil Franklin <neil@franklin.ch.remove>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: 01 Mar 2003 17:45:56 +0100
Organization: My own Private Self
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Bernd Paysan <bernd.paysan@gmx.de> writes:

> Neil Franklin wrote:
>
> > bfranchuk@jetnet.ab.ca writes:
> >
> >> I have a FPGA, that is why I am going back to TTL the CPU just don't
> >> fit in it - Altera 10K10.
> >
> > 576 LEs. Seems to be an 24x24 grid, as far as the data sheet wants to
> > tell. Small. Actually smallest in the series (576 to 12160 LEs).
> >
> > Today 5000 LEs is considered the place to start for general purpose
> > FPGA CPUs.

Addendum: Small RISCy stuff can be done under 1000 LEs.


> My b16 (http://www.jwdt.com/~paysan/b16.html) fits into ~700 LEs including
> external flash and SRAM access, and a 16 bit GPIO.

A Forth processor. Definitely RISCy. More Ultra-RISCy actually :-).

Hmm, Forth, admirably compact (programs and their hardware demands),
looks like something that I really should like. Just somehow I never
managed to wrap my mind around it. And I like assembly and prefer RPN
calculators, so it doesn't seem to be the stack.


> use a 10K10, too, but it wasn't supported by the Quartus web edition, so I
> used a 10K30E. BTW: The Cyclones have a cheaper configuration device, and
> they start at ~3000LE.

Modern sizes.


> "If you want it done right, you have to do it yourself"

All too true, as soon as one belongs to the "only the right way is a
good way" elite.


> http://www.jwdt.com/~paysan/

Nice site.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith
- hardware runs the world, software controls the hardware
  code generates the software, have you coded today?

######

Path: chonsp.franklin.ch!not-for-mail
From: Neil Franklin <neil@franklin.ch.remove>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: 01 Mar 2003 17:59:01 +0100
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bfranchuk@jetnet.ab.ca writes:

> Neil Franklin wrote:
>
> > 576 LEs. Seems to be an 24x24 grid, as far as the data sheet wants to
> > tell. Small. Actually smallest in the series (576 to 12160 LEs).
>
> The le's is not the problem, routing is.

Hmm. I never had such problems. Is the 10K routing limited?

The docs I have here also suggest that. 144/8=18 horiontal and 24
vertical global lines per LE. The chip I am using has 12 local (do not
need to be shared over entire chip width), 3 distance and 3 global
lines horizontal and vertical per LC.


> Anyhow this TTL design
> uses 74LS670's dual port ram and that can't be emulated with this
> FPGA.

That requires the 10KE. Or an Xilinx chip (still their largest
advantage, them 16bit dual port SRAMs).


> > Today 5000 LEs is considered the place to start for general purpose
> > FPGA CPUs.
>
> Hardware bloat!

:-)


> > So that should give you about 10 times the space.
>
> Right now the config is about 16kb.Say 256kb for the
> bigger chips do to more routing tables and easy numbers

For the Xilinx chips I have docs handy for:

- for 16x24=384 LCs in XC2S15 256kbit = 32kByte config
- for 48x72=3456 LCs in XC2S150 1Mbit = 128kByte config
- for 96x144=13824 LCs in XC2S600E 4Mbit = 512kByte config


> to work  with. I plan to have 128k( 12 bits ) of memory
> on the base machine. Some how having the CPU with more
> memory than the computer don't feel right.

A 24bit system should fit an XC2S150. So that is 128k*8 FPGA vs
128k*12 memory. So 2:3.

OTOH my PDP10 in its small KA-10 version should also fit that and uses
9Mbit (256kword*36) SRAM. So 1:9.


> > "PROM": Standard flash ROM (or battery backed SRAM) and small uC (or
> > even Basic stamp?) to move the date flash->FPGA, for a few $. One does
> > not need to use the over-expensive low-volume special PARTS.
>
> I would use CPLD's rather than a FPGA since they power up
> pre-configured.

That is their advantage. But the price they pay is smaller
density. And they are only made in small sizes.


> porting from TLL to other logic is fairly easy.

Yes. Once the hard thinking work of design is done, you can easily
convert (= recode) to anything. Even to an transistor based own logic
family for ultimate do-it-yourself.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith
- hardware runs the world, software controls the hardware
  code generates the software, have you coded today?

######

From: bfranchuk@jetnet.ab.ca
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Sat, 01 Mar 2003 12:31:46 -0700
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Neil Franklin wrote:

> The docs I have here also suggest that. 144/8=18 horiontal and 24
> vertical global lines per LE. The chip I am using has 12 local (do not
> need to be shared over entire chip width), 3 distance and 3 global
> lines horizontal and vertical per LC.

It is the I/O pins that are the problem to route, as it seems to
route them first.

> That requires the 10KE. Or an Xilinx chip (still their largest
> advantage, them 16bit dual port SRAMs).

Anyhow I still need the motherboard/frontpanel and memory/io cards
built first. Since I plan to run about a 1 MHZ memory cycle using
a 6800/6809 style clock the cpu board could be almost any logic
but TUBE.

> Yes. Once the hard thinking work of design is done, you can easily
> convert (= recode) to anything. Even to an transistor based own logic
> family for ultimate do-it-yourself.

Or even do a chip as I am looking some of the open source
chip design packages. Assuming a 2ns gate delay I am guessing
I could run @50 ns. 52 pin chip ?
Ben.

PS. While this is not a Forth design as it is a general purpose CPU
Forth macros will run nicely on it.

######

From: Keith R. Williams <krw@attglobal.net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Sat, 1 Mar 2003 22:39:19 -0500
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Xref: chonsp.franklin.ch alt.folklore.computers:130855

In article <3E5E5400.7040708@jetnet.ab.ca>, 
bfranchuk@jetnet.ab.ca says...
> Keith R. Williams wrote:
> 
> > Use an FPGA.  Software is free for all but the largest (and expen$ive) 
> > parts.  You can get development boards for $100 or so.  TTL random 
> > logic has gone the way of the dodo.
> 
> I have a FPGA, that is why I am going back to TTL the CPU just don't
> fit in it - Altera 10K10. The main problem is getting a PROM burnt for
> the system. FPGA $5, PROM $50, PROM PROGRAMMER $500. Anybody want
> a FPGA protype system for a resonable price?

I've never used an ALtera chip, but the Xilinx stuff doesn't need 
any of that junk.  Get a download cable (the design is free), 
hook it to your printer port, and play.  You only need the PROM 
if you want to make it a product (systems and cables are larger 
than PROMs ;-).  

I'm reasonably sure Altera has a similar product.


> > No programmer needed with SRAM based FPGAs.  You can download the 
> > patterns or use flash.
> 
> You still need a uP to boot up the FPGA.

See above.  You can do it from a PC printer port.  Some boards 
allow configuration via PCI too.  

> > Hard wired logic has the disadvantage of being a PITA. ;-)
> 
> I find the development software a PITA that you have you spend
> $$ every year and/or get a license update every few months
> is a BIGGER PITA.

The software (at least the entry stuff) is free.  If you want to 
go for the professional packages it does get pricey.  The last 
FPGA I did we had something upwards of $80K in the the seat.  
It's certainly possible to do it free now.  
 
> Who knows if the program I am running will be supported in
> 5 years from now. If I want to build  a new TTL computer I just
> lay out a new PCB and take the chips out of the old boards.

Yuck.  What a dreadful waste of time.  BTDT, have the scars.
 
> As a side note what little I have seen of VHDL and VERLOG
> I don't like, as well I have not figured how write hardware
> discriptions in it at all. I have not seen any RTL software
> for FPGA's. Note do to a limited budget I tend to use free
> software.

I'm not a verilog lover, but I quite like VHDL.  I guess it's a 
preference.  I like PL/I too (can't spell 'C'). 

You simply haven't looked. FPGA software is free for the 
download.  It may not be quite as good as the expen$ive spread, 
but it works.  The high end packages are better at inferring 
logic from HDLs than the free stuff.  Though if you're using SSI 
TTL you don't need any of that fancy inferrin', you're going to 
get rite down there and instantiate anyway, like a *real_man*.
  
> I want to be hardware independant and open source with my
> computer as /BAH is with living.

You're simply wasting precious time on this earth.  If that's 
you, go for it.  Shrug!

-- 
  Keith

######

From: Keith R. Williams <krw@attglobal.net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Sat, 1 Mar 2003 22:48:29 -0500
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Xref: chonsp.franklin.ch alt.folklore.computers:130856

In article <3E5E9ECB.7060700@jetnet.ab.ca>, 
bfranchuk@jetnet.ab.ca says...
> Neil Franklin wrote:
> 
> > 576 LEs. Seems to be an 24x24 grid, as far as the data sheet wants to
> > tell. Small. Actually smallest in the series (576 to 12160 LEs).
> 
> The le's is not the problem, routing is. Anyhow this TTL design
> uses 74LS670's dual port ram and that can't be emulated with this
> FPGA.

You're living in the stone age.  The modern FPGAs have tremendous 
routing resources.  Take a look at the Xilinx Virtex line.  There 
is routing resource up the ying-yang.  The later ones are rather 
inexpensive too.
> 
> > Today 5000 LEs is considered the place to start for general purpose
> > FPGA CPUs.
> 
> Hardware bloat!

Oh please.  You sound like one cantankerous old fart. ;-)

> > So that should give you about 10 times the space.
> 
> Right now the config is about 16kb.Say 256kb for the
> bigger chips do to more routing tables and easy numbers
> to work  with. I plan to have 128k( 12 bits ) of memory
> on the base machine. Some how having the CPU with more
> memory than the computer don't feel right.
> 
> > "PROM": Standard flash ROM (or battery backed SRAM) and small uC (or
> > even Basic stamp?) to move the date flash->FPGA, for a few $. One does
> > not need to use the over-expensive low-volume special PARTS.
> 
> I would use CPLD's rather than a FPGA since they power up
> pre-configured.

What a horrid idea.  You sacrifice density/complexity for silly 
configuration.  DOwnload the design from your printer port.  
Flash/EPROM programmable logic devices simply suck bilge water.

> > 150 TTLs and their power supply will cost more (money and space). And
> > be slower.
> 
> I am guessing at 5 amps for the power used so a
> old AT power supply would be fine. Since this design is
> "classic" computer design from about 1980 I don't plan to run
> faster than 1 MHZ. I will use static ram and flash to emulate
> good old core memory or dynamic ram/EEPROM.

Put the whole bloody thing in one FPGA and play to your hearts 
content.  But, since you want to use your pretty new wire-wrap 
tool, go fer it. 

> > Under Wine and Linux that should not be a problem.
> Sure and I need win/2010 to flush my toilet too.
> 
> If this was a commercial design, I would be using
> state of the art tools and logic devices. Still
> porting from TLL to other logic is fairly easy.
> I am guessing I have about 32 levels of gate delay
> so @ 3 ns per logic gate that is about 100 ns.
> LS TTL looks to run at about 1000 ns.

3ns?  You're an optimistic SOB, aren't you!  You're forgetting 
capacitance and distance, perhaps?  Yikes!
 
Stick with FPGAs.  Random logic is dead.  Long may it rest.

-- 
  Keith

######

From: bfranchuk@jetnet.ab.ca
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Sat, 01 Mar 2003 21:43:52 -0700
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Keith R. Williams wrote:

> You're living in the stone age.  The modern FPGAs have tremendous 
> routing resources.  Take a look at the Xilinx Virtex line.  There 
> is routing resource up the ying-yang.  The later ones are rather 
> inexpensive too.

Bigger is NOT allways better.

> 
> Oh please.  You sound like one cantankerous old fart. ;-)

If I wanted use a FPGA would use the one I have here.

> What a horrid idea.  You sacrifice density/complexity for silly 
> configuration.  DOwnload the design from your printer port.  
> Flash/EPROM programmable logic devices simply suck bilge water.

So what, you are NOT building it, I am!

> Put the whole bloody thing in one FPGA and play to your hearts 
> content.  But, since you want to use your pretty new wire-wrap 
> tool, go fer it. 

Well I can't wire wrap so getting some PCB boards made up.
Also all the NEW FPGA's are in stupid packages that a home-brewer can 
never use.

> 3ns?  You're an optimistic SOB, aren't you!  You're forgetting 
> capacitance and distance, perhaps?  Yikes!

This is a SMALL computer for TODAY. Regardless of what  technology
I use to impliment it, the levels of gating are about the same.

> Stick with FPGAs.  Random logic is dead.  Long may it rest.

I'll stick with schematics on quad paper. No amount of software
can replace a good brain! Ben.

######

Date: Sun, 2 Mar 2003 08:49:23 +0100
From: Steve O'Hara-Smith <steveo@eircom.net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Message-ID: <20030302084923.2189f69f.steveo@eircom.net>
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	<8737@myrtle.ukc.ac.uk>
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	<3E5D042A.30801@jetnet.ab.ca>
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	<3E5D4015.3000902@jetnet.ab.ca>
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	<3E5E5400.7040708@jetnet.ab.ca>
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Xref: chonsp.franklin.ch alt.folklore.computers:130835

On Sat, 1 Mar 2003 22:48:29 -0500
Keith R. Williams <krw@attglobal.net> wrote:

KRW> In article <3E5E9ECB.7060700@jetnet.ab.ca>, 
KRW> bfranchuk@jetnet.ab.ca says...
 
KRW> > Hardware bloat!
KRW> 
KRW> Oh please.  You sound like one cantankerous old fart. ;-)

	This is auld.farts.computing after all :)

	Anyway one big disadvantage of an FPGA is that you can't
point to the boards and identify the bits of the CPU, nor can you
sprinkle LEDs around like confetti for a good set of blinkenlights.

KRW> Stick with FPGAs.  Random logic is dead.  Long may it rest.

	Sailing ships are dead - but people still make yachts.

-- 
C:>WIN                                      |     Directable Mirrors
The computer obeys and wins.                |A Better Way To Focus The Sun
You lose and Bill collects.                 |  licenses available - see:
                                            |   http://www.sohara.org/

######

Path: chonsp.franklin.ch!not-for-mail
From: Neil Franklin <neil@franklin.ch.remove>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: 02 Mar 2003 20:27:27 +0100
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Steve O'Hara-Smith <steveo@eircom.net> writes:

> Keith R. Williams <krw@attglobal.net> wrote:
>
> KRW> bfranchuk@jetnet.ab.ca says...
>
> KRW> > Hardware bloat!
> KRW>
> KRW> Oh please.  You sound like one cantankerous old fart. ;-)
>
>       This is auld.farts.computing after all :)

Yes. Here makes me feel young.


>       Anyway one big disadvantage of an FPGA is that you can't
> point to the boards and identify the bits of the CPU,

That is what you have an plot of the FPGA contents for.

Not quite as touchy-physical, but it is not bad either.


> nor can you
> sprinkle LEDs around like confetti for a good set of blinkenlights.

Sure you can. You just make an LED matrix (copy your favourite front
pannel design) and connect it to FPGA IO pins. Then put in the FPGA an
multiplexer that scans the interesting data points.

You could even display your FPGAs internals onto an video monitor.


> KRW> Stick with FPGAs.  Random logic is dead.  Long may it rest.
>
>       Sailing ships are dead - but people still make yachts.

Yes. Fun does not need to be efficient.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith
- hardware runs the world, software controls the hardware
  code generates the software, have you coded today?

######

From: Keith R. Williams <krw@attglobal.net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Sun, 2 Mar 2003 19:25:44 -0500
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Xref: chonsp.franklin.ch alt.folklore.computers:130907

In article <3E618C08.8050203@jetnet.ab.ca>, 
bfranchuk@jetnet.ab.ca says...
> Keith R. Williams wrote:
> 
> > You're living in the stone age.  The modern FPGAs have tremendous 
> > routing resources.  Take a look at the Xilinx Virtex line.  There 
> > is routing resource up the ying-yang.  The later ones are rather 
> > inexpensive too.
> 
> Bigger is NOT allways better.
> 
> > 
> > Oh please.  You sound like one cantankerous old fart. ;-)
> 
> If I wanted use a FPGA would use the one I have here.

You pointed out that you couldn't use PALs/GALs because you 
haven't a programmer and argued against FPGAs for similar (and 
erroneous) reasons.  The obvious tool is an FPGA.  But if you're 
determined to make a model-T from iron ore, go for it.  I'd go 
another way, though a model-T certainly isn't an uninteresting 
goal.

> > What a horrid idea.  You sacrifice density/complexity for silly 
> > configuration.  DOwnload the design from your printer port.  
> > Flash/EPROM programmable logic devices simply suck bilge water.
> 
> So what, you are NOT building it, I am!

Go fer it!  Why ask for help/advice if you've already made up 
your mind?  Just do it.
 
> > Put the whole bloody thing in one FPGA and play to your hearts 
> > content.  But, since you want to use your pretty new wire-wrap 
> > tool, go fer it. 
> 
> Well I can't wire wrap so getting some PCB boards made up.

That was in deference to Del.  ;-)  ...but PCBs are expensive for 
toyz.  Even programmers are cheap, by comparison. It's your money 
though. Shrug.

> Also all the NEW FPGA's are in stupid packages that a home-brewer can 
> never use.

...and you're having custom PCBs made?  Wow, color me confused!  
You can get *standard* PCBs with a variety of FPGAs already 
mounted.  You're not making a product, I presume.  ;-)
> 
> > 3ns?  You're an optimistic SOB, aren't you!  You're forgetting 
> > capacitance and distance, perhaps?  Yikes!
> 
> This is a SMALL computer for TODAY. Regardless of what  technology
> I use to impliment it, the levels of gating are about the same.

3ns per gate in SSI is a very optimistic number.  I don't care 
what the size of the project. The levels of gating are never the 
same.  Programmable logic can drop the number of levels 
significantly.  Again, you asked, I answered.  Have fun.  

> > Stick with FPGAs.  Random logic is dead.  Long may it rest.
> 
> I'll stick with schematics on quad paper. No amount of software
> can replace a good brain! Ben.

Good software (as oxymoronic as it sounds) can replace hours upon 
hours of manual labor.  Have you considered the productivity 
gains of CPU designers in the past thirty years?  It's obvious 
your time isn't money, but what do you do when (if) you get the 
thing working?  Start over?  Programmable logic...

-- 
  Keith

######

From: Keith R. Williams <krw@attglobal.net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Sun, 2 Mar 2003 19:30:15 -0500
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Xref: chonsp.franklin.ch alt.folklore.computers:130905

In article <20030302084923.2189f69f.steveo@eircom.net>, 
steveo@eircom.net says...
> On Sat, 1 Mar 2003 22:48:29 -0500
> Keith R. Williams <krw@attglobal.net> wrote:
> 
> KRW> In article <3E5E9ECB.7060700@jetnet.ab.ca>, 
> KRW> bfranchuk@jetnet.ab.ca says...
>  
> KRW> > Hardware bloat!
> KRW> 
> KRW> Oh please.  You sound like one cantankerous old fart. ;-)
> 
> 	This is auld.farts.computing after all :)

Well, this cantankerous old fart is posting from comp.arch and 
didn't notice the cross-post from a.f.c.  ;-)

> 	Anyway one big disadvantage of an FPGA is that you can't
> point to the boards and identify the bits of the CPU, nor can you
> sprinkle LEDs around like confetti for a good set of blinkenlights.

Huh?  You can certainly put any level of blinkin' lights on an 
FPGA board as will impress management.  You can even redefine the 
blinkin' meaning of the blinkin' lights.  I wish I had FPGAs 
thirty years ago!
 
> KRW> Stick with FPGAs.  Random logic is dead.  Long may it rest.
> 
> 	Sailing ships are dead - but people still make yachts.

Yachts have a purpose.  A few boards of junk TTL isn't going to 
impress many young things in thongs. ;-)

-- 
  Keith

######

From: bfranchuk@jetnet.ab.ca
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Sun, 02 Mar 2003 18:45:12 -0700
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Xref: chonsp.franklin.ch alt.folklore.computers:130883

Keith R. Williams wrote:

> 
> You pointed out that you couldn't use PALs/GALs because you 
> haven't a programmer and argued against FPGAs for similar (and 
> erroneous) reasons.  The obvious tool is an FPGA.  But if you're 
> determined to make a model-T from iron ore, go for it.  I'd go 
> another way, though a model-T certainly isn't an uninteresting 
> goal.
> 
I'd take a old Rolls Royce instead.

> Go fer it!  Why ask for help/advice if you've already made up 
> your mind?  Just do it.
> 

I did not ask for help.

> That was in deference to Del.  ;-)  ...but PCBs are expensive for 
> toyz.  Even programmers are cheap, by comparison. It's your money 
> though. Shrug.

CAD has made proto-type PCB's resonable. I can't think of any hobby
that does not take a good amount of money. While tools can make up
for skill ,good tools are needed in any hobby.

> You can get *standard* PCBs with a variety of FPGAs already 
> mounted.  You're not making a product, I presume.  ;-)


Nope as who nowdays would pay $1200 Can for a .92 MHZ Machine.
Right now I am guessing at about $400 per board to build not
counting my time. Memory and I/O not included, but then how much
did the first computer kits run at cost wise. I also plan to
build this over several years. The TTL I can get first once I
finish the design.

> 
> Good software (as oxymoronic as it sounds) can replace hours upon 
> hours of manual labor.  Have you considered the productivity 
> gains of CPU designers in the past thirty years?  It's obvious 
> your time isn't money, but what do you do when (if) you get the 
> thing working?  Start over?  Programmable logic...

I don't mind using software, but I don't want to be tied down
to a system that may not be there a few years from now. That reminds
me I still need to work on software. Notice how hard it is
to bootstap nowdays as all the compiled languges with source require
mega-ram and mega-disk space.

Anyway I have done a FPGA cpu.
Ben.

######

From: bfranchuk@jetnet.ab.ca
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Sun, 02 Mar 2003 19:11:28 -0700
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Keith R. Williams wrote:
> 
> Yachts have a purpose.  A few boards of junk TTL isn't going to 
> impress many young things in thongs. ;-)

	That was not the design goal. I have a clean instruction set
given the hardware constraints and hopefully a clean logic design.
Non RISC too! :)

	Finding young things in thongs is rather hard
the winter regardless what you use as bait. I guess I'll
have to watch Japanese Anime for the sport of girl watching for
now.:D
Ben.

######

X-Trace-PostClient-IP: 68.147.131.211
From: Brian Inglis <Brian.Inglis@SystematicSw.ab.ca>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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On Sun, 02 Mar 2003 18:45:12 -0700 in alt.folklore.computers,
bfranchuk@jetnet.ab.ca wrote:

>That reminds
>me I still need to work on software. Notice how hard it is
>to bootstrap nowdays as all the compiled languages with source require
>mega-ram and mega-disk space.

IIRC Small-C is still available on CD from DDJ web site: not sure
how much it's tied to bytes. PCC Portable C Compiler is probably
downloadable and may be easier to get running on a different
architecture. 

Thanks. Take care, Brian Inglis 	Calgary, Alberta, Canada
-- 
Brian.Inglis@CSi.com 	(Brian dot Inglis at SystematicSw dot ab dot ca)
    fake address		use address above to reply
abuse@aol.com tosspam@aol.com abuse@att.com abuse@earthlink.com 
abuse@hotmail.com abuse@mci.com abuse@msn.com abuse@sprint.com 
abuse@yahoo.com abuse@cadvision.com abuse@shaw.ca abuse@telus.com 
abuse@ibsystems.com uce@ftc.gov				spam traps

######

From: Peter da Silva <peter@abbnm.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Sun, 02 Mar 2003 22:02:01 -0600
Organization: ABB Inc., Network Management Division
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Brian Inglis wrote:
> On Sun, 02 Mar 2003 18:45:12 -0700 in alt.folklore.computers,
> bfranchuk@jetnet.ab.ca wrote:
>>That reminds
>>me I still need to work on software. Notice how hard it is
>>to bootstrap nowdays as all the compiled languages with source require
>>mega-ram and mega-disk space.

> IIRC Small-C is still available on CD from DDJ web site: not sure
> how much it's tied to bytes. PCC Portable C Compiler is probably
> downloadable and may be easier to get running on a different
> architecture. 

Small C is kinda lousy at code generation. Might be better to
start with FIG-Forth... even interpreted, it can be pretty peppy.

-- 
`-_-'   Ar rug tú barróg ar do mhactíre inniu?
 'U`    Peter da Silva

######

From: "Andy Glew" <andy_glew_public@yahoo.com>
Newsgroups: comp.arch,alt.folklore.computers
References: <5tC5a.1106$TR4.120765@newsread1.prod.itd.earthlink.net> <3E5828B5.E261C23E@earthlink.net> <Qfa6a.2570$cD5.246128@newsread2.prod.itd.earthlink.net> <8723@myrtle.ukc.ac.uk> <3E5ACC81.84A4C51A@earthlink.net> <zjD6a.254166$vm2.197763@rwcrnsc54> <3E5B031A.8070605@jetnet.ab.ca> <1046186601.917677@haldjas.folklore.ee> <wccsmuce4ex.fsf@shell01.TheWorld.com> <s71heasz314.fsf@beech.CS.Berkeley.EDU> <wcc4r6sw3p3.fsf@shell01.TheWorld.com>
Subject: Re: Antiquity of Byte-Word addressing?
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> > > Another question:  Why have bit-addressable machines never caught on?
> > > It would save a lot of shifting and masking if I could load, say, any
> > > power-of-2 sized bitfield into a register.
> > David Gay

It might save the user shifting and masking.

The hardware would just end up doing it,
implicitly, on each memory reference.

######

Date: Mon, 3 Mar 2003 07:48:07 +0100
From: Steve O'Hara-Smith <steveo@eircom.net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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Xref: chonsp.franklin.ch alt.folklore.computers:130949

On Sun, 2 Mar 2003 19:30:15 -0500
Keith R. Williams <krw@attglobal.net> wrote:

KRW> > 	Anyway one big disadvantage of an FPGA is that you can't
KRW> > point to the boards and identify the bits of the CPU, nor can you
KRW> > sprinkle LEDs around like confetti for a good set of blinkenlights.
KRW> 
KRW> Huh?  You can certainly put any level of blinkin' lights on an 
KRW> FPGA board as will impress management.  You can even redefine the 

	That's a virtual blinkenlights - they are not hooked up to
the bits they display.

-- 
C:>WIN                                      |     Directable Mirrors
The computer obeys and wins.                |A Better Way To Focus The Sun
You lose and Bill collects.                 |  licenses available - see:
                                            |   http://www.sohara.org/

######

From: lars@bearnip.com (Lars Duening)
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Mon, 3 Mar 2003 08:52:21 -0700
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Brian Inglis <Brian.Inglis@SystematicSw.ab.ca> wrote:

> On Sun, 02 Mar 2003 18:45:12 -0700 in alt.folklore.computers,
> bfranchuk@jetnet.ab.ca wrote:
> 
> >That reminds
> >me I still need to work on software. Notice how hard it is
> >to bootstrap nowdays as all the compiled languages with source require
> >mega-ram and mega-disk space.
> 
> IIRC Small-C is still available on CD from DDJ web site: not sure
> how much it's tied to bytes. PCC Portable C Compiler is probably
> downloadable and may be easier to get running on a different
> architecture. 

And there's also lcc.

######

From: Keith R. Williams <krw@attglobal.net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Mon, 3 Mar 2003 13:06:38 -0500
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In article <20030303074807.48e28cc7.steveo@eircom.net>, 
steveo@eircom.net says...
> On Sun, 2 Mar 2003 19:30:15 -0500
> Keith R. Williams <krw@attglobal.net> wrote:
> 
> KRW> > 	Anyway one big disadvantage of an FPGA is that you can't
> KRW> > point to the boards and identify the bits of the CPU, nor can you
> KRW> > sprinkle LEDs around like confetti for a good set of blinkenlights.
> KRW> 
> KRW> Huh?  You can certainly put any level of blinkin' lights on an 
> KRW> FPGA board as will impress management.  You can even redefine the 
> 
> 	That's a virtual blinkenlights - they are not hooked up to
> the bits they display.

They can be anything from virtual to real blinkenlights.  They can be  
from meaningful to less, from dull red to pretty colors.  Add in an LCD 
display and one can really impress. ...or any combination of the above. 
That's the beauty of programmable logic.

-- 
  Keith

######

Date: Mon, 3 Mar 2003 19:59:58 +0100
From: Steve O'Hara-Smith <steveo@eircom.net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Message-ID: <20030303195958.7da9f72d.steveo@eircom.net>
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Xref: chonsp.franklin.ch alt.folklore.computers:130952

On Mon, 3 Mar 2003 13:06:38 -0500
Keith R. Williams <krw@attglobal.net> wrote:

KRW> In article <20030303074807.48e28cc7.steveo@eircom.net>, 
KRW> steveo@eircom.net says...
 
KRW> > 	That's a virtual blinkenlights - they are not hooked up to
KRW> > the bits they display.
KRW> 
KRW> They can be anything from virtual to real blinkenlights.  They can be

	They are virtual if the light labeled A0 isn't hardwired to
bit 0 of the address bus.

KRW> from meaningful to less, from dull red to pretty colors.  Add in an
KRW> LCD display and one can really impress. ...or any combination of the
KRW> above. That's the beauty of programmable logic.

	Yes, that's what makes them virtual. There is no fixed physical
connection between the wire carrying the bit and the light puporting
to show the state of the bit.

-- 
C:>WIN                                      |     Directable Mirrors
The computer obeys and wins.                |A Better Way To Focus The Sun
You lose and Bill collects.                 |  licenses available - see:
                                            |   http://www.sohara.org/

######

From: Keith R. Williams <krw@attglobal.net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Mon, 3 Mar 2003 16:11:42 -0500
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In article <20030303195958.7da9f72d.steveo@eircom.net>, 
steveo@eircom.net says...
> On Mon, 3 Mar 2003 13:06:38 -0500
> Keith R. Williams <krw@attglobal.net> wrote:
> 
> KRW> In article <20030303074807.48e28cc7.steveo@eircom.net>, 
> KRW> steveo@eircom.net says...
>  
> KRW> > 	That's a virtual blinkenlights - they are not hooked up to
> KRW> > the bits they display.
> KRW> 
> KRW> They can be anything from virtual to real blinkenlights.  They can be
> 
> 	They are virtual if the light labeled A0 isn't hardwired to
> bit 0 of the address bus.

Why do you assume they aren't?  It's my design and I can wire them any 
way I wish. ;-)

> KRW> from meaningful to less, from dull red to pretty colors.  Add in an
> KRW> LCD display and one can really impress. ...or any combination of the
> KRW> above. That's the beauty of programmable logic.
> 
> 	Yes, that's what makes them virtual. There is no fixed physical
> connection between the wire carrying the bit and the light puporting
> to show the state of the bit.

Unless your meaning of "real" is to load the A0 driver directly with 
the LED (not a good idea in any logic family/design) that is not 
necessarily true.  That is, if you put a wire, LED driver, or even 
limiting resistor inbetween A0 and the LED that somehow makes it 
"virtual".  That definition of "virtual" is too restrictive for me.  
Kinda makes virtual == useless. 

For my meaning of "real" (LED light reflects logic value; we can 
discuss human perception here too) one can wire address_bus[0] out to 
light labeled A0 or wire it through encoders to another type of 
display. The designer can choose the level of abstraction, none, or any 
combination at compile/synthesis time.  There are no constraints placed 
on the designer by programmable logic that forces blinkenlights be 
"virtual". Other than total I/O, rather the opposite is true.

I've done FPGAs with the equivalent of wiring A0 to an LED labeled A0 
(address decode/register select directly to an LED).  I've also 
reassigned that LED to something more interesting when that got boring 
(I.e. working).  I've muxed several functions to the same LED 
controlled by an addressable register. One of the more challenging 
things was to wire the LED "on" (the blasted FPGA wouldn't configure - 
mostly operator error ;-).  That day, LED_on == beer_time!

-- 
  Keith


-- 
  Keith

######

From: jmfbahciv@aol.com
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Tue, 04 Mar 03 10:00:48 GMT
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In article <MPG.18cd639fa4c3b8b598991e@enews.newsguy.com>,
   Keith R. Williams <krw@attglobal.net> wrote:
>In article <20030303074807.48e28cc7.steveo@eircom.net>, 
>steveo@eircom.net says...
>> On Sun, 2 Mar 2003 19:30:15 -0500
>> Keith R. Williams <krw@attglobal.net> wrote:
>> 
>> KRW> > 	Anyway one big disadvantage of an FPGA is that you can't
>> KRW> > point to the boards and identify the bits of the CPU, nor can you
>> KRW> > sprinkle LEDs around like confetti for a good set of 
blinkenlights.
>> KRW> 
>> KRW> Huh?  You can certainly put any level of blinkin' lights on an 
>> KRW> FPGA board as will impress management.  You can even redefine the 
>> 
>> 	That's a virtual blinkenlights - they are not hooked up to
>> the bits they display.
>
>They can be anything from virtual to real blinkenlights.  They can be  
>from meaningful to less, from dull red to pretty colors.  Add in an LCD 
>display and one can really impress. ...or any combination of the above. 
>That's the beauty of programmable logic.

If the lights don't tell you what is going on, then they're not
blinkenlights.

/BAH

Subtract a hundred and four for e-mail.

######

From: jmfbahciv@aol.com
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Wed, 05 Mar 03 12:35:30 GMT
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In article <qhznoau12g.fsf@ruckus.brouhaha.com>,
   Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote:
>haynes@alumni.uark.edu (Jim Haynes) writes:
>> I'm under the impression that, with the notable exception of the 7030
>> STRETCH,
>
>The Stretch didn't really have byte addressing per se.  The computational
>unit for integer and logical operators was a byte of 1 to 8 bits, but
>the addressing was to an arbitrary bit boundary with no alignment
>restrictions.  For instance, you could use 8-bit bytes starting at bit 3
>of a word.
>
>Instructions were 32-bit aligned, and floating-point operands were
>64-bit aligned.
>
>> IBM S/360 was the first line of machines to address memory by
>> the byte, but to also have a word (and halfword and double word) 
>> structure.  Was there anything earlier?
>
>The DEC PDP-6 had byte addressing for some instructions, and was first
>shipped to customers in 1964, so it predates the IBM System/360 which
>was announced in 1964 but not shipped until 1965.  The PDP-6 allowed for
>any byte size from zero to thirty-sx bits, starting on any bit of a word,
>but unlike Stretch it did not allow a single byte to cross a word 
>boundary.

But the -6 didn't cross word boundaries...did it? IOW, if I had 
a byte pointer 8 bits wide but pointing at bit 34, it wouldn't
pick up bits 34, 35, and concantentate it with bits 0, 1, 2, 3,
4 and 5 of the next word.

/BAH


/BAH

Subtract a hundred and four for e-mail.

######

Date: Tue, 4 Mar 2003 07:08:10 +0100
From: Steve O'Hara-Smith <steveo@eircom.net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Message-ID: <20030304070810.6e899b5c.steveo@eircom.net>
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	<20030303195958.7da9f72d.steveo@eircom.net>
	<MPG.18cd7c0da923110c98991f@enews.newsguy.com>
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On Mon, 3 Mar 2003 16:11:42 -0500
Keith R. Williams <krw@attglobal.net> wrote:

KRW> In article <20030303195958.7da9f72d.steveo@eircom.net>, 
KRW> steveo@eircom.net says...
KRW> > On Mon, 3 Mar 2003 13:06:38 -0500

KRW> > 	Yes, that's what makes them virtual. There is no fixed physical
KRW> > connection between the wire carrying the bit and the light
KRW> > puporting to show the state of the bit.
KRW> 
KRW> Unless your meaning of "real" is to load the A0 driver directly with 
KRW> the LED (not a good idea in any logic family/design) that is not 
KRW> necessarily true.  That is, if you put a wire, LED driver, or even 
KRW> limiting resistor inbetween A0 and the LED that somehow makes it 

	No that's real enough - but as soon as there is logic between
the signal and the light such that the light might not reflect the signal
I'll consider it virtual.

KRW> I've done FPGAs with the equivalent of wiring A0 to an LED labeled A0

	I guess that would satisfy my criteria for reality of a
blinkenlight.

KRW> (address decode/register select directly to an LED).  I've also 
KRW> reassigned that LED to something more interesting when that got

	That wouldn't.

KRW> boring (I.e. working).  I've muxed several functions to the same LED 
KRW> controlled by an addressable register. One of the more challenging 

	Definitely not that.

-- 
C:>WIN                                      |     Directable Mirrors
The computer obeys and wins.                |A Better Way To Focus The Sun
You lose and Bill collects.                 |  licenses available - see:
                                            |   http://www.sohara.org/

######

From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Newsgroups: comp.arch,alt.folklore.computers
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"Jim Haynes" <haynes@alumni.uark.edu> wrote in message
news:5tC5a.1106$TR4.120765@newsread1.prod.itd.earthlink.net...
> I'm under the impression that, with the notable exception of the 7030
> STRETCH, IBM S/360 was the first line of machines to address memory by
> the byte, but to also have a word (and halfword and double word)
> structure.  Was there anything earlier?


I just noticed that the 701 was halfword (36 bit word) addressable.

It would seem to me that this does NOT qualify as a byte addressable
machine.  Characters were 6 bits, and, even so, the ability to address a
halfword doesn't seem quite so significant as the ability to address
quarterwords.

-- glen

######

Sender: eric@ruckus.brouhaha.com
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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haynes@alumni.uark.edu (Jim Haynes) writes:
> I'm under the impression that, with the notable exception of the 7030
> STRETCH,

The Stretch didn't really have byte addressing per se.  The computational
unit for integer and logical operators was a byte of 1 to 8 bits, but
the addressing was to an arbitrary bit boundary with no alignment
restrictions.  For instance, you could use 8-bit bytes starting at bit 3
of a word.

Instructions were 32-bit aligned, and floating-point operands were
64-bit aligned.

> IBM S/360 was the first line of machines to address memory by
> the byte, but to also have a word (and halfword and double word) 
> structure.  Was there anything earlier?

The DEC PDP-6 had byte addressing for some instructions, and was first
shipped to customers in 1964, so it predates the IBM System/360 which
was announced in 1964 but not shipped until 1965.  The PDP-6 allowed for
any byte size from zero to thirty-sx bits, starting on any bit of a word,
but unlike Stretch it did not allow a single byte to cross a word boundary.

######

From: "Rupert Pigott" <roo@dark-try-removing-this-boong.demon.co.uk>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Wed, 5 Mar 2003 00:15:10 -0000
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"Eric Smith" <eric-no-spam-for-me@brouhaha.com> wrote in message
news:qhznoau12g.fsf@ruckus.brouhaha.com...
> haynes@alumni.uark.edu (Jim Haynes) writes:
> > I'm under the impression that, with the notable exception of the 7030
> > STRETCH,
>
> The Stretch didn't really have byte addressing per se.  The computational
> unit for integer and logical operators was a byte of 1 to 8 bits, but
> the addressing was to an arbitrary bit boundary with no alignment
> restrictions.  For instance, you could use 8-bit bytes starting at bit 3
> of a word.

They didn't aim low with STRETCH, that's for sure.

The more I learn about IBM the more I wonder if there
is anything they haven't done...

Cheers,
Rupert

######

Sender: eric@ruckus.brouhaha.com
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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Steve O'Hara-Smith <steveo@eircom.net> writes:
> 	Yes, that's what makes them virtual. There is no fixed physical
> connection between the wire carrying the bit and the light puporting
> to show the state of the bit.

Do you consider the front panel of a PDP-9 or PDP-11/05 to be "virtual"?
They don't have a fixed physical connection between the flops and the
lights that display their state, instead scanning the bits out serially.
This was at one time a common technique used to reduce the wiring
requirements between the CPU logic and the front panel.

######

From: "del cecchi" <dcecchi@msn.com>
Newsgroups: comp.arch,alt.folklore.computers
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"Rupert Pigott" <roo@dark-try-removing-this-boong.demon.co.uk> wrote in
message news:1046823310.439241@saucer.planet.gong...
> "Eric Smith" <eric-no-spam-for-me@brouhaha.com> wrote in message
> news:qhznoau12g.fsf@ruckus.brouhaha.com...
> > haynes@alumni.uark.edu (Jim Haynes) writes:
> > > I'm under the impression that, with the notable exception of the
7030
> > > STRETCH,
> >
> > The Stretch didn't really have byte addressing per se.  The
computational
> > unit for integer and logical operators was a byte of 1 to 8 bits,
but
> > the addressing was to an arbitrary bit boundary with no alignment
> > restrictions.  For instance, you could use 8-bit bytes starting at
bit 3
> > of a word.
>
> They didn't aim low with STRETCH, that's for sure.
>
> The more I learn about IBM the more I wonder if there
> is anything they haven't done...
>
> Cheers,
> Rupert
>
There are several things that they haven't done, however not for lack of
trying.  :-)

del

######

Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Reply-To: Anne & Lynn Wheeler <lynn@garlic.com>
From: Anne & Lynn Wheeler <lynn@garlic.com>
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"Rupert Pigott" <roo@dark-try-removing-this-boong.demon.co.uk> writes:
> The more I learn about IBM the more I wonder if there
> is anything they haven't done...

there is the story about executive that had project in LA ...  i think
done in association with the (ibm) la science center and one of the
university medical schools for blood dialysis machine .... and was
involved in deciding whether to put a heater for the blood while it
was out of the body and decided not to. some 25(?) years later when he
was hooked up to one of his machines ... he was reported to have made
some comment that cold blood was painful and not having a heater was
possibly one of the worst decisions he had made.

-- 
Anne & Lynn Wheeler | http://www.garlic.com/~lynn/ 
Internet trivia 20th anv http://www.garlic.com/~lynn/rfcietff.htm

######

Date: Wed, 5 Mar 2003 06:34:42 +0100
From: Steve O'Hara-Smith <steveo@eircom.net>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Message-ID: <20030305063442.29279931.steveo@eircom.net>
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Xref: chonsp.franklin.ch alt.folklore.computers:131049

On 04 Mar 2003 16:22:43 -0800
Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote:

ES> Steve O'Hara-Smith <steveo@eircom.net> writes:
ES> > 	Yes, that's what makes them virtual. There is no fixed physical
ES> > connection between the wire carrying the bit and the light puporting
ES> > to show the state of the bit.
ES> 
ES> Do you consider the front panel of a PDP-9 or PDP-11/05 to be
ES> "virtual"? They don't have a fixed physical connection between the
ES> flops and the lights that display their state, instead scanning the

	Can you make a light show anything other than the state of the
bit in question (without changing the hardware) ? If yes then it's virtual
for sure, if not then I'd consider this an implementation detail :)

-- 
C:>WIN                                      |     Directable Mirrors
The computer obeys and wins.                |A Better Way To Focus The Sun
You lose and Bill collects.                 |  licenses available - see:
                                            |   http://www.sohara.org/

######

Sender: eric@ruckus.brouhaha.com
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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Xref: chonsp.franklin.ch alt.folklore.computers:131076

haynes@alumni.uark.edu (Jim Haynes) writes:
> IBM 7030 (STRETCH) was addressable to the bit level - but then it was a
> research project.

Actually, it wasn't a research product.  It was a development project
with the intent of pushing the state of the art but delivering specific
products.  (Though the products did change during development, but that's
not all that uncommon.)

> I believe STRETCH was the first IBM machine to have powers-of-2 data sizes.
> Someone asked why 8-bit bytes;

The Stretch hardware supported byte sizes from one to eight bits.

######

From: jmfbahciv@aol.com
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Thu, 06 Mar 03 10:24:27 GMT
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Xref: chonsp.franklin.ch alt.folklore.computers:131146

In article <LFw9a.372154$be.342715@rwcrnsc53>,
   "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote:
>
><jmfbahciv@aol.com> wrote in message news:b44ti9$e2g$1@bob.news.rcn.net...
>> In article <qhznoau12g.fsf@ruckus.brouhaha.com>,
>(snip)
>> >
>> >The DEC PDP-6 had byte addressing for some instructions, and was first
>> >shipped to customers in 1964, so it predates the IBM System/360 which
>> >was announced in 1964 but not shipped until 1965.  The PDP-6 allowed 
for
>> >any byte size from zero to thirty-sx bits, starting on any bit of a 
word,
>> >but unlike Stretch it did not allow a single byte to cross a word
>> >boundary.
>>
>> But the -6 didn't cross word boundaries...did it? IOW, if I had
>> a byte pointer 8 bits wide but pointing at bit 34, it wouldn't
>> pick up bits 34, 35, and concantentate it with bits 0, 1, 2, 3,
>> 4 and 5 of the next word.
>
>I thought the OP was asking about machines with a fixed byte 
>size.  

Ah, I missed that; thanks :-).

> ..I don't
>think the variable sized ones really count in this case.
>
>When I see a C compiler for the PDP-10, then maybe I can decide what byte
>really means for that machine.

Oh, it would probably take advantage of all those string instructions
they added to the microcode.  I understand why that project happened;
I never understood why they didn't just design a character device.
Caveat: I know nothing about hardware.

/BAH

Subtract a hundred and four for e-mail.

######

From: jmfbahciv@aol.com
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Thu, 06 Mar 03 12:39:25 GMT
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[spit..dammit..I keep forgetting they don't my posts over there]

In article <85smu03cpy.fsf@junk.nocrew.org>,
   Lars Brinkhoff <lars.spam@nocrew.org> wrote:
>jmfbahciv@aol.com writes:
>> "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote:
>> > When I see a C compiler for the PDP-10, then maybe I can decide
>> > what byte really means for that machine.
>> Oh, it would probably take advantage of all those string
>> instructions they added to the microcode.
>
>Actually, no.  I was told to avoid the string instructions in my port
>of GCC: "None of these is fast.  None of these is thoroughly tested.
>They all require a lot of registers for setup.  They are
>uncharacteristic of other PDP-10 instructions."
>
I know that.  That's why I added my speculation about designing
a device to do character manipulations for the process.

I never understood why anybody thought that a general purpose
time-sharing system could do batch processing (the way IBM
defined the term) well.


/BAH

Subtract a hundred and four for e-mail.

######

From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Newsgroups: comp.arch,alt.folklore.computers
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Subject: Re: Antiquity of Byte-Word addressing?
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<jmfbahciv@aol.com> wrote in message news:b44ti9$e2g$1@bob.news.rcn.net...
> In article <qhznoau12g.fsf@ruckus.brouhaha.com>,
(snip)
> >
> >The DEC PDP-6 had byte addressing for some instructions, and was first
> >shipped to customers in 1964, so it predates the IBM System/360 which
> >was announced in 1964 but not shipped until 1965.  The PDP-6 allowed for
> >any byte size from zero to thirty-sx bits, starting on any bit of a word,
> >but unlike Stretch it did not allow a single byte to cross a word
> >boundary.
>
> But the -6 didn't cross word boundaries...did it? IOW, if I had
> a byte pointer 8 bits wide but pointing at bit 34, it wouldn't
> pick up bits 34, 35, and concantentate it with bits 0, 1, 2, 3,
> 4 and 5 of the next word.

I thought the OP was asking about machines with a fixed byte size.  I don't
think the variable sized ones really count in this case.

When I see a C compiler for the PDP-10, then maybe I can decide what byte
really means for that machine.

-- glen

######

From: Lars Brinkhoff <lars.spam@nocrew.org>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: 06 Mar 2003 08:27:49 +0100
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"Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> writes:
> When I see a C compiler for the PDP-10, then maybe I can decide what
> byte really means for that machine.

There are several, but I don't think they are much help in your decision.

-- 
Lars Brinkhoff,         Services for Unix, Linux, GCC, PDP-10, HTTP
Brinkhoff Consulting    http://www.brinkhoff.se/

######

Sender: eric@ruckus.brouhaha.com
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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Organization: Eric Conspiracy Secret Labs
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"Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> writes:
> I thought the OP was asking about machines with a fixed byte size.  I don't
> think the variable sized ones really count in this case.

Didn't the OP bring up the IBM 7030 (Stretch)?  Stretch was the origin
of the term "byte", but it had a variable byte size (one to eight bits).

######

From: Lars Brinkhoff <lars.spam@nocrew.org>
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: 06 Mar 2003 13:23:53 +0100
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Xref: chonsp.franklin.ch alt.folklore.computers:131179

jmfbahciv@aol.com writes:
> "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote:
> > When I see a C compiler for the PDP-10, then maybe I can decide
> > what byte really means for that machine.
> Oh, it would probably take advantage of all those string
> instructions they added to the microcode.

Actually, no.  I was told to avoid the string instructions in my port
of GCC: "None of these is fast.  None of these is thoroughly tested.
They all require a lot of registers for setup.  They are
uncharacteristic of other PDP-10 instructions."

-- 
Lars Brinkhoff,         Services for Unix, Linux, GCC, PDP-10, HTTP
Brinkhoff Consulting    http://www.brinkhoff.se/

######

From: "Rupert Pigott" <roo@dark-try-removing-this-boong.demon.co.uk>
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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<jmfbahciv@aol.com> wrote in message news:b47i5s$oqu$3@bob.news.rcn.net...
[SNIP]

> I know that.  That's why I added my speculation about designing
> a device to do character manipulations for the process.

Cost, set up time and context switch complication comes
to mind. If it's another execution unit you may wish to
add another port to the register file (dunno how -10s
were wired) - which would cost bigish $$$ too. :)

Cheers,
Rupert

######

From: jmfbahciv@aol.com
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Fri, 07 Mar 03 10:21:53 GMT
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Xref: chonsp.franklin.ch alt.folklore.computers:131307

In article <1046958603.394263@saucer.planet.gong>,
   "Rupert Pigott" <roo@dark-try-removing-this-boong.demon.co.uk> wrote:
><jmfbahciv@aol.com> wrote in message news:b47i5s$oqu$3@bob.news.rcn.net...
>[SNIP]
>
>> I know that.  That's why I added my speculation about designing
>> a device to do character manipulations for the process.
>
>Cost, set up time and context switch complication comes
>to mind. If it's another execution unit you may wish to
>add another port to the register file (dunno how -10s
>were wired) - which would cost bigish $$$ too. :)

I don't know anything about the string manipulation biz :-).
You must as an expert app guy.  Is all string manipulation
done in-line?  That's a real clumsy question.  Let me try
again.  If you have a string that needs manipulation, does
the next logical step of the prog have to wait until it's
done?  If not, then shipping the stuff off to my "device"
would let the real CPU do other stuff until it gets a
done interrupt.

/BAH

Subtract a hundred and four for e-mail.

######

From: jmfbahciv@aol.com
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Fri, 07 Mar 03 10:28:00 GMT
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[spit]

In article <3e67a66a_4@news1.prserv.net>,
   Greg Pfister <pfister@us.ibm.com> wrote:
>Lars Brinkhoff wrote:
>> jmfbahciv@aol.com writes:
>> 
>>>"Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote:
>>>
>>>>When I see a C compiler for the PDP-10, then maybe I can decide
>>>>what byte really means for that machine.
>>>
>>>Oh, it would probably take advantage of all those string
>>>instructions they added to the microcode.
>> 
>> 
>> Actually, no.  I was told to avoid the string instructions in my port
>> of GCC: "None of these is fast.  None of these is thoroughly tested.
>> They all require a lot of registers for setup.  They are
>> uncharacteristic of other PDP-10 instructions."
>
>Now that's kind of wierd. Way back on grad school the group I was in 
>used a PDP-10, and (in assembler) we made regular and extensive use of 
>the string instructions.

Ah!  :-)  A real, live user of the instructions.  What kinds
of manipulations did you do?  I guess I'm asking for a design
goal (just in case the explanation is too complicated to dash
off in a newsgroup post).  I never understood that part (string
manipulations) of the computing biz.  My only experience was
sort, or merge-sort.

> .. Yes, the setup was painful, 

Oh, was it?  I don't think I ever looked at them.  I know
I never wrote one, let alone debugged it.  Did you have 
problems debugging the instructions?

> ...but it was the 
>best way to deal with 7-bit ASCII on a 36-bit machine.

<GRIN>  I've only done ILDBs myself.  That way I could examine
every character by hand.  Paranoia, I guess.
>
>"Uncharacteristic of other PDP-10 instructions" matters only to a 
>compiler. :-)

Not when it's in a state of BLISS-10.

/BAH

Subtract a hundred and four for e-mail.

######

From: jmfbahciv@aol.com
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Sat, 08 Mar 03 11:51:29 GMT
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Xref: chonsp.franklin.ch alt.folklore.computers:131346

In article <3E6918B9.71601FD4@yahoo.com>,
   Peter Flass <peter_flass@yahoo.com> wrote:
>jmfbahciv@aol.com wrote:
>> 
>> If you have a string that needs manipulation, does
>> the next logical step of the prog have to wait until it's
>> done?  If not, then shipping the stuff off to my "device"
>> would let the real CPU do other stuff until it gets a
>> done interrupt.
>
>I would think it depends on your compiler/assembler/execution unit.

Nope.  The only reason to single-step the computations is because
the process is ordered.  For instance, I can't calculate an acceleration
until a distance has been input.  I'm merely wondering if string
computations in the world are similar.  

I guess what I'm asking is:  Are all string computation problems
a sort.  That is definitely a step function; but even then the
sort can be shipped to a sort device, letting the CPU do 
what it does best.

 
>Most programmers being linear thinkers, they'd probably code it
>sequentially.

Yea, I know how most people think.  But these can also comprehend
packing up a piece so that somebody else does the work, e.g. they
don't do their own drycleaning.  All HLL programmers let the
compiler package to the real arithmetic.

> ..  Rearranging the instructions, such as is frequently done
>nowadays would run into problems with memory aliasing through different
>pointers, multiple CPU's, channel hardware, etc.  It's easier to keep
>track of an FP register than an arbitrary block of memory.

It is?  I'd much rather deal with memeory than an FP register.
With memory, once I tell it to stay put, it does.

/BAH


Subtract a hundred and four for e-mail.

######

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Greg Pfister  <pfister@us.ibm.com> wrote:
+---------------
| Lars Brinkhoff wrote:
| > jmfbahciv@aol.com writes:
| >>"Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote:
| >>>When I see a C compiler for the PDP-10, then maybe I can decide
| >>>what byte really means for that machine.
| >>
| >>Oh, it would probably take advantage of all those string
| >>instructions they added to the microcode.
| > 
| > Actually, no.  I was told to avoid the string instructions in my port
| > of GCC: "None of these is fast.  None of these is thoroughly tested.
| > They all require a lot of registers for setup.  They are
| > uncharacteristic of other PDP-10 instructions."
| 
| Now that's kind of wierd. Way back on grad school the group I was in 
| used a PDP-10, and (in assembler) we made regular and extensive use of 
| the string instructions. Yes, the setup was painful, but it was the 
| best way to deal with 7-bit ASCII on a 36-bit machine.
+---------------

Are you sure you're not thinking of the original {I,}{L,D}PB
instructions?  While they could certainly be (and were) used
for "string processing" (7-bit, 8-bit, 9-bit), I don't think
those are the "string instructions" Barb is talking about. IIRC
the latter were added *very* late in the PDP-10 architectural
evolution...

+---------------
| "Uncharacteristic of other PDP-10 instructions" matters only to a 
| compiler. :-)
+---------------

Not back in those days, when the entire O/S was hand-coded in assembler!!


-Rob

-----
Rob Warnock, PP-ASEL-IA		<rpw3@rpw3.org>
627 26th Avenue			<URL:http://rpw3.org/>
San Mateo, CA 94403		(650)572-2607

######

From: "Rupert Pigott" <roo@dark-try-removing-this-boong.demon.co.uk>
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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Xref: chonsp.franklin.ch alt.folklore.computers:131361

<jmfbahciv@aol.com> wrote in message news:b49ug9$ec$4@bob.news.rcn.net...
> In article <1046958603.394263@saucer.planet.gong>,
>    "Rupert Pigott" <roo@dark-try-removing-this-boong.demon.co.uk> wrote:
> ><jmfbahciv@aol.com> wrote in message
news:b47i5s$oqu$3@bob.news.rcn.net...
> >[SNIP]
> >
> >> I know that.  That's why I added my speculation about designing
> >> a device to do character manipulations for the process.
> >
> >Cost, set up time and context switch complication comes
> >to mind. If it's another execution unit you may wish to
> >add another port to the register file (dunno how -10s
> >were wired) - which would cost bigish $$$ too. :)
>
> I don't know anything about the string manipulation biz :-).
> You must as an expert app guy.  Is all string manipulation
> done in-line?  That's a real clumsy question.  Let me try
> again.  If you have a string that needs manipulation, does
> the next logical step of the prog have to wait until it's
> done?  If not, then shipping the stuff off to my "device"
> would let the real CPU do other stuff until it gets a
> done interrupt.

In most code the answer is : Yes, it sits there and
waits, mainly because people expect the hardware to
execute in series. The compiler may be at liberty
to re-order stuff depending on the language & rules ;)

OMG... You just woke up braincells which haven't worked
since I was hacking T80[0/1/5]'s at INMOS... Their FPU
basically would execute in the background like that,
although stuff like interrupts and register transfers
would sync it up. You could do some very nifty stuff
like Matrix ops where the FP work overlapped the array
element address calculations...

T800's were f**king awesome to put it bluntly. :)

T800s could do lots of other neat things 'async' too,
like I/O on all four of their 20Mbit bi-directional
links in the background.

Cheers,
Rupert

######

From: bfranchuk@jetnet.ab.ca
Newsgroups: comp.arch,alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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Rob Warnock wrote:

> Not back in those days, when the entire O/S was hand-coded in assembler!!
Lets not forget the original apple basic, was hand coded too.
Ben.

######

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jmfbahciv@aol.com wrote:
> 
> If you have a string that needs manipulation, does
> the next logical step of the prog have to wait until it's
> done?  If not, then shipping the stuff off to my "device"
> would let the real CPU do other stuff until it gets a
> done interrupt.

I would think it depends on your compiler/assembler/execution unit. 
Most programmers being linear thinkers, they'd probably code it
sequentially.  Rearranging the instructions, such as is frequently done
nowadays would run into problems with memory aliasing through different
pointers, multiple CPU's, channel hardware, etc.  It's easier to keep
track of an FP register than an arbitrary block of memory.

######

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On Fri, 7 Mar 2003 13:09:53 -0000 in alt.folklore.computers,
"Rupert Pigott" <roo@dark-try-removing-this-boong.demon.co.uk>
wrote:

><jmfbahciv@aol.com> wrote in message news:b49ug9$ec$4@bob.news.rcn.net...
>> In article <1046958603.394263@saucer.planet.gong>,
>>    "Rupert Pigott" <roo@dark-try-removing-this-boong.demon.co.uk> wrote:
>> ><jmfbahciv@aol.com> wrote in message
>news:b47i5s$oqu$3@bob.news.rcn.net...
>> >[SNIP]
>> >
>> >> I know that.  That's why I added my speculation about designing
>> >> a device to do character manipulations for the process.
>> >
>> >Cost, set up time and context switch complication comes
>> >to mind. If it's another execution unit you may wish to
>> >add another port to the register file (dunno how -10s
>> >were wired) - which would cost bigish $$$ too. :)
>>
>> I don't know anything about the string manipulation biz :-).
>> You must as an expert app guy.  Is all string manipulation
>> done in-line?  That's a real clumsy question.  Let me try
>> again.  If you have a string that needs manipulation, does
>> the next logical step of the prog have to wait until it's
>> done?  If not, then shipping the stuff off to my "device"
>> would let the real CPU do other stuff until it gets a
>> done interrupt.
>
>In most code the answer is : Yes, it sits there and
>waits, mainly because people expect the hardware to
>execute in series. The compiler may be at liberty
>to re-order stuff depending on the language & rules ;)
>
>OMG... You just woke up braincells which haven't worked
>since I was hacking T80[0/1/5]'s at INMOS... Their FPU
>basically would execute in the background like that,
>although stuff like interrupts and register transfers
>would sync it up. You could do some very nifty stuff
>like Matrix ops where the FP work overlapped the array
>element address calculations...

The x86 and x87 worked mostly asynchronously since the early
days: check out opcodes ESC and FWAIT: more recent versions do
the wait implicitly when it's required to sync the CPU and FPU. 

Thanks. Take care, Brian Inglis 	Calgary, Alberta, Canada
-- 
Brian.Inglis@CSi.com 	(Brian dot Inglis at SystematicSw dot ab dot ca)
    fake address		use address above to reply
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######

Newsgroups: alt.folklore.computers
From: Charles Shannon Hendrix <shannon@news.widomaker.com>
Subject: Re: Antiquity of Byte-Word addressing?
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In article <1047042594.63477@saucer.planet.gong>, Rupert Pigott wrote:

> OMG... You just woke up braincells which haven't worked
> since I was hacking T80[0/1/5]'s at INMOS... Their FPU
> basically would execute in the background like that,
> although stuff like interrupts and register transfers
> would sync it up. You could do some very nifty stuff
> like Matrix ops where the FP work overlapped the array
> element address calculations...
> 
> T800's were f**king awesome to put it bluntly. :)
> 
> T800s could do lots of other neat things 'async' too,
> like I/O on all four of their 20Mbit bi-directional
> links in the background.

Did you ever look at the Atari transputer systems?

######

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<bfranchuk@jetnet.ab.ca> wrote:
+---------------
| Rob Warnock wrote:
| > Not back in those days, when the entire O/S was hand-coded in assembler!!
|
| Lets not forget the original apple basic, was hand coded too.
+---------------

So what? That was more than a decade later!

1964 -- PDP-6 first shipped. Mostly the same ISA as PDP-10,
        and PDP-6 Monitor (assembler) was direct ancestor to
        PDP-10 Monitor (later known as TOPS-10).

1967 -- PDP-10

...time passes...

1976 -- Apple-I


-Rob

-----
Rob Warnock, PP-ASEL-IA		<rpw3@rpw3.org>
627 26th Avenue			<URL:http://rpw3.org/>
San Mateo, CA 94403		(650)572-2607

######

From: "Rupert Pigott" <roo@dark-try-removing-this-boong.demon.co.uk>
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Sat, 8 Mar 2003 13:12:15 -0000
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"Charles Shannon Hendrix" <shannon@news.widomaker.com> wrote in message
news:slrnb6j37b.4qp.shannon@news.widomaker.com...
> In article <1047042594.63477@saucer.planet.gong>, Rupert Pigott wrote:
>
> > OMG... You just woke up braincells which haven't worked
> > since I was hacking T80[0/1/5]'s at INMOS... Their FPU
> > basically would execute in the background like that,
> > although stuff like interrupts and register transfers
> > would sync it up. You could do some very nifty stuff
> > like Matrix ops where the FP work overlapped the array
> > element address calculations...
> >
> > T800's were f**king awesome to put it bluntly. :)
> >
> > T800s could do lots of other neat things 'async' too,
> > like I/O on all four of their 20Mbit bi-directional
> > links in the background.
>
> Did you ever look at the Atari transputer systems?

I always wanted to look at an ATW... The specs looked
pretty nifty, they ran Helios didn't they ?

However, when compared to the pile of junk/production
cards I assembled on my desk at INMOS they looked
pretty weak. It was fun building MPPs like Lego. ;)

Cheers,
Rupert

######

Message-ID: <3E6A2092.8C6920CF@yahoo.com>
From: Peter Flass <peter_flass@yahoo.com>
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Xref: chonsp.franklin.ch alt.folklore.computers:131246

jmfbahciv@aol.com wrote:
> 
> In article <3E6918B9.71601FD4@yahoo.com>,
>    Peter Flass <peter_flass@yahoo.com> wrote:
> >jmfbahciv@aol.com wrote:
> >>
> >> If you have a string that needs manipulation, does
> >> the next logical step of the prog have to wait until it's
> >> done?  If not, then shipping the stuff off to my "device"
> >> would let the real CPU do other stuff until it gets a
> >> done interrupt.
> >
> >I would think it depends on your compiler/assembler/execution unit.
> 
> Nope.  The only reason to single-step the computations is because
> the process is ordered.  For instance, I can't calculate an acceleration
> until a distance has been input.  I'm merely wondering if string
> computations in the world are similar.

I guess nobody answered this yet.  I'd have to say yes.  A typical type
of problem noght involve scanning a string for a comma, copying all the
text from the beginning to the comma somewhere else, appending a second
string to the result, and then appending the remainder of the original
string.  Once you get beyond simple moves and compares, long sequences
of string instructions would be common.
> 
> 
> > ..  Rearranging the instructions, such as is frequently done
> >nowadays would run into problems with memory aliasing through different
> >pointers, multiple CPU's, channel hardware, etc.  It's easier to keep
> >track of an FP register than an arbitrary block of memory.
> 
> It is?  I'd much rather deal with memeory than an FP register.
> With memory, once I tell it to stay put, it does.

Well, it stays put, but you're talking in general about an arbitrary
area of memory of arbitrary length.  Unlike an FP register it might be
accessed anywhere at any arbirary byte, and could overlap other string
fields, and other non-string fields also- for example you could have a
32-byte field accessed as a string (for example to clear it to zeroes)
and also as 8 32-bit words for arithmetic.  Your string unit would have
to interlock memory with the rest of the processor.

######

From: jmfbahciv@aol.com
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Sun, 09 Mar 03 12:43:53 GMT
Organization: UltraNet Communications, Inc.
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Xref: chonsp.franklin.ch alt.folklore.computers:131543

In article <3E6A2092.8C6920CF@yahoo.com>,
   Peter Flass <peter_flass@yahoo.com> wrote:
>jmfbahciv@aol.com wrote:
>> 
>> In article <3E6918B9.71601FD4@yahoo.com>,
>>    Peter Flass <peter_flass@yahoo.com> wrote:
>> >jmfbahciv@aol.com wrote:
>> >>
>> >> If you have a string that needs manipulation, does
>> >> the next logical step of the prog have to wait until it's
>> >> done?  If not, then shipping the stuff off to my "device"
>> >> would let the real CPU do other stuff until it gets a
>> >> done interrupt.
>> >
>> >I would think it depends on your compiler/assembler/execution unit.
>> 
>> Nope.  The only reason to single-step the computations is because
>> the process is ordered.  For instance, I can't calculate an acceleration
>> until a distance has been input.  I'm merely wondering if string
>> computations in the world are similar.
>
>I guess nobody answered this yet. 

Nope, they haven't; now you have.  Thank you :-)

> .. I'd have to say yes.  A typical type
>of problem noght involve scanning a string for a comma, copying all the
>text from the beginning to the comma somewhere else, appending a second
>string to the result, and then appending the remainder of the original
>string.  Once you get beyond simple moves and compares, long sequences
>of string instructions would be common.

This would be a typesetting app or an editor.  In the case of an
editor (which implied interaction between user and machine at
the same wall-clock time), slowness (or speed) doesn't matter.
So that leaves the typesetting.  In the olden days (I don't 
how it's getting done now), the typesetting action was done
on a device that happened to have a CPU dedicated for the function.
Where is that guy who produces books?  Are you still here?

How much of DBMS stuff is string manipulation?  I would think
that most of it would be string substitution unless a field length
had to be expanded.

>> 
>> 
>> > ..  Rearranging the instructions, such as is frequently done
>> >nowadays would run into problems with memory aliasing through different
>> >pointers, multiple CPU's, channel hardware, etc.  It's easier to keep
>> >track of an FP register than an arbitrary block of memory.
>> 
>> It is?  I'd much rather deal with memeory than an FP register.
>> With memory, once I tell it to stay put, it does.
>
>Well, it stays put, but you're talking in general about an arbitrary
>area of memory of arbitrary length. 

Yea; those are numbers that I can keep track of.  No system
is going to yank them out from underneath me.

> ... Unlike an FP register it might be
>accessed anywhere at any arbirary byte, and could overlap other string
>fields, and other non-string fields also- for example you could have a
>32-byte field accessed as a string (for example to clear it to zeroes)
>and also as 8 32-bit words for arithmetic.  Your string unit would have
>to interlock memory with the rest of the processor.

why?..Oh, I see.  That's one of reasons I kept hardware on the
guy-thing list.  I wasn't thinking of sharing the memory.  I
was thinking of shipping it off to be "owned" by my string device.
The argument list that I would set up would be beginning address
of string, ending address of string (or length), operation to be
done, ship it; I no longer have that data in my address space
and won't be able to look at it until the device ships the request
back.

I'm assuming it's not profitable to design a piece of gear for
this (based on the fact it doesn't exists :-)).


/BAH


Subtract a hundred and four for e-mail.

######

Newsgroups: alt.folklore.computers
From: Charles Shannon Hendrix <shannon@news.widomaker.com>
Subject: Re: Antiquity of Byte-Word addressing?
References: <5tC5a.1106$TR4.120765@newsread1.prod.itd.earthlink.net> <qhznoau12g.fsf@ruckus.brouhaha.com> <b44ti9$e2g$1@bob.news.rcn.net> <LFw9a.372154$be.342715@rwcrnsc53> <b47a8r$ahj$1@bob.news.rcn.net> <85smu03cpy.fsf@junk.nocrew.org> <b47i5s$oqu$3@bob.news.rcn.net> <1046958603.394263@saucer.planet.gong> <b49ug9$ec$4@bob.news.rcn.net> <1047042594.63477@saucer.planet.gong> <slrnb6j37b.4qp.shannon@news.widomaker.com> <1047129136.16706@saucer.planet.gong>
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Xref: chonsp.franklin.ch alt.folklore.computers:131517

In article <1047129136.16706@saucer.planet.gong>, Rupert Pigott wrote:

>> Did you ever look at the Atari transputer systems?
> 
> I always wanted to look at an ATW... The specs looked
> pretty nifty, they ran Helios didn't they ?

That was the plan.

> However, when compared to the pile of junk/production
> cards I assembled on my desk at INMOS they looked
> pretty weak. It was fun building MPPs like Lego. ;)

I thought they could use the same stuff?

There is a web site out there with picture of one a guy has in
his collection.  Bastard also managed to snag a 1450XLD too.

No US sales, but evidently a few went out in the UK, and maybe
Europe.

######

From: pechter@shell.monmouth.com (Bill/Carolyn Pechter)
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: 10 Mar 2003 16:03:31 -0500
Organization: Lakewood MicroSystems
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Xref: chonsp.franklin.ch alt.folklore.computers:131699

In article <b4hutt$9u2$1@bob.news.rcn.net>,  <jmfbahciv@aol.com> wrote:
>
>Sigh!  YOu don't need a CPU do a dump to and from disk.  You do
>need a CPU to tell the controller where it may dump.
>
>/BAH
>
>Subtract a hundred and four for e-mail.

Depends on the machine involved.  Some machines have smart disk
controllers and just have to point the buffer start to the controller.
Then magic happens... 8-)

Some machines you have to have the cpu do the seek, read header etc.

The DEC RL11 controller (RL01/RL02 disks) was too dumb to do an implied
seek when it reached the end of the track and had to switch heads.

The older RK11 controller (RK05 disks) did that without problems.
The RL had a single (2 on qbus) board controller... the RK05 was an
entire backplane unit (4? slots).

You assume smart controllers -  some were pretty dumb...  you often have 
to tell the controller where to dump but also to read the header to figure
out where it was and to read it again after a seek and to offset to recover
damaged blocks...

In the old days and on some newer hardware this is automatic, with the
smarts built in to either the drive or the controller.  But there was a
window of time that to shrink the size of drive and the controller
that some functionality was traded off for cost/size and to reduce
complexity.

Bill

-- 
+---------------------------------------------------------------------------+
| Bill and/or Carolyn Pechter    |        pechter@shell.monmouth.com        |
|   Bill Gates is a Persian cat and a monocle away from being a villain in  |
|   a James Bond movie              -- Dennis Miller                        | 
+---------------------------------------------------------------------------+

######

From: jmfbahciv@aol.com
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Tue, 11 Mar 03 12:20:14 GMT
Organization: UltraNet Communications, Inc.
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Xref: chonsp.franklin.ch alt.folklore.computers:131735

In article <b4iuj3$jkg$1@shell.monmouth.com>,
   pechter@shell.monmouth.com (Bill/Carolyn Pechter) wrote:
>In article <b4hutt$9u2$1@bob.news.rcn.net>,  <jmfbahciv@aol.com> wrote:
>>
>>Sigh!  YOu don't need a CPU do a dump to and from disk.  You do
>>need a CPU to tell the controller where it may dump.
>>
>>/BAH
>>
>>Subtract a hundred and four for e-mail.
>
>Depends on the machine involved.  Some machines have smart disk
>controllers and just have to point the buffer start to the controller.
>Then magic happens... 8-)

Yea.  I was think I was thinking about file structure organization
when I wrote that.  It takes a lot more code to do that than to
do a straight dump.

>
>Some machines you have to have the cpu do the seek, read header etc.
>
>The DEC RL11 controller (RL01/RL02 disks) was too dumb to do an implied
>seek when it reached the end of the track and had to switch heads.

The machines (I've been told about) that do data capture were usually
PDP-8s.  But I didn't understand anything about how it was hooked
up.  I sure like to look at that stuff.

>
>The older RK11 controller (RK05 disks) did that without problems.
>The RL had a single (2 on qbus) board controller... the RK05 was an
>entire backplane unit (4? slots).
>
>You assume smart controllers -  some were pretty dumb...  you often have 
>to tell the controller where to dump but also to read the header to figure
>out where it was and to read it again after a seek and to offset to 
recover
>damaged blocks...
>
>In the old days and on some newer hardware this is automatic, with the
>smarts built in to either the drive or the controller.  But there was a
>window of time that to shrink the size of drive and the controller
>that some functionality was traded off for cost/size and to reduce
>complexity.

Maybe I'm confused about the medium used to record data (I'm still
thinking real real-time).  I assumed disks.  Perhaps they were 
magtapes instead?

/BAH

Subtract a hundred and four for e-mail.

######

From: jmfbahciv@aol.com
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Tue, 11 Mar 03 12:26:16 GMT
Organization: UltraNet Communications, Inc.
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Xref: chonsp.franklin.ch alt.folklore.computers:131732

In article <slrnb6r138.r97.shannon@news.widomaker.com>,
   Charles Shannon Hendrix <shannon@news.widomaker.com> wrote:
>In article <b4hutt$9u2$1@bob.news.rcn.net>, jmfbahciv@aol.com wrote:
>
>>> ..most would be multibyte, except for the occasional
>>>integer. DB stored (as opposed to defined maximum) column lengths
>>>change all the time, so there's a lot of shuffling going on, and
>>>even conversion, behind the scenes. 
>> 
>> But are all of this data strings?
>
>Doesn't really matter if they are or not.  The CPU doesn't care as a
>"string" doesn't exist from the CPUs point of view.
>
>It only has meaning to us.

Yea, I know.  I just figured that a string instruction would
be some address with some mask with an operation implied in
the opcode.  It that's not so, then the only other thing
I could think of would be a software routine that loaded bytes,
chewed them, then dumped them.



>
>Move graphics data, numbers, random noise, or War and Peaces... it's
>all the same to the CPU.

That's what I'd always assumed :-).  So why did all of that money
get spend on hardware...or firmware... to do string manipulations?
The only reason to move a function down to a lower level is 
performance improvements...or is this another bad assumpion on
my part?
>
>>> ..and there's at least a couple of ways of doing
>>>it, called CISC (3x0, VAX) and RISC; although both boil down to
>>>moving words wherever possible: one in the microcode, the other
>>>in an assembler routine. 
>> 
>> Wait a minute.  Moving words isn't all character string modifications.
>> Most of the moves that I've seen is address setup..other than
>> filling/emptying buffers of disk data.          
>
>True, but character data moves is probably second only to graphics
>data on modern workstations.

REally? 

>
>On a large Sun server I did some performance testing and things like
>that, and moving character strings was over 90% of the non I/O portion
>of some of our code.  If the programs did math, it was a little less,
>but still made up an awful lot of the code.

Well, of course.  It was a server.  Moving bits around is its
primary job!
<snip>

/BAH

Subtract a hundred and four for e-mail.

######

From: jmfbahciv@aol.com
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Tue, 11 Mar 03 12:40:06 GMT
Organization: UltraNet Communications, Inc.
Lines: 176
Message-ID: <b4ko4r$fne$1@bob.news.rcn.net>
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Xref: chonsp.franklin.ch alt.folklore.computers:131749

In article <bsvq6v4mhvjks8srfm0nbfghar06mmhgti@4ax.com>,
   Brian Inglis <Brian.Inglis@SystematicSw.ab.ca> wrote:
>On Mon, 10 Mar 03 11:17:38 GMT in alt.folklore.computers,
>jmfbahciv@aol.com wrote:
>
>>In article <cv7o6vghhei8p5d53scpejb5lvlkm75kl2@4ax.com>,
>>   Brian Inglis <Brian.Inglis@SystematicSw.ab.ca> wrote:
>>>On Sun, 09 Mar 03 12:43:53 GMT in alt.folklore.computers,
>>>jmfbahciv@aol.com wrote:
>>>
>>>>In article <3E6A2092.8C6920CF@yahoo.com>,
>>>>   Peter Flass <peter_flass@yahoo.com> wrote:
>>>>>jmfbahciv@aol.com wrote:
>>>>>> 
>>>>>> In article <3E6918B9.71601FD4@yahoo.com>,
>>>>>>    Peter Flass <peter_flass@yahoo.com> wrote:
>>>>>> >jmfbahciv@aol.com wrote:
>>>>>> >>
>>>>>> >> If you have a string that needs manipulation, does
>>>>>> >> the next logical step of the prog have to wait until it's
>>>>>> >> done?  If not, then shipping the stuff off to my "device"
>>>>>> >> would let the real CPU do other stuff until it gets a
>>>>>> >> done interrupt.
>>>>>> >
>>>>>> >I would think it depends on your compiler/assembler/execution unit.
>>>>>> 
>>>>>> Nope.  The only reason to single-step the computations is because
>>>>>> the process is ordered.  For instance, I can't calculate an 
>>acceleration
>>>>>> until a distance has been input.  I'm merely wondering if string
>>>>>> computations in the world are similar.
>>>>>
>>>>>I guess nobody answered this yet. 
>>>>
>>>>Nope, they haven't; now you have.  Thank you :-)
>>>>
>>>>> .. I'd have to say yes.  A typical type
>>>>>of problem noght involve scanning a string for a comma, copying all 
the
>>>>>text from the beginning to the comma somewhere else, appending a 
second
>>>>>string to the result, and then appending the remainder of the original
>>>>>string.  Once you get beyond simple moves and compares, long sequences
>>>>>of string instructions would be common.
>>>>
>>>>This would be a typesetting app or an editor.  In the case of an
>>>>editor (which implied interaction between user and machine at
>>>>the same wall-clock time), slowness (or speed) doesn't matter.
>>>>So that leaves the typesetting.  In the olden days (I don't 
>>>>how it's getting done now), the typesetting action was done
>>>>on a device that happened to have a CPU dedicated for the function.
>>>>Where is that guy who produces books?  Are you still here?
>>>
>>>A lot of apps handle lots of strings nowadays: all GUIs and most
>>>Unix command line apps are string shufflers. 
>>
>>Can you be more precise.  What strings are munged?  As far as
>>I can see here, character string operations still seem to be
>>in the two classes.
>
>The GUIs mung a bunch of bitstrings every time you move your UDH;
>Unix apps pull strings apart, pass them around, and reassemble
>them in interesting ways. 
>Which two classes? 

Editing and document production.  And I'm sorry to say that
I cannot recall why I started talking about this.  I think
my brain spazzed :-(.  I know it got started with something
somebody said and my reading a text on how to make books.


>Good programmers tend to avoid shuffling strings whenever
>possible, passing around pointers and lengths, but some easier to
>use and object oriented languages do a lot of string creation,
>munging, and destruction behind the scenes. 
>Think what various DEC Basics did with strings and garbage
>collection behind the scenes; and multiply that by one thousand
>for some modern apps. 

Barf.  Is it all necessary?

<snip>

>>>>How much of DBMS stuff is string manipulation?  I would think
>>>>that most of it would be string substitution unless a field length
>>>>had to be expanded.
>>>
>>>IBM stats said 30% of instructions in commercial programs were
>>>moves: 
>>
>>I'm surprised it was that low.  I would have guessed 70%...
>>even that might have be low.
>
>The other two to three were probably loops, indexing or address
>calculations, count updates, tests, etc. 

For commercial programs?  OH, I see.  YOu're talking about
PERFORM FOOBAR WHILE X UNCHANGED cases.  I didn't think that
commercial shops' main computing was producing reports.  I guess
I'd always thought that most of the computing needs was keeping
track of all the data without interfering the report production.
(Report production could be printing bills, envelops, P&L statements,
etc.).

>
>>> ..most would be multibyte, except for the occasional
>>>integer. DB stored (as opposed to defined maximum) column lengths
>>>change all the time, so there's a lot of shuffling going on, and
>>>even conversion, behind the scenes. 
>>
>>But are all of this data strings?
>
>Not a lot of numeric stuff is stored as binary types in DBs or
>used as such in programs nowadays, 

Aaaahhh!!!  That's my bug :-)))

> ..so they don't need to be
>converted: mainly packed or unpacked digit strings, and lots of
>arbitrary character strings. 
>
>>>>I'm assuming it's not profitable to design a piece of gear for
>>>>this (based on the fact it doesn't exists :-)).
>>>
>>>It's called a CPU 
>>
>>Sigh!  YOu don't need a CPU do a dump to and from disk.  You do
>>need a CPU to tell the controller where it may dump.
>
>You were talking about a string thing, not I/O. 

[dejected emoticon here] I no longer know what I was talking about.

>
>>> ..and there's at least a couple of ways of doing
>>>it, called CISC (3x0, VAX) and RISC; although both boil down to
>>>moving words wherever possible: one in the microcode, the other
>>>in an assembler routine. 
>>
>>Wait a minute.  Moving words isn't all character string modifications.
>>Most of the moves that I've seen is address setup..other than
>>filling/emptying buffers of disk data.          
>
>Most machines are now word oriented at the core, so shuffling
>four bytes to or from a word may involve fetching, modifying,
>updating a word four times: better to shuffle the words whenever
>possible. 

<GRIN>  So bytes are a myth?  It's about time!

>
>>Although...now I'm thinking of comm.  In the olden days, when
>>people typed characters, I guess those packets would be filled
>>bits that might be considered a character string.  But in this
>>pointy-click generation that doesn't seem to apply.  What exactly
>>gets sent on the wire with a point click these days?  From what
>>I see, I've been assuming that the only thing necessary is an
>>address of the screen.
>
>Depends on the platform and app: local windows apps would get a
>packet with a couple of pixel coordinates and button bits every
>few ms from the mouse when it's moving, blast a few bytes to the
>screen buffer to update the mouse pointer; remote screen editing
>apps would get a packet with a character or two among all the
>protocol bytes, and echo similarly: like LAT but worse IIRC;
>remote windows apps would get sent multibyte motion packets with
>protocol wrappers when things were moving, and send back graphic
>screen update packets when things changed; remote command line
>apps might get a line every few seconds, and send back a line or
>a screed of lines in response. 

Good grief!  Motion ain't local?  Now I am getting a remote headache.

/BAH

Subtract a hundred and four for e-mail.

######

Newsgroups: alt.folklore.computers
From: Charles Shannon Hendrix <shannon@news.widomaker.com>
Subject: Re: Antiquity of Byte-Word addressing?
References: <5tC5a.1106$TR4.120765@newsread1.prod.itd.earthlink.net> <qhznoau12g.fsf@ruckus.brouhaha.com> <b44ti9$e2g$1@bob.news.rcn.net> <LFw9a.372154$be.342715@rwcrnsc53> <b47a8r$ahj$1@bob.news.rcn.net> <85smu03cpy.fsf@junk.nocrew.org> <b47i5s$oqu$3@bob.news.rcn.net> <1046958603.394263@saucer.planet.gong> <b49ug9$ec$4@bob.news.rcn.net> <3E6918B9.71601FD4@yahoo.com> <b4co4l$qed$1@bob.news.rcn.net> <3E6A2092.8C6920CF@yahoo.com> <b4ffj6$p01$1@bob.news.rcn.net> <cv7o6vghhei8p5d53scpejb5lvlkm75kl2@4ax.com> <b4hutt$9u2$1@bob.news.rcn.net>
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Xref: chonsp.franklin.ch alt.folklore.computers:131801

In article <b4hutt$9u2$1@bob.news.rcn.net>, jmfbahciv@aol.com wrote:

>> ..most would be multibyte, except for the occasional
>>integer. DB stored (as opposed to defined maximum) column lengths
>>change all the time, so there's a lot of shuffling going on, and
>>even conversion, behind the scenes. 
> 
> But are all of this data strings?

Doesn't really matter if they are or not.  The CPU doesn't care as a
"string" doesn't exist from the CPUs point of view.

It only has meaning to us.

Move graphics data, numbers, random noise, or War and Peaces... it's
all the same to the CPU.

>> ..and there's at least a couple of ways of doing
>>it, called CISC (3x0, VAX) and RISC; although both boil down to
>>moving words wherever possible: one in the microcode, the other
>>in an assembler routine. 
> 
> Wait a minute.  Moving words isn't all character string modifications.
> Most of the moves that I've seen is address setup..other than
> filling/emptying buffers of disk data.          

True, but character data moves is probably second only to graphics
data on modern workstations.

On a large Sun server I did some performance testing and things like
that, and moving character strings was over 90% of the non I/O portion
of some of our code.  If the programs did math, it was a little less,
but still made up an awful lot of the code.

> Although...now I'm thinking of comm.  In the olden days, when
> people typed characters, I guess those packets would be filled
> bits that might be considered a character string.  But in this
> pointy-click generation that doesn't seem to apply.  What exactly
> gets sent on the wire with a point click these days?  From what
> I see, I've been assuming that the only thing necessary is an
> address of the screen.

Depends on the system.

For X, you have a defined message protocol for graphics over the wire.

For other systems, you have some kind of kludge to move graphics data
between server and client.

######

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From: Brian Inglis <Brian.Inglis@SystematicSw.ab.ca>
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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On Mon, 10 Mar 03 11:17:38 GMT in alt.folklore.computers,
jmfbahciv@aol.com wrote:

>In article <cv7o6vghhei8p5d53scpejb5lvlkm75kl2@4ax.com>,
>   Brian Inglis <Brian.Inglis@SystematicSw.ab.ca> wrote:
>>On Sun, 09 Mar 03 12:43:53 GMT in alt.folklore.computers,
>>jmfbahciv@aol.com wrote:
>>
>>>In article <3E6A2092.8C6920CF@yahoo.com>,
>>>   Peter Flass <peter_flass@yahoo.com> wrote:
>>>>jmfbahciv@aol.com wrote:
>>>>> 
>>>>> In article <3E6918B9.71601FD4@yahoo.com>,
>>>>>    Peter Flass <peter_flass@yahoo.com> wrote:
>>>>> >jmfbahciv@aol.com wrote:
>>>>> >>
>>>>> >> If you have a string that needs manipulation, does
>>>>> >> the next logical step of the prog have to wait until it's
>>>>> >> done?  If not, then shipping the stuff off to my "device"
>>>>> >> would let the real CPU do other stuff until it gets a
>>>>> >> done interrupt.
>>>>> >
>>>>> >I would think it depends on your compiler/assembler/execution unit.
>>>>> 
>>>>> Nope.  The only reason to single-step the computations is because
>>>>> the process is ordered.  For instance, I can't calculate an 
>acceleration
>>>>> until a distance has been input.  I'm merely wondering if string
>>>>> computations in the world are similar.
>>>>
>>>>I guess nobody answered this yet. 
>>>
>>>Nope, they haven't; now you have.  Thank you :-)
>>>
>>>> .. I'd have to say yes.  A typical type
>>>>of problem noght involve scanning a string for a comma, copying all the
>>>>text from the beginning to the comma somewhere else, appending a second
>>>>string to the result, and then appending the remainder of the original
>>>>string.  Once you get beyond simple moves and compares, long sequences
>>>>of string instructions would be common.
>>>
>>>This would be a typesetting app or an editor.  In the case of an
>>>editor (which implied interaction between user and machine at
>>>the same wall-clock time), slowness (or speed) doesn't matter.
>>>So that leaves the typesetting.  In the olden days (I don't 
>>>how it's getting done now), the typesetting action was done
>>>on a device that happened to have a CPU dedicated for the function.
>>>Where is that guy who produces books?  Are you still here?
>>
>>A lot of apps handle lots of strings nowadays: all GUIs and most
>>Unix command line apps are string shufflers. 
>
>Can you be more precise.  What strings are munged?  As far as
>I can see here, character string operations still seem to be
>in the two classes.

The GUIs mung a bunch of bitstrings every time you move your UDH;
Unix apps pull strings apart, pass them around, and reassemble
them in interesting ways. 
Which two classes? 
Good programmers tend to avoid shuffling strings whenever
possible, passing around pointers and lengths, but some easier to
use and object oriented languages do a lot of string creation,
munging, and destruction behind the scenes. 
Think what various DEC Basics did with strings and garbage
collection behind the scenes; and multiply that by one thousand
for some modern apps. 

>>Editing and typesetting became word processing a couple of
>>decades ago: processing bytes into bitmaps and moving bitstrings,
>>or figuring out what bitmaps and where they should be generated.
>
>Fine.  The two have been merged under a new category if you want.
>In my world, all editing was not typesetting or doc prepping.
>We edited sources and build and packaging procedures, too. 
>>
>>>How much of DBMS stuff is string manipulation?  I would think
>>>that most of it would be string substitution unless a field length
>>>had to be expanded.
>>
>>IBM stats said 30% of instructions in commercial programs were
>>moves: 
>
>I'm surprised it was that low.  I would have guessed 70%...
>even that might have be low.

The other two to three were probably loops, indexing or address
calculations, count updates, tests, etc. 

>> ..most would be multibyte, except for the occasional
>>integer. DB stored (as opposed to defined maximum) column lengths
>>change all the time, so there's a lot of shuffling going on, and
>>even conversion, behind the scenes. 
>
>But are all of this data strings?

Not a lot of numeric stuff is stored as binary types in DBs or
used as such in programs nowadays, so they don't need to be
converted: mainly packed or unpacked digit strings, and lots of
arbitrary character strings. 

>>>I'm assuming it's not profitable to design a piece of gear for
>>>this (based on the fact it doesn't exists :-)).
>>
>>It's called a CPU 
>
>Sigh!  YOu don't need a CPU do a dump to and from disk.  You do
>need a CPU to tell the controller where it may dump.

You were talking about a string thing, not I/O. 

>> ..and there's at least a couple of ways of doing
>>it, called CISC (3x0, VAX) and RISC; although both boil down to
>>moving words wherever possible: one in the microcode, the other
>>in an assembler routine. 
>
>Wait a minute.  Moving words isn't all character string modifications.
>Most of the moves that I've seen is address setup..other than
>filling/emptying buffers of disk data.          

Most machines are now word oriented at the core, so shuffling
four bytes to or from a word may involve fetching, modifying,
updating a word four times: better to shuffle the words whenever
possible. 

>Although...now I'm thinking of comm.  In the olden days, when
>people typed characters, I guess those packets would be filled
>bits that might be considered a character string.  But in this
>pointy-click generation that doesn't seem to apply.  What exactly
>gets sent on the wire with a point click these days?  From what
>I see, I've been assuming that the only thing necessary is an
>address of the screen.

Depends on the platform and app: local windows apps would get a
packet with a couple of pixel coordinates and button bits every
few ms from the mouse when it's moving, blast a few bytes to the
screen buffer to update the mouse pointer; remote screen editing
apps would get a packet with a character or two among all the
protocol bytes, and echo similarly: like LAT but worse IIRC;
remote windows apps would get sent multibyte motion packets with
protocol wrappers when things were moving, and send back graphic
screen update packets when things changed; remote command line
apps might get a line every few seconds, and send back a line or
a screed of lines in response. 

Thanks. Take care, Brian Inglis 	Calgary, Alberta, Canada
-- 
Brian.Inglis@CSi.com 	(Brian dot Inglis at SystematicSw dot ab dot ca)
    fake address		use address above to reply
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abuse@ibsystems.com uce@ftc.gov				spam traps

######

Newsgroups: alt.folklore.computers
From: bdc@world.std.com (Brian 'Jarai' Chase)
Subject: Re: Antiquity of Byte-Word addressing?
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In article <b4knar$c26$2@bob.news.rcn.net>,  <jmfbahciv@aol.com> wrote:
> In article <slrnb6r138.r97.shannon@news.widomaker.com>,
>    Charles Shannon Hendrix <shannon@news.widomaker.com> wrote:

> > Move graphics data, numbers, random noise, or War and Peaces... it's
> > all the same to the CPU.
> 
> That's what I'd always assumed :-).  So why did all of that money
> get spend on hardware...or firmware... to do string manipulations?
> The only reason to move a function down to a lower level is 
> performance improvements...or is this another bad assumpion on
> my part?

Never forget that, in the absence of any strong, rational, technical
reasons for a design feature, enhanced marketability is the most likely
cause.  I'm sure that, at some point, someone decided that if they wanted
to target IBM's market with PDP-10s, then they'd need string manipulation
instructions.  No doubt some customers asked for them, too--suffering
from instruction set envy.

My understanding of these sorts of overly complex instructions on the VAX,
and apparently on the PDP-10 based on the discussion in this thread, is
that they actually were generally performance dogs in comparision to their
counterparts implemented in software using standard operations.  The one
real technical benefit I can see is that, in core, using the machine's
string operations saved you some words/bytes of code.  Given the scarcity,
and hence high cost, of memory, this may have been a justified benefit at
the time.

Having run NetBSD on both extremely CISCy and RISCy architectures, the
disparity in the size of the generated object code that's produced from
identical source, between the two ends of that spectrum, is very
significant.

-brian.

######

Newsgroups: alt.folklore.computers
From: Charles Shannon Hendrix <shannon@news.widomaker.com>
Subject: Re: Antiquity of Byte-Word addressing?
References: <5tC5a.1106$TR4.120765@newsread1.prod.itd.earthlink.net> <qhznoau12g.fsf@ruckus.brouhaha.com> <b44ti9$e2g$1@bob.news.rcn.net> <LFw9a.372154$be.342715@rwcrnsc53> <b47a8r$ahj$1@bob.news.rcn.net> <85smu03cpy.fsf@junk.nocrew.org> <b47i5s$oqu$3@bob.news.rcn.net> <1046958603.394263@saucer.planet.gong> <b49ug9$ec$4@bob.news.rcn.net> <1047042594.63477@saucer.planet.gong> <slrnb6j37b.4qp.shannon@news.widomaker.com> <1047129136.16706@saucer.planet.gong> <slrnb6llut.im.shannon@news.widomaker.com> <1047292729.638753@saucer.planet.gong>
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In article <1047292729.638753@saucer.planet.gong>, Rupert Pigott wrote:

> Pretty sure they did actually run it. Oddly it seems to
> be commonly listed as a 16bit machine - did it really
> have a 68K host processor or something ? The T800 was a
> full 32bit microprocessor with no compromises or
> addressing mode BS. They even give you *all* 32 address
> lines too. Again, no multiplexing, no BS. ;)

At that time, it was amazing.

I think it would be nice to have them still, or at least systems set up
that way.

>> > However, when compared to the pile of junk/production
>> > cards I assembled on my desk at INMOS they looked
>> > pretty weak. It was fun building MPPs like Lego. ;)
>>
>> I thought they could use the same stuff?
> 
> Not sure if they used the same kind of connectors for
> external ports (if they had any)... Did those suckers
> use "TRAMS" ?

Not sure.  I thought the transputer had a standard interconnect interface
they had to support, so you could do things like build hypercubes.
In college, we had a transputer hypercude simulator.  Each "node" ran
on a seperate box on the network to simulate their operation.

> IIRC the graphics TRAM I had was called a B419.
> 
> http://www.classiccmp.org/transputer/imsb419.htm
> 
> Those specs don't look right to me. I'm sure the
> VRAM was slower than the DRAM and I have a feeling
> that it used a G332, not a G300. Was nice to code
> for, although it didn't really offer enough raw
> bandwidth to the memory for my taste. I wanted to
> do hi-res stuff :)

Well, when you think about what time period this was...

>> No US sales, but evidently a few went out in the UK, and maybe
>> Europe.
> 
> Looking via google there are estimates of 350 machines
> escaping into the wild. :)

What I never understood is why the transputer project at Atari was killed.
You can't say it was because they were not marketable, because Atari
never really tried.  People wanted them.  I remember a lot of people
were waiting for them in the US.

Atari had a lot of good engineers over the years, who were absolutely
trampled by management.

The Atari ST originall was a better machine than what they released, and
Tramiel would have made MORE money had he not cut so many corners.

######

Newsgroups: alt.folklore.computers
From: Charles Shannon Hendrix <shannon@news.widomaker.com>
Subject: Re: Antiquity of Byte-Word addressing?
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In article <b4knar$c26$2@bob.news.rcn.net>, jmfbahciv@aol.com wrote:

>>It only has meaning to us.
> 
> Yea, I know.  I just figured that a string instruction would
> be some address with some mask with an operation implied in
> the opcode.  It that's not so, then the only other thing
> I could think of would be a software routine that loaded bytes,
> chewed them, then dumped them.

It's going to get more "interesting" with a move from ascii to UTF8.

No more mapping from one character to one memory location.  That
assumption is not valid with UTF8.

It's not just that code will break either.  Things like predicting
file sizes, searching algoriths... all kinds of things change when one
character is no longer in a single memory location.

And no, this is not the same as byte-per-character versus packed
characters in long words.

Even then you could assume a character was a certain number of bits.

> That's what I'd always assumed :-).  So why did all of that money
> get spend on hardware...or firmware... to do string manipulations?

I didn't know there was any.

I have thought about setting my machine up with UTF8 and learn to play
with it.

I really hate seeing it.  I like the fact that ascii fits in 8-bits... :)

However, ascii assumptions are obviously a pain in the ass for a lot of
other people.

>>True, but character data moves is probably second only to graphics
>>data on modern workstations.
> 
> REally? 

Well, actually it depends on what you are running.  Obviously a lot of
graphics work involves heavy math.

But the general stuff... if you have a GUI running, you are going to
be moving and masking bits all day long.  Even when processing text,
it's graphics data moves and manipulation under a GUI.

It's amazing sometimes to think, as I type this posting in vim in a
copy of rxvt (X terminal emulator), how much processing has to be
done for each keystroke. 

I bet most of it is in X, not vim or the tty code.

Maybe someone should try writing a paper which lists the instructions
per keystroke for various software and harware combinations.

For example, typing email in M$ Word versus, rxvt and vi.

> Well, of course.  It was a server.  Moving bits around is its
> primary job!

True, but it's amazing how many people fretted because the SPARC CPU had
lower FPU performance than a competing system (at the time).

It's fun sometimes to disassemble programs, and use something like awk
to generate an instruction histogram.

We need more tools for doing this sort of thing.  I'd like to be able to
(easily) run a program and get a histogram of the instruction set used.
Per function would be nice too.

I played around in the past with some of Sun's tools, and some from DEC.

It was always maddening to do performance analysis on a big UNIX server,
because of the huge variety of programs being run, and how loads can
shift from day to day.  You also generally don't have a disciplined user
base, so there is no real rhyme or reason to how the sytems are loaded
at many shops.

Performance analysis usually starts AFTER things go to hell in a
bucket... :)

######

From: "Rupert Pigott" <roo@dark-try-removing-this-boong.demon.co.uk>
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Thu, 13 Mar 2003 20:31:11 -0000
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"Charles Shannon Hendrix" <shannon@news.widomaker.com> wrote in message
news:slrnb71o5b.9ch.shannon@news.widomaker.com...
> In article <1047292729.638753@saucer.planet.gong>, Rupert Pigott wrote:

[SNIP]

> > IIRC the graphics TRAM I had was called a B419.
> >
> > http://www.classiccmp.org/transputer/imsb419.htm
> >
> > Those specs don't look right to me. I'm sure the
> > VRAM was slower than the DRAM and I have a feeling
> > that it used a G332, not a G300. Was nice to code
> > for, although it didn't really offer enough raw
> > bandwidth to the memory for my taste. I wanted to
> > do hi-res stuff :)
>
> Well, when you think about what time period this was...

Yeah, I know. But it's not the point. :)

Cheers,
Rupert

######

Newsgroups: alt.folklore.computers
From: Charles Shannon Hendrix <shannon@news.widomaker.com>
Subject: Re: Antiquity of Byte-Word addressing?
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In article <83d1k-rl9.ln1@pez.jarai.com>, Brian 'Jarai' Chase wrote:

> Having run NetBSD on both extremely CISCy and RISCy architectures, the
> disparity in the size of the generated object code that's produced from
> identical source, between the two ends of that spectrum, is very
> significant.

Really?  I find that my Sun SS5 (SPARC v8 CPU) has programs not much
larger than my x86 Linux machine, using the GNU compilers.

I know in some cases I have seen a lot of disparity, but then sometimes
I've found Intel code to get quite large.

The Alpha sometimes proceduced really large binaries, but I no longer
have a machine to check again.

######

From: Pete Fenelon <pete@fenelon.com>
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
Date: Thu, 13 Mar 2003 21:17:37 -0000
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Charles Shannon Hendrix <shannon@news.widomaker.com> wrote:
> 
> Really?  I find that my Sun SS5 (SPARC v8 CPU) has programs not much
> larger than my x86 Linux machine, using the GNU compilers.

Certainly they seem to be within a binary order of magnitude for most
things, although I must admit that often on my x86 boxes I'm willing
to trade more space for faster execution time (disc and memory are
cheap and my own x86 boxes are generally single-user) so I tend to
use Intel's own compiler where possible and let it unroll loops and
do all kinds of time-optimisations. This brings some of my Intel
sizes closer to Sparc ones. ;) (hell, it's a change from the part
of my job that involves trying to save bytes on tiny micros ;))

> The Alpha sometimes proceduced really large binaries, but I no longer
> have a machine to check again.

From my fairly limited memory of compiling for Alpha (mostly of
evaluating it against RS6k and Sparc boxes), naive codegen strategies
and poor register-colouring and dataflow analysis could lead to a
lot of no-ops and suchlike because of the pipelining.

Cleverer instruction schedulers (the Haifa scheduler comes to mind)
know more about the pipeline and can keep it fed more efficiently - so
less NOPs 

pete
-- 
pete@fenelon.com "there's no room for enigmas in built-up areas" HMHB

######

Newsgroups: alt.folklore.computers
From: bdc@world.std.com (Brian 'Jarai' Chase)
Subject: Re: Antiquity of Byte-Word addressing?
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In article <slrnb71r99.9ch.shannon@news.widomaker.com>,
Charles Shannon Hendrix  <cshNOSPAM@NOSPAM.widomaker.com> wrote:
> In article <83d1k-rl9.ln1@pez.jarai.com>, Brian 'Jarai' Chase wrote:

> > Having run NetBSD on both extremely CISCy and RISCy architectures, the
> > disparity in the size of the generated object code that's produced from
> > identical source, between the two ends of that spectrum, is very
> > significant.
> 
> Really?  I find that my Sun SS5 (SPARC v8 CPU) has programs not much
> larger than my x86 Linux machine, using the GNU compilers.

Admittedly, my perspective is from the VAX binaries.  To provide a quick,
dirty, and not entirely scientific example, I unpacked and totalled the
sizes of the files in /usr/bin for the vax, sparc, pmax (MIPS), alpha,
and i386 releases of NetBSD 1.6:

NetBSD Port	/usr/bin size
-------------	--------------
NetBSD/vax	 9560473 bytes
NetBSD/i386	10615397 bytes
NetBSD/sparc	11885389 bytes
NetBSD/alpha	16301277 bytes
NetBSD/pmax	18143085 bytes

The SPARC code is a lot smaller than I'd have expected.  Still, you can
see the difference between the very CISCy VAX and i386 vs the very RISCy
Alpha and MIPS processors. 

-brian.

######

From: "Rupert Pigott" <roo@dark-try-removing-this-boong.demon.co.uk>
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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"Brian 'Jarai' Chase" <bdc@world.std.com> wrote in message
news:3aa8k-kld.ln1@pez.jarai.com...

[SNIP]

> The SPARC code is a lot smaller than I'd have expected.  Still, you can
> see the difference between the very CISCy VAX and i386 vs the very RISCy
> Alpha and MIPS processors.

INMOS carried out a comparison of binary sizes based on
a full-screen editor called "F" (which I loved and have
not been able to track down since...).

IIRC the Transputer beat the iAPX86 and was around about
30% smaller than the SPARC binary. I was surprised by
the SPARC's size too.

The problem is that you're comparing compilers to a large
extent.

Cheers,
Rupert

######

From: bfranchuk@jetnet.ab.ca
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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Rupert Pigott wrote:

> The problem is that you're comparing compilers to a large
> extent.


Lets not forget nowdays every thing has the stupid dynamic
libraries so you really don't know the size of your code
anyway. What every happended to benchmarks for comparing
speed and size and good code generation?
Ben.

######

From: "Rupert Pigott" <roo@dark-try-removing-this-boong.demon.co.uk>
Newsgroups: alt.folklore.computers
Subject: Re: Antiquity of Byte-Word addressing?
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<bfranchuk@jetnet.ab.ca> wrote in message
news:3E721ACC.2030205@jetnet.ab.ca...
> Rupert Pigott wrote:
>
> > The problem is that you're comparing compilers to a large
> > extent.
>
>
> Lets not forget nowdays every thing has the stupid dynamic
> libraries so you really don't know the size of your code
> anyway. What every happended to benchmarks for comparing
> speed and size and good code generation?
> Ben.

That's why you statically link & strip the binaries. ;)

Marketing don't like that, it stinks of ironing out
the playing field. :)

Cheers,
Rupert

######

Newsgroups: alt.folklore.computers
From: bdc@world.std.com (Brian 'Jarai' Chase)
Subject: Re: Antiquity of Byte-Word addressing?
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In article <3E721ACC.2030205@jetnet.ab.ca>,  <bfranchuk@jetnet.ab.ca> wrote:
> Rupert Pigott wrote:

> > The problem is that you're comparing compilers to a large
> > extent.
> 
> Lets not forget nowdays every thing has the stupid dynamic
> libraries so you really don't know the size of your code
> anyway. What every happended to benchmarks for comparing
> speed and size and good code generation?

Well, one of the reasons for choosing NetBSD for the comparision is that
a) the compiler used is the same version of GCC across all the platforms,
so at least the machine independent parts of the compiler are identical,
and b) the comparison of sizes of dynamically linked binaries is still
relevant because all of the non-dynamically linked bits of code contained
within those binaries are based on the same source.

Given the nature of RISC architectures, with their smaller number of
instructions, simpler instructions, and data alignment requirements, one
would expect the resulting binaries to be somewhat bigger than those of
CISC architectures.  Likewise you'd expect them to take up more memory
when running.  Empirical evidence, in the context of the code generated
by GCC under NetBSD, seems to confirm that this is what happens.

Now, if someone wants to assert that the code generated for RISC 
architectures is generally equivalent in size or smaller than that 
generated for CISC architectures, I'd definitely find evidence 
illustrating such findings to be educational, as it goes against 
what I'd expect.

-brian.

######

Newsgroups: alt.folklore.computers
From: Charles Shannon Hendrix <shannon@news.widomaker.com>
Subject: Re: Antiquity of Byte-Word addressing?
References: <5tC5a.1106$TR4.120765@newsread1.prod.itd.earthlink.net> <qhznoau12g.fsf@ruckus.brouhaha.com> <b44ti9$e2g$1@bob.news.rcn.net> <LFw9a.372154$be.342715@rwcrnsc53> <b47a8r$ahj$1@bob.news.rcn.net> <85smu03cpy.fsf@junk.nocrew.org> <b47i5s$oqu$3@bob.news.rcn.net> <1046958603.394263@saucer.planet.gong> <b49ug9$ec$4@bob.news.rcn.net> <1047042594.63477@saucer.planet.gong> <slrnb6j37b.4qp.shannon@news.widomaker.com> <1047129136.16706@saucer.planet.gong> <slrnb6llut.im.shannon@news.widomaker.com> <1047292729.638753@saucer.planet.gong> <slrnb71o5b.9ch.shannon@news.widomaker.com> <1047590284.342512@saucer.planet.gong>
Organization: Big Endian
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Xref: chonsp.franklin.ch alt.folklore.computers:132234

In article <1047590284.342512@saucer.planet.gong>, Rupert Pigott wrote:
> "Charles Shannon Hendrix" <shannon@news.widomaker.com> wrote in message
> news:slrnb71o5b.9ch.shannon@news.widomaker.com...
>> In article <1047292729.638753@saucer.planet.gong>, Rupert Pigott wrote:
> 
> [SNIP]
> 
>> > IIRC the graphics TRAM I had was called a B419.
>> >
>> > http://www.classiccmp.org/transputer/imsb419.htm
>> >
>> > Those specs don't look right to me. I'm sure the
>> > VRAM was slower than the DRAM and I have a feeling
>> > that it used a G332, not a G300. Was nice to code
>> > for, although it didn't really offer enough raw
>> > bandwidth to the memory for my taste. I wanted to
>> > do hi-res stuff :)
>>
>> Well, when you think about what time period this was...
> 
> Yeah, I know. But it's not the point. :)

BTW, if you are interested in Occam:

http://www.cs.ukc.ac.uk/projects/ofa/kro/ 

This runs on non transputers.

######

Newsgroups: alt.folklore.computers
From: Charles Shannon Hendrix <shannon@news.widomaker.com>
Subject: Re: Antiquity of Byte-Word addressing?
References: <1046958603.394263@saucer.planet.gong> <b4hutt$9u2$1@bob.news.rcn.net> <slrnb6r138.r97.shannon@news.widomaker.com> <b4knar$c26$2@bob.news.rcn.net> <83d1k-rl9.ln1@pez.jarai.com> <slrnb71r99.9ch.shannon@news.widomaker.com> <v71tbhpm08ikd2@corp.supernews.com>
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Xref: chonsp.franklin.ch alt.folklore.computers:132243

In article <v71tbhpm08ikd2@corp.supernews.com>, Pete Fenelon wrote:
> Charles Shannon Hendrix <shannon@news.widomaker.com> wrote:
>> 
>> Really?  I find that my Sun SS5 (SPARC v8 CPU) has programs not much
>> larger than my x86 Linux machine, using the GNU compilers.
> 
> Certainly they seem to be within a binary order of magnitude for most
> things, although I must admit that often on my x86 boxes I'm willing

Which machines specifically do you observe this on?

My systems are SPARC and AMD-x86 systems.  Plenty of the binaries on
the AMD side are larger.  It's worth nothing too that the GNU compiler
I use for each platform is far more mature for x86.

I get about a 50% increase in code size, sometimes.  For example:

program		SPARC	    x86

mutt		544440	    475924
vim		866368	    1195483
gzip		207484	    51040	    (this is a v7 sparc build)

The latter program is a v7 build, which means no FPU instructions.
It can be built smaller I believe.

Each program is my own compile with the same features and as optimized
as I could do quickly.

So you see, in some cases RISC is actually smaller.

> From my fairly limited memory of compiling for Alpha (mostly of
> evaluating it against RS6k and Sparc boxes), naive codegen strategies
> and poor register-colouring and dataflow analysis could lead to a
> lot of no-ops and suchlike because of the pipelining.

I thought DEC's compilers were supposed to be the better ones.

I know that they often seemed to do far better than GNU C.

> Cleverer instruction schedulers (the Haifa scheduler comes to mind)
> know more about the pipeline and can keep it fed more efficiently - so
> less NOPs 

Isn't that what you get if you get a compiler with, say, Tru64 these
days?

######

Newsgroups: alt.folklore.computers
From: Charles Shannon Hendrix <shannon@news.widomaker.com>
Subject: Re: Antiquity of Byte-Word addressing?
References: <1046958603.394263@saucer.planet.gong> <b4knar$c26$2@bob.news.rcn.net> <83d1k-rl9.ln1@pez.jarai.com> <slrnb71r99.9ch.shannon@news.widomaker.com> <3aa8k-kld.ln1@pez.jarai.com>
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Xref: chonsp.franklin.ch alt.folklore.computers:132235

In article <3aa8k-kld.ln1@pez.jarai.com>, Brian 'Jarai' Chase wrote:

>> Really?  I find that my Sun SS5 (SPARC v8 CPU) has programs not much
>> larger than my x86 Linux machine, using the GNU compilers.
> 
> Admittedly, my perspective is from the VAX binaries.  To provide a quick,
> dirty, and not entirely scientific example, I unpacked and totalled the
> sizes of the files in /usr/bin for the vax, sparc, pmax (MIPS), alpha,
> and i386 releases of NetBSD 1.6:
> 
> NetBSD Port	/usr/bin size
> -------------	--------------
> NetBSD/vax	 9560473 bytes
> NetBSD/i386	10615397 bytes
> NetBSD/sparc	11885389 bytes
> NetBSD/alpha	16301277 bytes
> NetBSD/pmax	18143085 bytes
> 
> The SPARC code is a lot smaller than I'd have expected.  Still, you can
> see the difference between the very CISCy VAX and i386 vs the very RISCy
> Alpha and MIPS processors. 

I expected Alpha and MIPS to be larger.

However, I suspect that a lot of it is the compiler not being very good
in comparison to GNU for SPARC and x86.

It's too bad we have compiler variation, since it makes it harder to
compare things.

Things may have improved in the Alpha and MIPS GNU backends.  I haven't
used Alpha in years now.

######

Newsgroups: alt.folklore.computers
From: Charles Shannon Hendrix <shannon@news.widomaker.com>
Subject: Re: Antiquity of Byte-Word addressing?
References: <1046958603.394263@saucer.planet.gong> <b4knar$c26$2@bob.news.rcn.net> <83d1k-rl9.ln1@pez.jarai.com> <slrnb71r99.9ch.shannon@news.widomaker.com> <3aa8k-kld.ln1@pez.jarai.com> <1047632218.156371@saucer.planet.gong> <3E721ACC.2030205@jetnet.ab.ca>
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Xref: chonsp.franklin.ch alt.folklore.computers:132233

In article <3E721ACC.2030205@jetnet.ab.ca>, bfranchuk@jetnet.ab.ca wrote:
> Rupert Pigott wrote:
> 
>> The problem is that you're comparing compilers to a large
>> extent.
> 
> 
> Lets not forget nowdays every thing has the stupid dynamic
> libraries so you really don't know the size of your code
> anyway. What every happended to benchmarks for comparing
> speed and size and good code generation?

No one cares, CPU and memory is free now, or so goes the mantra.

I try to tell people that it *does* matter, but they don't care.

Then when their powerful systems still get bogged down, they have no
real idea why.  Further, the things they do to "fix" things now looks
more like a voodoo ritual than any kind of applied science I know about.

When I compare binaries, I try to build static, or make sure each
platform uses libraries the same way.

######

Newsgroups: alt.folklore.computers
From: Charles Shannon Hendrix <shannon@news.widomaker.com>
Subject: Re: Antiquity of Byte-Word addressing?
References: <1046958603.394263@saucer.planet.gong> <3aa8k-kld.ln1@pez.jarai.com> <1047632218.156371@saucer.planet.gong> <3E721ACC.2030205@jetnet.ab.ca> <cuoak-jdf.ln1@pez.jarai.com>
Organization: Big Endian
Reply-To: cshNOSPAM@NOSPAM.widomaker.com
Message-ID: <slrnb76oi9.1lg.shannon@news.widomaker.com>
User-Agent: slrn/0.9.7.4 (Linux)
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Date: Sat, 15 Mar 2003 12:26:33 -0500
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Xref: chonsp.franklin.ch alt.folklore.computers:132241

In article <cuoak-jdf.ln1@pez.jarai.com>, Brian 'Jarai' Chase wrote:

> Well, one of the reasons for choosing NetBSD for the comparision is that
> a) the compiler used is the same version of GCC across all the platforms,

But definitely not the same level of quality.

> Given the nature of RISC architectures, with their smaller number of
> instructions, simpler instructions, and data alignment requirements, one
> would expect the resulting binaries to be somewhat bigger than those of
> CISC architectures.  Likewise you'd expect them to take up more memory

So would I, but I've not noted it to be as drastic as some people
think.

On MIPS, binaries are huge, even with SGI's compilers.

Also, its sometimes hard to tell if a CPU is RISC or CISC.  The
Athlon has a RISC core, and a lot of x86 instrictions are RISC-like.

Further, there are some very complex ISAs in RISC CPUs, and some
definitely CISC-like instructions.

It's clear that the original definitions of RISC and CISC have been
blurred a bit.