Message-ID: <3D743E47.4A05925@jps.net> From: Conrad Field X-Mailer: Mozilla 4.75 [en] (Win95; U) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch,alt.folklore.computers Subject: What was the size of Microcode in various machines References: <3D6EA8D1.1CE008B7@cisco.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 66 Date: Tue, 03 Sep 2002 04:46:48 GMT NNTP-Posting-Host: 165.247.225.75 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 1031028408 165.247.225.75 (Mon, 02 Sep 2002 21:46:48 PDT) NNTP-Posting-Date: Mon, 02 Sep 2002 21:46:48 PDT Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.news2me.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:115894 Hans Vlems wrote: > > Microcode is what the finite state machine, as implemented in cicrcuitry, > actually executes. Assembly language has nothing to do with hardware, it is > just one way of writing programs. This has not always been that way. The > first PDP-11, the 11/20 had no microcode (this is called a "hardcoded > cpu"?). An assembly language instruction was translated by the assembler to > a bit pattern and that bit patterns was indeed fed to the hardware. It was > quite difficult to design and build families of systems that way, which is > why IBM came up with the 360 series, one of the first, if not the first, > machines that relied on microcode. The PDP 11/40 had microcode words of more > than 100 bits. The cpu architecture was 16 bits. A special microcode console > was plugged into one of the processor boards and it allowed an engineer to > figure out where the machine was faulty. I have worked on a large variety of machines and have always wonder about the size of mircocode words and the number of excutions per memory cycle on the fortunate machines that I did not touch... The largest microcoded machine in word size was the Sperry 90/60 with an 64 bit fetch microcode and a 124 excution code that ran concurrently at 2 cycle per main memory. Honeywell byte proccessor of just 16 bits for an IBM style instruction emulation. Of course that is what Sperry RCA, GE, Honewell had in mind in order to keep instep for a every change that IBM made to their machines. The Peripheral controllers also had there mirco codes interpreting the I/O commands sent from the processors. STC tape controllers IIRC were 16 bits, ISS disk controllers were 64 bits, things are starting to get fussy again, folks. Now the bigger the microcode doesn't always mean a better machine, sometime a balance is struck with the right amount of hardwire fuctions versus microcode flexibility creates a very efficient machine, one being the last RCA designed processor, the 90/80, with a 32 bit microcode. SO guys, get your memories a goin' and give me the low down on some microcoded driven boxes of yesteryear. > > In general microcode is hidden for the customer. Exceptions were the B1700 > and the 11/780. The B1700 came with tools that allowed the customer to > define a custom instruction set. For the 11/780 an extension kit was > available. Customers could write their own specific instructions. Not sure > that many did since the VAX instruction set was quite rich. > > Hans > > "Rupert Pigott" schreef in bericht > news:ako7mn$jrd$1@newsg4.svr.pol.co.uk... > > "Eric Chomko" wrote in message > > news:ako6g5$v5m$1@news.ums.edu... > > > J Ahlstrom (jahlstro@cisco.com) wrote: > > > : Brian Nichols wrote: > > > > [SNIP] > > -- Conrad Field ****************************************************** http://www.rummageads.com http://www.rummageads.com/rummage/ http://www.rummageads.com/audioads/ http://www.rummageads.com/audiojunkyard/ http://www.rummageads.com/audiojunkyard/wish.htm ****************************************************** ###### From: Lars Brinkhoff Newsgroups: comp.arch,alt.folklore.computers Subject: Re: What was the size of Microcode in various machines Date: 03 Sep 2002 07:57:05 +0200 Organization: nocrew Lines: 17 Sender: lars@junk.nocrew.org Message-ID: <85wuq3r4y6.fsf@junk.nocrew.org> References: <3D6EA8D1.1CE008B7@cisco.com> <3D743E47.4A05925@jps.net> NNTP-Posting-Host: junk.nocrew.org (213.242.147.30) Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: fu-berlin.de 1031032822 57279575 213.242.147.30 (16 [140306]) X-Orig-Path: junk.nocrew.org!not-for-mail User-Agent: Gnus/5.0808 (Gnus v5.8.8) Emacs/20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!fu-berlin.de!uni-berlin.de!junk.nocrew.ORG!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:115867 Conrad Field writes: > SO guys, get your memories a goin' and give me the low down on some > microcoded driven boxes of yesteryear. I'm not sure, but these may be the microcode widths and sizes of some PDP-10 processors: DEC KL10 model A 96 bits x 1280 words DEC KL10 model B 96 bits x 2K words DEC KS10 96 bits x 2K words Xerox MAXC 72 bits x 1K or 2K words Foonly F-1 120 bits Systems Concepts SC-40 80 bits x 32K words -- Lars Brinkhoff http://lars.nocrew.org/ Linux, GCC, PDP-10, Brinkhoff Consulting http://www.brinkhoff.se/ HTTP programming ###### From: "Stephen Fuld" Newsgroups: comp.arch,alt.folklore.computers References: <3D6EA8D1.1CE008B7@cisco.com> <3D743E47.4A05925@jps.net> Subject: Re: What was the size of Microcode in various machines Lines: 39 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Message-ID: Date: Tue, 03 Sep 2002 17:16:07 GMT NNTP-Posting-Host: 32.101.177.213 X-Complaints-To: abuse@worldnet.att.net X-Trace: bgtnsc05-news.ops.worldnet.att.net 1031073367 32.101.177.213 (Tue, 03 Sep 2002 17:16:07 GMT) NNTP-Posting-Date: Tue, 03 Sep 2002 17:16:07 GMT Organization: AT&T Worldnet Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!news.maxwell.syr.edu!wn1feed!worldnet.att.net!bgtnsc05-news.ops.worldnet.att.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:115855 "Conrad Field" wrote in message news:3D743E47.4A05925@jps.net... > I have worked on a large variety of machines and have always wonder > about the size of mircocode words and the number of excutions per memory > cycle on the fortunate machines that I did not touch... > The largest microcoded machine in word size was the Sperry 90/60 with > an 64 bit fetch microcode and a 124 excution code that ran concurrently > at 2 cycle per main memory. Honeywell byte proccessor of just 16 bits > for an IBM style instruction emulation. Of course that is what Sperry > RCA, GE, Honewell had in mind in order to keep instep for a every > change that IBM made to their machines. > The Peripheral controllers also had there mirco codes interpreting > the I/O commands sent from the processors. STC tape controllers IIRC > were 16 bits, ISS disk controllers were 64 bits, things are starting > to get fussy again, folks. > Now the bigger the microcode doesn't always mean a better machine, > sometime a balance is struck with the right amount of hardwire fuctions > versus microcode flexibility creates a very efficient machine, one being > the last RCA designed processor, the 90/80, with a 32 bit microcode. > SO guys, get your memories a goin' and give me the low down on some > microcoded driven boxes of yesteryear. A disk controller I worked on in the 1980s (for mainframe systems) had a 40 bit word and executed each instruction in one 200 ns memory cycle. Each word was divided into two parts of 20 bits each. The first part controlled the (2901 bit sliced) ALU and reads and writes to external hardware reagisters within the box. The last 20 bits had the micro sequencer control field and an "immediate" field whic could be used as a jump target or the immediate value for a load or external register write type instruction. The system started out with 3K words of control store, but as we added functionality (particularly caching) it grew up to 12K words. -- - Stephen Fuld e-mail address disguised to prevent spam ###### From: jdallen2000@yahoo.com (James Dow Allen) Newsgroups: comp.arch,alt.folklore.computers Subject: Re: What was the size of Microcode in various machines Date: 3 Sep 2002 23:38:24 -0700 Organization: http://groups.google.com/ Lines: 22 Message-ID: <266426e1.0209032238.777e970e@posting.google.com> References: <3D6EA8D1.1CE008B7@cisco.com> <3D743E47.4A05925@jps.net> NNTP-Posting-Host: 202.183.179.136 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1031121504 12623 127.0.0.1 (4 Sep 2002 06:38:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 4 Sep 2002 06:38:24 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:115970 Conrad Field wrote in message news:<3D743E47.4A05925@jps.net>... > I have worked on a large variety of machines and have always wonder > about the size of mircocode words and the number of excutions per memory > cycle on the fortunate machines that I did not touch... IBM Mainframes of early to mid 1970's: Model microinst. width nanosec per microinst 370/135 & 370/138 16 (+2P) min. 275 max 935?? 370/145 & 370/148 32 (+4P) min. 202.5 max 585?? 370/155 & 370/158 72 (incl. P) 115 370/165, 370/168 & 370/3032 108(?) ** 80 370/3033 108(?) ** 57 For the 370/165 etc., the microinst was an extra 12(?) bits wider in the section used for 14xx emulation. ("108", "12", "14xx" are all from distant memory recesses, and might be off.) The 370/3031 was essentially two 158's hooked together, stripped down in opposite ways. James ###### From: Lars Brinkhoff Newsgroups: comp.arch,alt.folklore.computers,alt.sys.pdp10 Subject: Re: What was the size of Microcode in various machines Date: 04 Sep 2002 09:17:51 +0200 Organization: nocrew Lines: 54 Sender: lars@junk.nocrew.org Message-ID: <853csqql40.fsf@junk.nocrew.org> References: <3D6EA8D1.1CE008B7@cisco.com> <3D743E47.4A05925@jps.net> <85wuq3r4y6.fsf@junk.nocrew.org> NNTP-Posting-Host: junk.nocrew.org (213.242.147.30) Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: fu-berlin.de 1031124016 58179901 213.242.147.30 (16 [140306]) X-Orig-Path: junk.nocrew.org!not-for-mail User-Agent: Gnus/5.0808 (Gnus v5.8.8) Emacs/20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!feedme.news.mediaways.net!fu-berlin.de!uni-berlin.de!junk.nocrew.ORG!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:115955 alt.sys.pdp10:11819 [Now also cross-posted to alt.sys.pdp10.] Eric Smith writes: > Lars Brinkhoff writes: > > I'm not sure, but these may be the microcode widths and sizes of some > > PDP-10 processors: > > > > DEC KL10 model A 96 bits x 1280 words > > DEC KL10 model B 96 bits x 2K words > > Really only about 80 bits per microword, as not all of the bits are > actually implemented in the hardware. The microassembler produces > 96-bit words, but the extra bits get dropped on the floor when > loaded into the hardware. Thanks for the info. > The KL10 "model A" described in the System Reference Manual refers > to the KL10-PA Arithmetic Processor, and the "model B" refers to the > KL10-PV. Or the KL10-PW, right? > Note that these are used in various models with a single letter > suffix, so a KL10-B is actually a "model A" (unless field upgraded). > > There was reportedly a cancelled KL10 model that would have expanded > the control store to 4K words. This would have been nice as the > KL10-PV microcode was at the size limit and features were getting > removed to make room for bug fixes. > > > DEC KS10 96 bits x 2K words > > The microsequencer has 12-bit addresses, and the branch field in the > microword is 12 bits wide, so in principle the KS10 microstore could > be expanded to 4K words. However, DEC had a hard time squeezing > even the 2K words into the space available using the SRAM chips they > could get in 1977. And they had a lot of problems with those SRAM > chips, leading to a patented technique where a control store parity > error would cause the front-end processor to initiate an on-the-fly > microcode reload. But the 96-bit width is correct, then? I restore these lines from my original message in case anyone on alt.sys.pdp10 has any comments: > > Xerox MAXC 72 bits x 1K or 2K words > > Foonly F-1 120 bits? > > Systems Concepts 80 bits x 32K words -- Lars Brinkhoff http://lars.nocrew.org/ Linux, GCC, PDP-10, Brinkhoff Consulting http://www.brinkhoff.se/ HTTP programming ###### From: Lars Brinkhoff Newsgroups: comp.arch,alt.folklore.computers,alt.sys.pdp10 Subject: Re: What was the size of Microcode in various machines Followup-To: alt.sys.pdp10 Date: 05 Sep 2002 06:30:25 +0200 Organization: nocrew Lines: 16 Sender: lars@junk.nocrew.org Message-ID: <85lm6hoy72.fsf@junk.nocrew.org> References: <3D6EA8D1.1CE008B7@cisco.com> <3D743E47.4A05925@jps.net> <85wuq3r4y6.fsf@junk.nocrew.org> <853csqql40.fsf@junk.nocrew.org> NNTP-Posting-Host: junk.nocrew.org (213.242.147.30) Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: fu-berlin.de 1031200542 58830152 213.242.147.30 (16 [140306]) X-Orig-Path: junk.nocrew.org!not-for-mail User-Agent: Gnus/5.0808 (Gnus v5.8.8) Emacs/20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.fjserv.net!opentransit.net!fu-berlin.de!uni-berlin.de!junk.nocrew.ORG!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:116024 alt.sys.pdp10:11821 Eric Smith writes: > The KL10-PW is functionally very nearly the same as the KL10-PV, so most > of the "model B" docs apply. There are some details that are changed, > though, and they aren't documented in the System Reference Manual. :-( These are some differences according to Joe Smith: KL10-PV KL10-PW Year announced 1978? 1984? Words of cache 2048 4096 Page table entries 512 1024 Runs TOPS-10 7.03/7.04 Maybe Yes -- Lars Brinkhoff http://lars.nocrew.org/ Linux, GCC, PDP-10, Brinkhoff Consulting http://www.brinkhoff.se/ HTTP programming ###### Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: alt.sys.pdp10 Subject: Re: What was the size of Microcode in various machines References: <3D6EA8D1.1CE008B7@cisco.com> <3D743E47.4A05925@jps.net> <85wuq3r4y6.fsf@junk.nocrew.org> <853csqql40.fsf@junk.nocrew.org> <85lm6hoy72.fsf@junk.nocrew.org> Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 05 Sep 2002 00:17:02 -0700 Message-ID: Lines: 21 User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: 209.66.107.17 X-Trace: 5 Sep 2002 00:41:45 -0700, 209.66.107.17 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!feedme.news.mediaways.net!priapus.visi.com!news-out.visi.com!green.readfreenews.net!news.readfreenews.net!triton.net!smallfeed.triton.net!nntp1.hal-pc.org!204.94.211.44.MISMATCH!enews.sgi.com!news.spies.com!209.66.107.17 Xref: chonsp.franklin.ch alt.sys.pdp10:11826 Eric Smith writes: > The KL10-PW is functionally very nearly the same as the KL10-PV, so most > of the "model B" docs apply. There are some details that are changed, > though, and they aren't documented in the System Reference Manual. :-( Lars Brinkhoff writes: > These are some differences according to Joe Smith: > > KL10-PV KL10-PW > Year announced 1978? 1984? > Words of cache 2048 4096 > Page table entries 512 1024 > Runs TOPS-10 7.03/7.04 Maybe Yes Yes, that's well known. What I was referring to, which is much less widely known, is that there are some changes to bits in registers and such that a system programmer may need to know about, and DEC never updated the System Reference Manual to reflect these changes. :-( I was very surprised when I found the relevant information in another manual. When I spot that manual again, I'll get it scanned. ###### From: Lars Brinkhoff Newsgroups: alt.sys.pdp10 Subject: Re: What was the size of Microcode in various machines Date: 05 Sep 2002 09:28:12 +0200 Organization: nocrew Lines: 14 Sender: lars@junk.nocrew.org Message-ID: <85d6rsq4j7.fsf@junk.nocrew.org> References: <3D6EA8D1.1CE008B7@cisco.com> <3D743E47.4A05925@jps.net> <85wuq3r4y6.fsf@junk.nocrew.org> <853csqql40.fsf@junk.nocrew.org> <85lm6hoy72.fsf@junk.nocrew.org> NNTP-Posting-Host: junk.nocrew.org (213.242.147.30) Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: fu-berlin.de 1031211028 58002456 213.242.147.30 (16 [140306]) X-Orig-Path: junk.nocrew.org!not-for-mail User-Agent: Gnus/5.0808 (Gnus v5.8.8) Emacs/20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!feedme.news.mediaways.net!fu-berlin.de!uni-berlin.de!junk.nocrew.ORG!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:11820 Eric Smith writes: > Yes, that's well known. What I was referring to, which is much less > widely known, is that there are some changes to bits in registers and > such that a system programmer may need to know about, and DEC never > updated the System Reference Manual to reflect these changes. :-( > > I was very surprised when I found the relevant information in another > manual. When I spot that manual again, I'll get it scanned. Great, that would be interesting. -- Lars Brinkhoff http://lars.nocrew.org/ Linux, GCC, PDP-10, Brinkhoff Consulting http://www.brinkhoff.se/ HTTP programming ###### From: Paul Repacholi Newsgroups: alt.sys.pdp10 Subject: Re: What was the size of Microcode in various machines Date: 05 Sep 2002 19:55:27 +0800 Organization: iQnet Lines: 27 Sender: prep@k9 Message-ID: <8765xkslao.fsf@prep.synonet.com> References: <3D6EA8D1.1CE008B7@cisco.com> <3D743E47.4A05925@jps.net> <85wuq3r4y6.fsf@junk.nocrew.org> <853csqql40.fsf@junk.nocrew.org> <85lm6hoy72.fsf@junk.nocrew.org> NNTP-Posting-Host: news-01.core.usertools.net Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: nnrp.waia.asn.au 1031235822 24857 202.154.80.9 (5 Sep 2002 14:23:42 GMT) X-Complaints-To: usenet@nnrp.waia.asn.au NNTP-Posting-Date: Thu, 5 Sep 2002 14:23:42 +0000 (UTC) User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.2 Cache-Post-Path: angelina!unknown@p007.qv1-01.dial.usertools.net X-Cache: nntpcache 2.3.3 (see http://www.nntpcache.org/) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!feedme.news.mediaways.net!newsfeed.iinet.net.au!nntp.waia.asn.au!nnrp.waia.asn.au!127.0.0.1!nobody Xref: chonsp.franklin.ch alt.sys.pdp10:11824 Lars Brinkhoff writes: > Eric Smith writes: > > The KL10-PW is functionally very nearly the same as the KL10-PV, > > so most of the "model B" docs apply. There are some details that > > are changed, though, and they aren't documented in the System > > Reference Manual. :-( > These are some differences according to Joe Smith: > KL10-PV KL10-PW > Year announced 1978? 1984? That is the CPU of the KL10-RE? If so, then it was known about during the Fall 83 DECUS. > Words of cache 2048 4096 > Page table entries 512 1024 > Runs TOPS-10 7.03/7.04 Maybe Yes -- Paul Repacholi 1 Crescent Rd., +61 (08) 9257-1001 Kalamunda. West Australia 6076 Raw, Cooked or Well-done, it's all half baked. EPIC, The Architecture of the future, always has been, always will be. ###### From: Lars Brinkhoff Newsgroups: alt.sys.pdp10 Subject: Re: What was the size of Microcode in various machines Date: 05 Sep 2002 17:03:35 +0200 Organization: nocrew Lines: 14 Sender: lars@junk.nocrew.org Message-ID: <85r8g8o4vs.fsf@junk.nocrew.org> References: <3D6EA8D1.1CE008B7@cisco.com> <3D743E47.4A05925@jps.net> <85wuq3r4y6.fsf@junk.nocrew.org> <853csqql40.fsf@junk.nocrew.org> <85lm6hoy72.fsf@junk.nocrew.org> <8765xkslao.fsf@prep.synonet.com> NNTP-Posting-Host: junk.nocrew.org (213.242.147.30) Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: fu-berlin.de 1031238314 59140073 213.242.147.30 (16 [140306]) X-Orig-Path: junk.nocrew.org!not-for-mail User-Agent: Gnus/5.0808 (Gnus v5.8.8) Emacs/20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!fu-berlin.de!uni-berlin.de!junk.nocrew.ORG!not-for-mail Xref: chonsp.franklin.ch alt.sys.pdp10:11822 Paul Repacholi writes: > > KL10-PV KL10-PW > > Year announced 1978? 1984? > > That is the CPU of the KL10-RE? If so, then it was known about during > the Fall 83 DECUS. According to some info on http://www.inwap.com/pdp10/models.txt, KL10-PW was the CPU of KL10-E+ and KL10-R+. KL10-E and KL10-R had KL10-PV. Other info says KL10-R had KL10-PW. -- Lars Brinkhoff http://lars.nocrew.org/ Linux, GCC, PDP-10, Brinkhoff Consulting http://www.brinkhoff.se/ HTTP programming ###### From: Lars Brinkhoff Newsgroups: comp.arch,alt.folklore.computers Subject: Re: What was the size of Microcode in various machines Date: 05 Sep 2002 21:57:02 +0200 Organization: nocrew Lines: 10 Sender: lars@junk.nocrew.org Message-ID: <85n0qwmcq9.fsf@junk.nocrew.org> References: <3D6EA8D1.1CE008B7@cisco.com> <3D743E47.4A05925@jps.net> NNTP-Posting-Host: junk.nocrew.org (213.242.147.30) Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: fu-berlin.de 1031256032 58611517 213.242.147.30 (16 [140306]) X-Orig-Path: junk.nocrew.org!not-for-mail User-Agent: Gnus/5.0808 (Gnus v5.8.8) Emacs/20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!fu-berlin.de!uni-berlin.de!junk.nocrew.ORG!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:116082 Conrad Field writes: > The largest microcoded machine in word size was the Sperry 90/60 with > an 64 bit fetch microcode and a 124 excution code that ran concurrently > at 2 cycle per main memory. The XKL-1 processor has 128-bit microcode. -- Lars Brinkhoff http://lars.nocrew.org/ Linux, GCC, PDP-10, Brinkhoff Consulting http://www.brinkhoff.se/ HTTP programming ###### Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: alt.sys.pdp10 Subject: Re: What was the size of Microcode in various machines References: <3D6EA8D1.1CE008B7@cisco.com> <3D743E47.4A05925@jps.net> <85wuq3r4y6.fsf@junk.nocrew.org> <853csqql40.fsf@junk.nocrew.org> <85lm6hoy72.fsf@junk.nocrew.org> <8765xkslao.fsf@prep.synonet.com> Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 05 Sep 2002 13:14:13 -0700 Message-ID: Lines: 16 User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: 209.66.107.17 X-Trace: 5 Sep 2002 13:39:01 -0700, 209.66.107.17 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!uninett.no!news.net.uni-c.dk!arclight.uoregon.edu!enews.sgi.com!news.spies.com!209.66.107.17 Xref: chonsp.franklin.ch alt.sys.pdp10:11832 Paul Repacholi writes: [about the KL10-PW] > That is the CPU of the KL10-RE? If so, then it was known about during > the Fall 83 DECUS. The KL10-PW is the CPU of the 1095 and 2065; that is what distinguishes them from the 1091 and 2060. Earlier "model B" CPUs (KL10-PV) could be upgraded to the KL10-PW by replacing some CPU modules (about seven of them, IIRC), and making a few backplane wiring changes. The KL10-PW-specific modules can be recognized by the fact that they have module numbers of the form M-85x (three digits), versus M-85xx (four digits) for all other KL10 CPU modules. This was an interesting reversal of the earlier trend in the PDP-8/e and PDP-11 to replace older Mxxx modules with new improved designs designated Mxxxy. ###### From: greenaum@BOLLOCKSyahoo.co.uk Newsgroups: comp.arch,alt.folklore.computers Subject: Re: What was the size of Microcode in various machines Date: Mon, 9 Sep 2002 18:28:55 +0000 (UTC) Organization: Rossum's Universal Robots Lines: 12 Message-ID: <3d8b5952.18042945@news.btopenworld.com> References: <3D6EA8D1.1CE008B7@cisco.com> <3D743E47.4A05925@jps.net> Reply-To: greenaum@BOLLOCKSyahoo.co.uk NNTP-Posting-Host: host213-122-80-163.in-addr.btopenworld.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: knossos.btinternet.com 1031596135 22027 213.122.80.163 (9 Sep 2002 18:28:55 GMT) X-Complaints-To: news-complaints@lists.btinternet.com NNTP-Posting-Date: Mon, 9 Sep 2002 18:28:55 +0000 (UTC) X-No-Archive: yes X-Newsreader: Forte Agent 1.5/32.452 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!newsfeed.stueberl.de!teaser.fr!proxad.net!proxad.net!news-hub.cableinet.net!blueyonder!btnet-peer!btnet-peer0!btnet-feed5!btnet!news.btopenworld.com!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:116221 > first PDP-11, the 11/20 had no microcode (this is called a "hardcoded > cpu"?) I've seen it called "random logic", as in the Z80 was designed using random logic. Actually that seems odd considering how orthogonal it was, well, fairly. ------------------------------------------------------------------------ if love is a drug, then, ideally, it's a healing, healthful drug... it's kind of like prozac is supposed to work (without the sexual side effects and long-term damage to the brain and psyche) ###### From: Paul Wallich Newsgroups: comp.arch,alt.folklore.computers Subject: Re: What was the size of Microcode in various machines Date: Mon, 09 Sep 2002 16:18:07 -0400 Organization: PANIX Public Access Internet and UNIX, NYC Lines: 26 Message-ID: References: <3D6EA8D1.1CE008B7@cisco.com> <3D743E47.4A05925@jps.net> <3d8b5952.18042945@news.btopenworld.com> NNTP-Posting-Host: vt-montpelier1a-442.bur.adelphia.net X-Trace: reader1.panix.com 1031602682 565 24.48.165.186 (9 Sep 2002 20:18:02 GMT) X-Complaints-To: abuse@panix.com NNTP-Posting-Date: Mon, 9 Sep 2002 20:18:02 +0000 (UTC) User-Agent: MT-NewsWatcher/3.1 (PPC) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news.stealth.net!news.stealth.net!panix!pw Xref: chonsp.franklin.ch alt.folklore.computers:116269 In article <3d8b5952.18042945@news.btopenworld.com>, greenaum@BOLLOCKSyahoo.co.uk wrote: >> first PDP-11, the 11/20 had no microcode (this is called a "hardcoded >> cpu"?) > >I've seen it called "random logic", as in the Z80 was designed using >random logic. Actually that seems odd considering how orthogonal it >was, well, fairly. In this context, "random" has the twisted CS sense of "utterly deterministic but not superficially regular". Random logic just means laying out exactly the gates required to implement a given function (say, instruction decoding and sequencing) with a minimum of wiring between them and no obvious redundancies. So regular structures such as a microcode ROM or a PLA are right out. Of course, random logic and microcode are by no means incompatible -- in fact, microcode tends to imply the presence of a certain amount of random logic to actually execute the twiddling expressed by the microcode bits. See, for example, the design of the Xerox Alto. (It occurs to me that every computer at PARC in the late 1970s, along with the network connections between them, could now be implemented in the corner of one FPGA.) paul ###### From: Bernd Paysan Subject: Re: What was the size of Microcode in various machines Newsgroups: comp.arch,alt.folklore.computers Followup-To: comp.arch Date: Tue, 10 Sep 2002 12:52:57 +0200 References: <3D6EA8D1.1CE008B7@cisco.com> <3D743E47.4A05925@jps.net> <3d8b5952.18042945@news.btopenworld.com> User-Agent: KNode/0.7.1 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Message-ID: <9uikla.t33.ln@miriam> Lines: 22 NNTP-Posting-Host: 194.139.17.47 X-Trace: 1031655603 read.news.de.uu.net 194 194.139.17.47 X-Complaints-To: abuse@de.uu.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!newsfeed.online.be!bnewspeer00.bru.ops.eu.uu.net!bnewspost00.bru.ops.eu.uu.net!emea.uu.net!read.news.de.uu.net!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:116370 Paul Wallich wrote: > Of course, random logic and microcode are by no means incompatible -- in > fact, microcode tends to imply the presence of a certain amount of > random logic to actually execute the twiddling expressed by the > microcode bits. I don't call register files, ALUs, and multiplexers "random logic", since they have a quite regular structure. Microcode was often implemented in a way so that very few irregular structures would be needed. After all, automatic place and route tools weren't invented when microcode was popular. Nowadays, only CISC CPUs still have microcode for some of their most complex instructions (e.g. jmpf/callf in x86) - and this microcode translates to instructions that are equivalent to the simpler normal x86 instructions, but can use some additional registers for internal states within the microcode program. -- Bernd Paysan "If you want it done right, you have to do it yourself" http://www.jwdt.com/~paysan/ ###### From: dutky@bellatlantic.net (Jeffrey Dutky) Newsgroups: comp.arch,alt.folklore.computers Subject: Re: What was the size of Microcode in various machines Date: 10 Sep 2002 11:21:18 -0700 Organization: http://groups.google.com/ Lines: 20 Message-ID: References: <3D6EA8D1.1CE008B7@cisco.com> <3D743E47.4A05925@jps.net> <3d8b5952.18042945@news.btopenworld.com> <9uikla.t33.ln@miriam> NNTP-Posting-Host: 12.42.34.10 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1031682078 30854 127.0.0.1 (10 Sep 2002 18:21:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 10 Sep 2002 18:21:18 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:116365 Bernd Paysan wrote: > Nowadays, only CISC CPUs still have microcode for some of their > most complex instructions (e.g. jmpf/callf in x86) - and this > microcode translates to instructions that are equivalent to the > simpler normal x86 instructions, but can use some additional > registers for internal states within the microcode program. Ah, you beat me to the punch. Since the original question was asked explicitly in the past tense, I was wondering what the size and width of the microcode was in recent AMD and Intel processors? Maybe Andy Glew could comment? Otherwise, I was under the impression that pipelined processors operated under the control of something similar microcode, just with each stage run in parrallel with other stages of other instructions. Am I wrong in my impression that there is some kind of table that directs the later pipeline stages in RISC CPUs based on the decoded instruction? - Jeff Dutky