From: ab528@FreeNet.Carleton.CA (Heinz W. Wiggeshoff) Newsgroups: alt.folklore.computers Subject: Most complex instructions Date: 16 Aug 2001 18:15:48 GMT Organization: The National Capital FreeNet Lines: 11 Message-ID: <9lh2kk$k6u$1@freenet9.carleton.ca> References: <9k3oan$t35$1@top.mitre.org> <6aie7.52269$e%3.8225465@news2-win.server.ntlworld.com> Reply-To: ab528@FreeNet.Carleton.CA (Heinz W. Wiggeshoff) NNTP-Posting-Host: freenet10 X-Trace: freenet9.carleton.ca 997985748 20702 134.117.136.30 (16 Aug 2001 18:15:48 GMT) X-Complaints-To: complaints@ncf.ca NNTP-Posting-Date: 16 Aug 2001 18:15:48 GMT X-Given-Sender: ab528@freenet10.carleton.ca (Heinz W. Wiggeshoff) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!news-out.visi.com!hermes.visi.com!nntp1.roc.gblx.net!nntp.gblx.net!nntp.gblx.net!xcski.com!freenet-news!FreeNet.Carleton.CA!ab528 Xref: chonsp.franklin.ch alt.folklore.computers:87592 > In article <6aie7.52269$e%3.8225465@news2-win.server.ntlworld.com>, > Chris Bigos wrote: > >>I wouldn't be surprised if the RPSB instruction (Repack Symbols) takes the >>prize for the most complex instruction ever implemented in the history of >>mainframe computing - certainly of the era. Any comments? (I guess this >>should be a new thread - if there isn't one on this topic already.) In the very early 70's, I read about a GE 6xx(?) list processing machine instruction. Someone commented that complier writers like those types of instructions. Any GE experts in a.f.c-land? ###### From: mwilson@the-wire.com (Mel Wilson) Newsgroups: alt.folklore.computers Subject: Re: Most complex instructions Message-ID: References: <9k3oan$t35$1@top.mitre.org> <6aie7.52269$e%3.8225465@news2-win.server.ntlworld.com> <9lh2kk$k6u$1@freenet9.carleton.ca> Lines: 90 X-Newsreader: VSoup v1.2.9.37Beta [95/NT] Date: Thu, 16 Aug 2001 15:38:58 -0400 NNTP-Posting-Host: 205.206.39.174 X-Trace: nnrp1.uunet.ca 998056248 205.206.39.174 (Fri, 17 Aug 2001 09:50:48 EDT) NNTP-Posting-Date: Fri, 17 Aug 2001 09:50:48 EDT Organization: UUNET Canada News Reader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!newsfeed01.sul.t-online.de!t-online.de!newsfeed.online.be!newsfeed.direct.ca!look.ca!news.uunet.ca!nnrp1.uunet.ca.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:87687 In article <9lh2kk$k6u$1@freenet9.carleton.ca>, ab528@FreeNet.Carleton.CA (Heinz W. Wiggeshoff) wrote: > In the very early 70's, I read about a GE 6xx(?) list processing machine > instruction. Someone commented that complier writers like those types > of instructions. Any GE experts in a.f.c-land? There were three instructions: Repeat, Repeat Double and Repeat Linked, coded RPT, RPD and RPL. The effect was to exceute the following one or two instructions up to a set number of times, with address modification between executions. Execution was faster because the instructions were executed out of the processor's instruction registers, without being re-fetched. Typical uses: Presetting a memory buffer to a fixed value (two words at a time): LDA FIXVAL initializing value LDQ FIXVAL again EAX1 BUFFADR address of the buffer RPT BUFFLEN/2,2 repeat_count and address increment STAQ 0,X1 repeat this instruction to fill buffer Block move of words in memory, one at a time: EAX3 FROMBUF address of sending field EAX6 TOBUF address of receiving field ORPD BUFFLEN,1 count and address increment LDA 0,X3 load from sending area STA 0,X6 store into receiving area The 'O' in 'ORPD' was an assembler directive which forced the RPD instruction to an odd address, because the instructions being repeated had to occupy an even-odd pair, so that they would occupy the 72-bit-wide instruction register together. The only reserved register for the repeat instructions was X0 which always held the running repeat-count, and a whack of control bits, which were filled in from optional fields in the RPx instruction that I no longer rememeber. One option caused the existing contents of X0 to control the process, so that repeat-counts could be computed at run-time. There were alse options to suppress modification of either operand address during the repeat, and options to stop repeating on various indicator register flags. This let you repeat a compare instruction to do, e.g. a sequential scan down a table, which might have looked something like: EAX5 0 prepare address reg LDA HILIM look for an entry > this value RPT TABLENG/6,6,TRC check each 6-word entry for word 1 > hilim CMPA TABLE+1,X5 compare table word with A reg TTF FOUNDIT transfer on tally-runout flag Off ... fall through if the search failed with the effect of running down a table of 6-word entries to find the first one whose second word exceeded a given value. IIRC, if the repeat count ran out, the Tally Runout indicator was set, so the not-found condition could be handled, as hinted above. On the found condition, the working address reg. would point at the last operand word. There was no typical use for the Repeat Linked (RPL) instruction. Nobody of my acquaintance ever found a use for it, and we tried. Rather than adding an increment, It would load the operand address for the next repetition from the high-order 18 bits of the current operand. You were pretty much stuck with testing bits in the low-order half of the word, and any possible application always seemed to need a little more. The repeat instructions always ran with interrupts inhibited because there was no way to save enough processor state to restart the instruction after an interrupt. This caused trouble trying to run GCOS code in a Multics system: a page-fault turns out to be, fundamentally, an interrupt you don't dare inhibit. Native Multics programs never used RPT, RPD or RPL; the newer Extended Instruction Set instructions could do the same things, arguably better. I never saw enough of virtual-memory GCOS to know if it had another solution. All the above IIRC, of course. Regards. Mel. ###### Sender: lynn@LYNNPC Newsgroups: alt.folklore.computers Subject: Re: Most complex instructions References: <9k3oan$t35$1@top.mitre.org> <6aie7.52269$e%3.8225465@news2-win.server.ntlworld.com> <9lh2kk$k6u$1@freenet9.carleton.ca> Reply-To: Anne & Lynn Wheeler From: Anne & Lynn Wheeler Message-ID: Organization: Wheeler&Wheeler Lines: 38 User-Agent: Gnus/5.0808 (Gnus v5.8.8) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Thu, 16 Aug 2001 20:50:31 GMT NNTP-Posting-Host: 199.174.225.253 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 997995031 199.174.225.253 (Thu, 16 Aug 2001 13:50:31 PDT) NNTP-Posting-Date: Thu, 16 Aug 2001 13:50:31 PDT X-Received-Date: Thu, 16 Aug 2001 13:47:54 PDT (newsmaster1.prod.itd.earthlink.net) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!kanja.arnes.si!news-hub.siol.net!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!rcn!newsfeed1.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:87694 ab528@FreeNet.Carleton.CA (Heinz W. Wiggeshoff) writes: > > In the very early 70's, I read about a GE 6xx(?) list processing machine > instruction. Someone commented that complier writers like those types > of instructions. Any GE experts in a.f.c-land? some where in early '90s(?), the ibm mainframe added instructions supporting luther woodrums radix partition tree stuff misc. ref http://www.garlic.com/~lynn/98.html#19 S/360 operating systems geneaology http://www.garlic.com/~lynn/98.html#20 Reviving the OS/360 thread (Questions about OS/360) http://www.garlic.com/~lynn/2001.html#2 A new "Remember when?" period happening right now from ibm pinciples of operation http://publibz.boulder.ibm.com:80/cgi-bin/bookmgr_OS390/BOOKS/DZ9AR004/A.7 and for even more complex stuff there is the whole (supervisor state) infrastructure controlling access to multiple address spaces along with the program call mechanism (access registers). The idea behind program call was to try and have the efficiency of branch and link while trying to preserve some authentication & access control checking that would be possible with a kernel call (aka but w/o the overhead). http://publibz.boulder.ibm.com:80/cgi-bin/bookmgr_OS390/BOOKS/DZ9AR004/5.4 http://publibz.boulder.ibm.com:80/cgi-bin/bookmgr_OS390/BOOKS/DZ9AR004/5.5 http://publibz.boulder.ibm.com:80/cgi-bin/bookmgr_OS390/BOOKS/DZ9AR004/5.6 http://publibz.boulder.ibm.com:80/cgi-bin/bookmgr_OS390/BOOKS/DZ9AR004/5.7 http://publibz.boulder.ibm.com:80/cgi-bin/bookmgr_OS390/BOOKS/DZ9AR004/5.8 http://publibz.boulder.ibm.com:80/cgi-bin/bookmgr_OS390/BOOKS/DZ9AR004/5.9 http://publibz.boulder.ibm.com:80/cgi-bin/bookmgr_OS390/BOOKS/DZ9AR004/5.10 http://publibz.boulder.ibm.com:80/cgi-bin/bookmgr_OS390/BOOKS/DZ9AR004/5.11 http://publibz.boulder.ibm.com:80/cgi-bin/bookmgr_OS390/BOOKS/DZ9AR004/5.12 and then there is poor SIE instruction ref'ed in previous posting. -- Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/ ###### From: mark@hubcap.clemson.edu (Mark Smotherman) Newsgroups: alt.folklore.computers Subject: Re: Most complex instructions Date: 16 Aug 2001 18:05:16 -0400 Organization: Clemson University Lines: 94 Message-ID: <9lhg2s$gth$1@hubcap.clemson.edu> References: <9k3oan$t35$1@top.mitre.org> <6aie7.52269$e%3.8225465@news2-win.server.ntlworld.com> <9lh2kk$k6u$1@freenet9.carleton.ca> NNTP-Posting-Host: localhost X-Trace: hubcap.clemson.edu 997999516 17330 127.0.0.1 (16 Aug 2001 22:05:16 GMT) X-Complaints-To: usenet@hubcap.clemson.edu NNTP-Posting-Date: 16 Aug 2001 22:05:16 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed.nextra.ch!news.nextra.ch!nextra.at!newsfeed2.skycache.com!Cidera!dca6-feed2.news.digex.net!jfk3-feed1.news.digex.net!intermedia!news.maxwell.syr.edu!news.mindspring.net!finch!hubcap.clemson.edu!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:87703 ab528@FreeNet.Carleton.CA (Heinz W. Wiggeshoff) writes: > In the very early 70's, I read about a GE 6xx(?) list processing machine > instruction. Someone commented that complier writers like those types > of instructions. Any GE experts in a.f.c-land? Perhaps you mean an instruction using indirection and then index tally words? I have a GE 635 manual to check the details if we can identify the instruction. Or perhaps it was an EIS instruction (a commercial inst. set added to the base accumulator machine architecture). I don't believe the 645/Multics added anything like this. IBM 1401 | 625 (1964) | / | \ | 635 | 615 Honeywell 200 .------' | | | transistors 645 | 605 (military) | - - - - - - - - | - - - - | - - - - - - - - | - - - - - - - - - - - integrated | 655 (1969) | circuits | | | IBM S/3 (wire wrap) 6180 6000 | | - - - - - - - - | - - - - | - - - - - - - - | - - - - - - | - - - printed Level 68 Level 66 Level 64 Level 62 circuit | | | boards DPS-8 DPS-6 DPS-7 Model designators for the Series 6000 non-EIS EIS EIS = extended instruction set, ------- ---- supported business d.p. (COBOL) slower / 6010 6020 versions\ 6030 6040 standard 6050 6060 w/cache 6070 6080 The non-Multics 6xx series had 18-bit addressability (the granularity of which was 36-bit word), and used the relocation register. There were two modes of execution: master/slave. OS entry was accomplished by a MME instruction (master mode entry). 645 Multics used 24-bit addressability and added a third execution mode: absolute. Absolute mode used physical addressing, while master and slave used virtual addressing via the segmentation and paging scheme. Non-Multics 6xx addressing modes R - register - use index register specified in tag field RI - register then indirect (multiple levels of indirection possible) IR - indirect then register (multiple levels of indirection possible) IT - indirect then tally (tally controlled character manipulation in this word-oriented machine) 6xx added several interesting "meta" instructions: execute, execute double repeat, repeat link, repeat double Non-Multics 6xx Registers 72-bit AQ eight 18-bit index registers Xn 8-bit exponent register 18-bit indicator register 24-bit timer register 18-bit instruction address register 18-bit base address register BAR (relocation register) 0 7 9 16 +-------+-+--------+-+ | base |0| blocks |0| blocks = # 1024-word blocks allocated +-------+-+--------+-+ 645 Multics added eight 24-bit base registers linked in four pairs (these were locked to prevent access in slave mode), an 18-bit procedure base register, an 18-bit temporary base register, and a 29-bit descriptor base register. Level 66 extended the relocation register by 6 bits to achieve a 16M physical address space, although user processes still had an 18-bit limit. -- Mark Smotherman, Computer Science Dept., Clemson University, Clemson, SC http://www.cs.clemson.edu/~mark/homepage.html ###### Message-ID: <3B7C440D.18378F84@thinkage.ca> From: "Alan T. Bowler" Organization: Thinkage Ltd. X-Mailer: Mozilla 4.5 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.folklore.computers Subject: Re: Most complex instructions References: <9k3oan$t35$1@top.mitre.org> <6aie7.52269$e%3.8225465@news2-win.server.ntlworld.com> <9lh2kk$k6u$1@freenet9.carleton.ca> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 42 Date: Thu, 16 Aug 2001 18:07:09 -0400 NNTP-Posting-Host: 192.102.11.4 X-Trace: nnrp1.uunet.ca 997999628 192.102.11.4 (Thu, 16 Aug 2001 18:07:08 EDT) NNTP-Posting-Date: Thu, 16 Aug 2001 18:07:08 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!4993885!news.imp.ch!sunqbc.risq.qc.ca!news.uunet.ca!nnrp1.uunet.ca.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:87660 "Heinz W. Wiggeshoff" wrote: > > > In article <6aie7.52269$e%3.8225465@news2-win.server.ntlworld.com>, > > Chris Bigos wrote: > > > >>I wouldn't be surprised if the RPSB instruction (Repack Symbols) takes the > >>prize for the most complex instruction ever implemented in the history of > >>mainframe computing - certainly of the era. Any comments? (I guess this > >>should be a new thread - if there isn't one on this topic already.) > > In the very early 70's, I read about a GE 6xx(?) list processing machine > instruction. Someone commented that complier writers like those types > of instructions. Any GE experts in a.f.c-land? The 600 Series had (has? since the architecture lives on) 3 "repeat" instructions that were sort of a poor man's vector mode. You can arrange that the next instruction is repeatedly executed until a count is reached, or a condition code satisfied. An index register is advanced so that you step through memory. RPT repeats one instruction, typical use add up a set of numbers of do a linear search RPD "repeat double" repeats two instructions if the instructions were load and store this could be used for a block move. This use was generally superceded when character and bit vector block move instrctions were added to the architecture. RPL "repeat link" This was the primary list processing variation. With effort you can also use the repeat double to run down a list. I don't know of any compiler that uses repeat link, for generated code, and RPT and RPD are sometimes generated to do the case lookup for B/C/Pascal switch statements. Other than that compilers generally can't find a use for these instructions. There is some library code that uses them. The C library memory allocator is the principal user of RPL and RPD to manage its free list. None of the repeat instructions is particulary complex, and they are all a lot simpler than the "move edit" instruction which is used by the Cobol compiler. Even more complex is the interdomain call/return instruction. (Calls to the OS for supervisor services are just part of its use.) ###### Message-ID: <3B7D4BD1.1E03C62F@thinkage.ca> From: "Alan T. Bowler" Organization: Thinkage Ltd. X-Mailer: Mozilla 4.5 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.folklore.computers Subject: Re: Most complex instructions References: <9k3oan$t35$1@top.mitre.org> <6aie7.52269$e%3.8225465@news2-win.server.ntlworld.com> <9lh2kk$k6u$1@freenet9.carleton.ca> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 35 Date: Fri, 17 Aug 2001 12:52:33 -0400 NNTP-Posting-Host: 192.102.11.4 X-Trace: nnrp1.uunet.ca 998067151 192.102.11.4 (Fri, 17 Aug 2001 12:52:31 EDT) NNTP-Posting-Date: Fri, 17 Aug 2001 12:52:31 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!newsfeed01.sul.t-online.de!t-online.de!newsfeed.online.be!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feeder.qis.net!sunqbc.risq.qc.ca!news.uunet.ca!nnrp1.uunet.ca.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:87664 Mel Wilson wrote: > > There was no typical use for the Repeat Linked (RPL) > instruction. Nobody of my acquaintance ever found a use for > it, and we tried. Rather than adding an increment, It would > load the operand address for the next repetition from the > high-order 18 bits of the current operand. You were pretty > much stuck with testing bits in the low-order half of the > word, and any possible application always seemed to need a > little more. I use it for the memory allocator in the single segment (unpaged, small-model) C library, also in the print image writers for the list of overstruck characters. > > The repeat instructions always ran with interrupts > inhibited because there was no way to save enough processor > state to restart the instruction after an interrupt. This > caused trouble trying to run GCOS code in a Multics system: > a page-fault turns out to be, fundamentally, an interrupt > you don't dare inhibit. Native Multics programs never used > RPT, RPD or RPL; the newer Extended Instruction Set > instructions could do the same things, arguably better. I > never saw enough of virtual-memory GCOS to know if it had > another solution. Essentially repeats are not used in that mode. The NS mode C memory allocator uses essentially the same data structure as the SS mode one, but uses a loop instead of an RPL. I sometimes debate restoring the repeats and taking a user level fault since although the repeat can't be restarted, I know where the algorithm can. However, it is probable that I really should investigate a completely different algorithm. ###### Message-ID: <3B7E6560.F5F6DE9F@yahoo.com> From: CBFalconer Reply-To: cbfalconer@worldnet.att.net Organization: Ched Research X-Mailer: Mozilla 4.75 [en] (Win98; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.folklore.computers Subject: Re: Most complex instructions (was Re: IBM 9020 FAA/ATC Systems from 1960's) References: <7HU77.9333$TM5.980906@typhoon.southeast.rr.com> <9k3oan$t35$1@top.mitre.org> <6aie7.52269$e%3.8225465@news2-win.server.ntlworld.com> <3B7C2B74.3E3D9FA4@yahoo.com> <9lkppq$jvf$1@daemonweed.reanimators.org> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 26 Date: Sat, 18 Aug 2001 17:09:06 GMT NNTP-Posting-Host: 12.90.169.240 X-Complaints-To: abuse@worldnet.att.net X-Trace: bgtnsc05-news.ops.worldnet.att.net 998154546 12.90.169.240 (Sat, 18 Aug 2001 17:09:06 GMT) NNTP-Posting-Date: Sat, 18 Aug 2001 17:09:06 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!pinatubo.switch.ch!newsfeeds.belnet.be!news.belnet.be!news.stealth.net!204.127.161.2.MISMATCH!wn2feed!worldnet.att.net!135.173.83.71!wnfilter1!worldnet-localpost!bgtnsc05-news.ops.worldnet.att.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:87753 Frank McConnell wrote: > > CBFalconer wrote: > > I believe the HP3000 circa 1980 had a 'schedule' instruction > > micro-programmed. This could be used to voluntarily relinquish > > the CPU, or by the op-sys on the appropriate timer interrupt. > > DISP, and its disable/enable pair PSDB and PSEB. All privileged > instructions, not intended for user code, although I have read and > written privileged non-system code use PSDB/PSEB to stall the > dispatcher. DISP effectively causes an interrupt (either when the > DISP instruction is executed, or when a later PSEB returns the > pseudo-disable count to 0), and that gets the actual MPE dispatcher > code involved. > > (Present tense: some of us still have runnable and/or running classic > 3000s!) Shades of MPE and SPL. Does HP still maintain those machines? -- Chuck F (cbfalconer@yahoo.com) (cbfalconer@XXXXworldnet.att.net) (Remove "XXXX" from reply address. yahoo works unmodified) mailto:uce@ftc.gov (for spambots to harvest) ###### Sender: lynn@LYNNPC Newsgroups: alt.folklore.computers Subject: Re: Most complex instructions (was Re: IBM 9020 FAA/ATC Systems from 1960's) References: <7HU77.9333$TM5.980906@typhoon.southeast.rr.com> <9k3oan$t35$1@top.mitre.org> <6aie7.52269$e%3.8225465@news2-win.server.ntlworld.com> <3B7C2B74.3E3D9FA4@yahoo.com> <9lkppq$jvf$1@daemonweed.reanimators.org> Reply-To: Anne & Lynn Wheeler From: Anne & Lynn Wheeler Message-ID: Organization: Wheeler&Wheeler Lines: 109 User-Agent: Gnus/5.0808 (Gnus v5.8.8) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Sat, 18 Aug 2001 17:52:39 GMT NNTP-Posting-Host: 199.174.230.80 X-Complaints-To: abuse@earthlink.net X-Trace: newsread2.prod.itd.earthlink.net 998157159 199.174.230.80 (Sat, 18 Aug 2001 10:52:39 PDT) NNTP-Posting-Date: Sat, 18 Aug 2001 10:52:39 PDT X-Received-Date: Sat, 18 Aug 2001 10:49:22 PDT (newsmaster1.prod.itd.earthlink.net) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed1.cidera.com!Cidera!cyclone2.usenetserver.com!usenetserver.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread2.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:87761 Frank McConnell writes: > DISP, and its disable/enable pair PSDB and PSEB. All privileged > instructions, not intended for user code, although I have read and > written privileged non-system code use PSDB/PSEB to stall the > dispatcher. DISP effectively causes an interrupt (either when the > DISP instruction is executed, or when a later PSEB returns the > pseudo-disable count to 0), and that gets the actual MPE dispatcher > code involved. VAMPS was a multiprocessor version of 370/125. The 370/115 & 370/125 had somewhat unique internal architectures (for 370). They consisted of a 9port (370) memory bus and several microprocessor engines installed on the memory bus ports. In the 370/115, all the microprocessors were identical ... they just had different programs loaded that were function specific ... i.e. emulate 370 processor, disk controller, unit record controller, tape controller, telecommunication controller, etc. The 370/125 differed from the 115 in that the engine used for the 370 emulation was about 50% faster than the other engines. VAMPS was a 370/125 project to install up to five "370 engines" in the same configuration (in max. 370 configuration, it only left four ports for controller engines). For the VAMPS project, migrated the VM/370 dispatcher, much of the first level interrupt handlers, and much of the page I/O supervisor into "mirocode" of the various engines; and of course there were the corresponding (privilege) instructions to interface to these migrated functions ... i.e. add task to dispatching queue, add page request to page I/O queue, etc. The 370 "engines" also had an enhanced version of VM microcode assist (in part because I was also concurrently working on ECPS for virgil/tully). The 370 "microcode" engine would attempt to perform all functions ... including various microcode assist operations. If it found that it could not complete an operation and needed survices of the (software) kernel, it would check to see if any processor was already operating in kernel mode, if so it would just queue a light-weight request with sufficient information to invoke the necessary processing and go looking for some other work. If there was no processor already in kernel mode, it would just enter kernel mode. The point was that 1) the then existing VM/370 kernel didn't have full symmetric multiprocessing support 2) the changes for the above amounted to relatively trivial number of lines of code in the kernel software, 3) the measured percent kernel time (based on the enhanced microcode assist) was much less than 20% (so a five engine configuration might have something like total max of 80% a single engine in kernel mode). When the VAMPS project was terminated, in part because the processing power overlapped the virgil/tully configurations ... we adopted the microcode design to kernel software. High-activity paths of the kernel that received control directly from the first level interrupt handlers were modified to support fine-grain locking symmetrical multiprocessing. However, the majority of the kernel (in terms of total code size, but not in terms of percent pathlength) was behind a single "kernel" lock. The traditional IBM mainframe approach to symmetric multiprocessing up until that time was single "kernel" lock where a processor would "spin" on the kernel lock until it was available. Adopting the VAMPS microcode dispatcher design to the software kernel, resulted instead something that I called a "bounce" lock; aka if the processor didn't obtain the "kernel" lock, it would queue a light-weight request for kernel lock/services and go off to the dispatcher to find some other work to do. This implementation provided the absolute maximum symmetric multiprocessor thruput per line of SMP code modifications. random refs: http://www.garlic.com/~lynn/subtopic.html#smp Multiprocessor, tightly-coupled, SMP, compare&swap http://www.garlic.com/~lynn/subtopic.html#fairshare Performance and/or Scheduling http://www.garlic.com/~lynn/95.html#5 Who started RISC? (was: 64 bit Linux?) http://www.garlic.com/~lynn/95.html#6 801 http://www.garlic.com/~lynn/99.html#149 OS/360 (and descendents) VM system? http://www.garlic.com/~lynn/2000.html#11 I'm overwhelmed http://www.garlic.com/~lynn/2000.html#12 I'm overwhelmed http://www.garlic.com/~lynn/2000c.html#30 internal corporate network, misc. http://www.garlic.com/~lynn/2000c.html#49 Does the word "mainframe" still have a meaning? http://www.garlic.com/~lynn/2000c.html#68 Does the word "mainframe" still have a meaning? http://www.garlic.com/~lynn/2000d.html#10 4341 was "Is a VAX a mainframe?" http://www.garlic.com/~lynn/2000d.html#11 4341 was "Is a VAX a mainframe?" http://www.garlic.com/~lynn/2000e.html#6 Ridiculous http://www.garlic.com/~lynn/2000e.html#7 Ridiculous http://www.garlic.com/~lynn/2000f.html#63 TSS ancient history, was X86 ultimate CISC? designs) http://www.garlic.com/~lynn/2000g.html#7 360/370 instruction cycle time http://www.garlic.com/~lynn/2000g.html#8 360/370 instruction cycle time http://www.garlic.com/~lynn/2001b.html#40 John Mashey's greatest hits http://www.garlic.com/~lynn/2001c.html#2 Z/90, S/390, 370/ESA (slightly off topic) http://www.garlic.com/~lynn/2001f.html#43 Golden Era of Compilers http://www.garlic.com/~lynn/2001f.html#69 Test and Set (TS) vs Compare and Swap (CS) http://www.garlic.com/~lynn/2001h.html#33 D http://www.garlic.com/~lynn/2001h.html#69 Very CISC Instuctions (Was: why the machine word size ...) -- Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/ ###### Sender: lynn@LYNNPC Newsgroups: alt.folklore.computers Subject: Re: Most complex instructions (was Re: IBM 9020 FAA/ATC Systems from 1960's) References: <7HU77.9333$TM5.980906@typhoon.southeast.rr.com> <9k3oan$t35$1@top.mitre.org> <6aie7.52269$e%3.8225465@news2-win.server.ntlworld.com> <3B7C2B74.3E3D9FA4@yahoo.com> <9lkppq$jvf$1@daemonweed.reanimators.org> Reply-To: Anne & Lynn Wheeler From: Anne & Lynn Wheeler Message-ID: Organization: Wheeler&Wheeler Lines: 41 User-Agent: Gnus/5.0808 (Gnus v5.8.8) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Sat, 18 Aug 2001 17:59:48 GMT NNTP-Posting-Host: 199.174.230.80 X-Complaints-To: abuse@earthlink.net X-Trace: newsread2.prod.itd.earthlink.net 998157588 199.174.230.80 (Sat, 18 Aug 2001 10:59:48 PDT) NNTP-Posting-Date: Sat, 18 Aug 2001 10:59:48 PDT X-Received-Date: Sat, 18 Aug 2001 10:56:31 PDT (newsmaster1.prod.itd.earthlink.net) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!fu-berlin.de!cyclone2.usenetserver.com!usenetserver.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread2.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:87760 Anne & Lynn Wheeler writes: > The 370 "engines" also had an enhanced version of VM microcode assist > (in part because I was also concurrently working on ECPS for > virgil/tully). oh yes, and some misc. ECPS, virgil/tully, microcode, etc refs: http://www.garlic.com/~lynn/subtopic.html#360mcode 370/370 m'code http://www.garlic.com/~lynn/94.html#21 370 ECPS VM microcode assist http://www.garlic.com/~lynn/94.html#27 370 ECPS VM microcode assist http://www.garlic.com/~lynn/94.html#28 370 ECPS VM microcode assist http://www.garlic.com/~lynn/94.html#51 Rethinking Virtual Memory http://www.garlic.com/~lynn/95.html#3 What is an IBM 137/148 ??? http://www.garlic.com/~lynn/99.html#7 IBM S/360 http://www.garlic.com/~lynn/99.html#148 OS/360 (and descendents) VM system? http://www.garlic.com/~lynn/2000.html#12 I'm overwhelmed http://www.garlic.com/~lynn/2000b.html#37 How to learn assembler language for OS/390 ? http://www.garlic.com/~lynn/2000c.html#50 Does the word "mainframe" still have a meaning? http://www.garlic.com/~lynn/2000c.html#76 Is a VAX a mainframe? http://www.garlic.com/~lynn/2000d.html#11 4341 was "Is a VAX a mainframe?" http://www.garlic.com/~lynn/2000d.html#12 4341 was "Is a VAX a mainframe?" http://www.garlic.com/~lynn/2000d.html#20 S/360 development burnout? http://www.garlic.com/~lynn/2000e.html#6 Ridiculous http://www.garlic.com/~lynn/2000f.html#55 X86 ultimate CISC? No. (was: Re: "all-out" vs less aggressive designs) http://www.garlic.com/~lynn/2000f.html#57 X86 ultimate CISC? No. (was: Re: "all-out" vs less aggressive designs) http://www.garlic.com/~lynn/2000f.html#63 TSS ancient history, was X86 ultimate CISC? designs) http://www.garlic.com/~lynn/2000g.html#7 360/370 instruction cycle time http://www.garlic.com/~lynn/2001b.html#29 z900 and Virtual Machine Theory http://www.garlic.com/~lynn/2001b.html#69 Z/90, S/390, 370/ESA (slightly off topic) http://www.garlic.com/~lynn/2001b.html#83 Z/90, S/390, 370/ESA (slightly off topic) http://www.garlic.com/~lynn/2001c.html#2 Z/90, S/390, 370/ESA (slightly off topic) http://www.garlic.com/~lynn/2001c.html#48 database (or b-tree) page sizes http://www.garlic.com/~lynn/2001d.html#26 why the machine word size is in radix 8?? http://www.garlic.com/~lynn/2001d.html#54 VM & VSE news http://www.garlic.com/~lynn/2001e.html#73 CS instruction, when introducted ? http://www.garlic.com/~lynn/2001f.html#16 Wanted other CPU's http://www.garlic.com/~lynn/2001h.html#59 Blinkenlights -- Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/ ###### From: mwilson@the-wire.com (Mel Wilson) Newsgroups: alt.folklore.computers Subject: Re: Most complex instructions Message-ID: References: <9k3oan$t35$1@top.mitre.org> <6aie7.52269$e%3.8225465@news2-win.server.ntlworld.com> <9lh2kk$k6u$1@freenet9.carleton.ca> <9lhg2s$gth$1@hubcap.clemson.edu> Lines: 26 X-Newsreader: VSoup v1.2.9.37Beta [95/NT] Date: Tue, 21 Aug 2001 08:41:57 -0400 NNTP-Posting-Host: 205.206.39.140 X-Trace: nnrp1.uunet.ca 998398366 205.206.39.140 (Tue, 21 Aug 2001 08:52:46 EDT) NNTP-Posting-Date: Tue, 21 Aug 2001 08:52:46 EDT Organization: UUNET Canada News Reader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.direct.ca!look.ca!news.uunet.ca!nnrp1.uunet.ca.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:87948 In article <9lhg2s$gth$1@hubcap.clemson.edu>, mark@hubcap.clemson.edu (Mark Smotherman) wrote: >Perhaps you mean an instruction using indirection and then index tally words? >I have a GE 635 manual to check the details if we can identify the instruction. [ a summary of series 6000 features ] Great chart. I've saved it. Thanks. >Model designators for the Series 6000 > > non-EIS EIS EIS = extended instruction set, > ------- ---- supported business d.p. (COBOL) >slower / 6010 6020 > versions\ 6030 6040 >standard 6050 6060 >w/cache 6070 6080 The 6180 was also an EIS machine. In fact the pointer registers used by Multics for segment/offset addressing were combined with the EIS address registers used for word/character/bit addressing. I don't know if this fits with your over-all scheme; I'm mentioning it just in case. Regards. Mel.