From: J Ahlstrom Newsgroups: alt.folklore.computers,comp.arch Subject: Intel 4004 Memory Date: Tue, 24 Apr 2001 16:52:16 -0700 Organization: Cisco Systems Inc. Message-ID: <3AE611B0.9C0479D0@cisco.com> X-Mailer: Mozilla 4.76 [en]C-CCK-MCD (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cache-Post-Path: sj-nntpcache-5!unknown@dhcp-171-68-135-147.cisco.com X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) X-Complaints-To: newsabuse@supernews.com Lines: 69 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!sn-xit-01!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:79294 Stan Mazor has asked me to post this. I worked on Intel MCS-4 at Intel in 1969/70. The 4002 RAM used 3 transistor PMOS dynamic RAM and 14 volt supply. The cpu cycle had 8 states of 1 Mhz. clock or about 1 microsecond each, designated a1, a2, a3, m1, m2, x1, x2, x3. During a1 and a2 the ROM address was sent (8-bits) to all ROM's during a3 the chip code was sent to all ROM's to enable 1 ROM chip. during m1, m2 the 8-bit instruction was fetched, during x1, x2, x3 the instruction was executed. Therefore the RAM was never used during a1, a2, a3, and the RAM was refreshed using an on 4002 chip refresh counter. If RAM was to be fetched the index registers sent out the address, in one instruction and the data was sent or received in another. As best I recall the addressing instruction was called SRC. Since the address to RAM out time was several micro-seconds of sequential state delay, the RAM access time wasn't relevant. My guess is that it operated in one clock time, but I don't remember. I think the best guess was that we designed the chip to operate at 1 microsecond per cycle, and the RAM cycle time was probably 1 microsecond inside the chip. We organized the 320-bit RAM as 4 words of 80-bits/20 digits each. 20 digits was for each floating point number being 16 digits of mantissa, 2 digits of exponent, 2 digits for sign and flags. The 16-pin package had a 4-bit bus for receiving the address, and sending the data. Since it was a bus oriented system the RAM decoded its own instruction during M1 and M2 therefore the CPU didn't have to tell the RAM what do do. (read/write) etc. Additionally the 16 digits were addressed using data in the CPU index register (4-bits), but the 4 other digits of the word were read/written by a specific opcode...e.g. read special digit 17, 18, 19, 20. Our thought was that code written for the mantissa would loop along the 16-digits, but the exponent code would be 'hard' coded to get the sign or exponent stuff. Additionally the 4002 had a 4 bit output register and 4 pins which were used to output I/O data, so there was additionaly instructions to write data to the RAM chip port (register). Again the chip had to be selected with an SRC instruction and then an output instruction was executed...as I recall. thx. stan Stanley Mazor, Director Customer Services Numerical Technologies Inc. 70 West Plumeria Drive San Jose, Ca., USA, 95134-2134 408-273-4485 fax: 408-919-1920 email: smazor@numeritech.com Safe Harbor: this message is not -- The harder I work, the luckier I get. (various including Edison, Plato, Gary Player, Sam Goldwyn)