Message-ID: <391FBFAA.1530B784@trailing-edge.com> Date: Mon, 15 May 2000 09:13:14 -0400 From: Tim Shoppa Organization: Trailing Edge Technology X-Mailer: Mozilla 3.03Gold (X11; I; OpenVMS V7.0 DEC 3000 Model 300L) MIME-Version: 1.0 Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Orthogonality (was Re: Motorola/Intel Wars) References: <8fanf1$ih4@nnrp1.farm.idt.net> <3919F95F.35BBB64F@dallas.net> <958038783.53624@shelley.paradise.net.nz> <391A9257.52DCB66D@netinsight.se> <958084713.291883@shelley.paradise.net.nz> <391B9A17.932A239E@netinsight.se> <391BB60E.487F9FCF@trailing-edge.com> <391BFBE6.BC4122CD@netinsight.se> <391BD096.6A224D5C@trailing-edge.com> <391C1A43.C4582FB5@netinsight.se> <391BF5EC.4642D331@trailing-edge.com> <391F9BD9.4178CEE5@netinsight.se> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 100 NNTP-Posting-Host: 63.73.218.130 X-Trace: reader0.news.uu.net 958396395 16870 63.73.218.130 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.nextra.ch!newsfeed1.online.no!newsfeed.online.no!newsfeed.wirehub.nl!newsfeed2.news.nl.uu.net!sun4nl!ams.uu.net!ffx.uu.net!spool0.news.uu.net!reader0.news.uu.net!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56376 Johnny Billquist wrote: > > Tim Shoppa wrote: > > > > Johnny Billquist wrote: > > > > > > Tim Shoppa wrote: > > > > > > > > R6 and R7 aren't really general purpose registers - they're SP and > > > > PC. > > > > > > Well, they no different from any other register from the instructions > > > point of view. > > > > > > SP used with autoincrement or autodecrement always add or substract > > > two, even if your are accessing bytes. > > > PC used in mode 7 automatically increment it, even though that > > > isn't obvious. > > > > I'll agree, SP and PC work into the scheme in a pretty slick way, > > but we both agree that they don't behave *exactly* like R0 through > > R5. > > Yes. But then we are talking about side effects on the register, which > isn't exactly relevant to the instruction. I don't think "autoincrement" and "autodecrement" can be called side effects. They're fundamental addressing modes. > I'm looking at the instructions, and they are orthogonal. :-) Sure, you can write them down, and MACRO-11 will even assemble them, but that doesn't mean that what they do makes any sense, or that it's even legal. For example, you can't JMP %R on any PDP-11 that I'm aware of, it's trapped as an illegal instruction. And many combinations don't do the same thing on all different PDP-11 models. For example, OPR PC,@A on a 11/23, 11/15, 11/20, 11/35, or 11/40 will put (PC of OPR)+4 into location A, while the same instruction on an 11/03, /04, /05, /10, /34, or /45 will put the (PC of OPR)+2 into location A. In my book, if an addressing mode/register combination gives different result on different processors, this makes it difficult to call it a perfectly orthogonal architecture definition, because the implementors of various different machines interpreted that combination differently. "Orthogonal" implies, to me at least, that the result of executing an opcode is determinable through a set of simple, uniformly-applied rules. At some point I'll have to torture test some of these combos on John Wilson's E11, which claims to faithfully emulate many different -11 models. I imagine John's done a pretty thorough job of testing already, so I probably won't find any problems (though I'm sure I'll find more errors in the _PDP-11 Family Differences_ tables that DEC published.) Does TST -(PC) on all -11's result in an infinite loop? I don't see any comments about autodecrement-PC modes in my books, maybe they figured nobody would be stupid enough to try it. Or maybe I'm just not clever enough to see a use for it! Along those lines: I've never even tried a MUL x,R6 on an EIS PDP-11. Nothing in my books tells me it's prohibited, but it's probably the stupidest thing a programmer could ever try to do :-). (For those who haven't been following the discussion and don't know PDP-11 assembler: MUL to an even-numbered register produces a 32-bit result, going into the register and the next register. R6 and R7 are the SP and PC.) Or maybe it isn't so stupid. I'd probably have to work for weeks to come up with a clever use for MUL R6 :-). > > > Fun. We disagree. Hmmm, maybe we should check if we mean the same > > > thing by "orthogonal"? > > > > I think we mean the same thing by orthogonal, we just don't agree > > what "perfectly orthogonal" is. There probably isn't a CPU that's > > "perfectly" orthogonal, and I don't think that one which was > > would have any advantages over one that's "orthogonal enough". > > Lots of architectures are "orthogonal enough". > > Hm, almost no architecture is even "orthogonal enough". > Atleast not "enough" by my standards. I don't know of > any except some DEC machines, anyway... And I know most micros > some minis, and one or two mainframe architectures. I personally think the 8080 is pretty good in this regard. Of course, I'm looking at orthogonality from the viewpoint of "toggling in instructions on a front panel and having the lights and switches translate to consistent actions by the CPU" viewpoint, not from "the assembler generates the action I meant" viewpoint. Different levels of abstraction to a Z80 programmer, identical levels of abstraction to an 8080 programmer :-). I like 8080 assembly mnemonics because, like PDP-11 mnemonics, the instrution and operand fields translate immediately to lights and switches on the front panel. Tim. ###### From: "Charlie Gibbs" Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Date: 15 May 00 10:46:54 -0800 Organization: http://extra.newsguy.com Lines: 12 Message-ID: <320.170T2708T6465777@sky.bus.com> References: <391C1A43.C4582FB5@netinsight.se> <391BF5EC.4642D331@trailing-edge.com> <391F9BD9.4178CEE5@netinsight.se> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> NNTP-Posting-Host: p-195.newsdawg.com X-Newsreader: THOR 2.5a (Amiga;TCP/IP) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!newshunter!cosy.sbg.ac.at!newsfeed.Austria.EU.net!newscore.univie.ac.at!bignews.mediaways.net!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.berkeley.edu!pln-w!spln!extra.newsguy.com!newsp.newsguy.com!news2 Xref: chonsp.franklin.ch alt.folklore.computers:56304 In article <391FBFAA.1530B784@trailing-edge.com> shoppa@trailing-edge.com (Tim Shoppa) writes: >Or maybe it isn't so stupid. I'd probably have to work for weeks >to come up with a clever use for MUL R6 :-). Copy protection? -- cgibbs@sky.bus.com (Charlie Gibbs) Remove the first period after the "at" sign to reply. ###### Message-ID: <3920055F.C62694FD@netinsight.se> From: Johnny Billquist Organization: Netinsight AB X-Mailer: Mozilla 4.5 [en] (X11; I; Linux 2.2.14 i686) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <8fanf1$ih4@nnrp1.farm.idt.net> <3919F95F.35BBB64F@dallas.net> <958038783.53624@shelley.paradise.net.nz> <391A9257.52DCB66D@netinsight.se> <958084713.291883@shelley.paradise.net.nz> <391B9A17.932A239E@netinsight.se> <391BB60E.487F9FCF@trailing-edge.com> <391BFBE6.BC4122CD@netinsight.se> <391BD096.6A224D5C@trailing-edge.com> <391C1A43.C4582FB5@netinsight.se> <391BF5EC.4642D331@trailing-edge.com> <391F9BD9.4178CEE5@netinsight.se> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Lines: 204 Date: Mon, 15 May 2000 14:10:41 GMT NNTP-Posting-Host: 194.16.221.33 X-Complaints-To: abuse@telia.com X-Trace: newsc.telia.net 958399841 194.16.221.33 (Mon, 15 May 2000 16:10:41 MET DST) NNTP-Posting-Date: Mon, 15 May 2000 16:10:41 MET DST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!newsfeedZ.netscum.dQ!netscum.int!uninett.no!news.ost.eltele.no!newsfeed1.telia.no!masternews.telia.net!newsc.telia.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56326 Tim Shoppa wrote: > > Johnny Billquist wrote: > > > > Tim Shoppa wrote: > > > > > > Johnny Billquist wrote: > > > > > > > > Tim Shoppa wrote: > > > > > > > > > > R6 and R7 aren't really general purpose registers - they're SP and > > > > > PC. > > > > > > > > Well, they no different from any other register from the instructions > > > > point of view. > > > > > > > > SP used with autoincrement or autodecrement always add or substract > > > > two, even if your are accessing bytes. > > > > PC used in mode 7 automatically increment it, even though that > > > > isn't obvious. > > > > > > I'll agree, SP and PC work into the scheme in a pretty slick way, > > > but we both agree that they don't behave *exactly* like R0 through > > > R5. > > > > Yes. But then we are talking about side effects on the register, which > > isn't exactly relevant to the instruction. > > I don't think "autoincrement" and "autodecrement" can be called > side effects. They're fundamental addressing modes. No. But the extra increment on R7 when used in mode 7 (and 4?) is a side effect. The same goes for incrementing/decrementing R6 by two even when accessing byte quantities. MOV (PC)+,R0 don't behave any differently than MOV (R1)+,R0 Even the bit patterns will be conformant. :-) It's just that MOV @x(PC),R0 will also automatically increment the PC, while it will automatically increment any other register so used. It could be argued that any indirect fetching through the PC always auto-increment the PC unless auto-decrement has been specified. That also takes care of the fetch cycle in instruction decoding. But I think that that behaviour is somewhat processor specific. If you do a MOV (PC),R0 I think that some will increment the PC, while others will not. I'd have to check this up, though. But anyway, this definitely is in the side-effect area, which only is relevant for R6 and R7, under special circumstances. > > I'm looking at the instructions, and they are orthogonal. :-) > > Sure, you can write them down, and MACRO-11 will even assemble them, > but that doesn't mean that what they do makes any sense, or that > it's even legal. For example, you can't JMP %R on any PDP-11 > that I'm aware of, it's trapped as an illegal instruction. Actually, there are one or two models where JMP %R is legal. I think it might have been the 11/05, in which code can reside in the registers, and the PC gets incremented by 1 when executing there. But the fact that some instructions don't make sense, or traps because the operation isn't possible is a different issue than the instructions being orthogonal. The instruction as such is perfectly legal, it's the result of executing that instruction which isn't. Just like division by zero is illegal. > And many combinations don't do the same thing on all different PDP-11 > models. For example, OPR PC,@A on a 11/23, 11/15, 11/20, 11/35, or > 11/40 will put (PC of OPR)+4 into location A, while the same instruction > on an 11/03, /04, /05, /10, /34, or /45 will put the (PC of OPR)+2 > into location A. In my book, if an addressing mode/register > combination gives different result on different processors, this makes > it difficult to call it a perfectly orthogonal architecture definition, > because the implementors of various different machines interpreted > that combination differently. "Orthogonal" implies, to me at least, > that the result of executing an opcode is determinable through a > set of simple, uniformly-applied rules. You are mixing in things that I don't consider a part of "orthogonal". The (un)predicted result of some arguments or combination of arguments don't mean the instructions aren't unorthogonal, but that some should be avoided, since the behaviour have been left undefined. That means that all ways can be considered correct, but since you want a deterministic behaviour in your program, you shouldn't use them. There are a lot of ways to get indeterministic behaviour in programs, such as addressing non-existant memory, getting overflow, underflow, and so on... You want to put "deterministic" as a part of "orthogonal" while I don't. Oh well... :-) > At some point I'll have to torture test some of these combos on > John Wilson's E11, which claims to faithfully emulate many different > -11 models. I imagine John's done a pretty thorough job of testing > already, so I probably won't find any problems (though I'm sure I'll > find more errors in the _PDP-11 Family Differences_ tables that DEC > published.) DEC appearantly have several errors in their tables, though I've never bothered to find out. I would probably expect Wilson to get one or another wrong as well, but he has probably done most of it right. > Does TST -(PC) on all -11's result in an infinite loop? I don't see > any comments about autodecrement-PC modes in my books, maybe they > figured nobody would be stupid enough to try it. Or maybe I'm just > not clever enough to see a use for it! I don't think I can see any use for TST -(PC), but the shortest program to get all memory having the same content is MOV -(PC),-(PC) and I believe it does work on all machines, which implies that TST -(PC) also should work on all of them. > Along those lines: > > I've never even tried a MUL x,R6 on an EIS PDP-11. Nothing > in my books tells me it's prohibited, but it's probably the > stupidest thing a programmer could ever try to do :-). I would expect it to do just what you expect, and after you get the result, chances are that you'll be sorry. Odd PC -> odd address trap. Odd SP -> Pretty soon odd address trap. We should try it. Hmmm, I can write a short program to check, just for the heck of it. I can run it on an 11/70 and an 11/84 myself. > Or maybe it isn't so stupid. I'd probably have to work for weeks > to come up with a clever use for MUL R6 :-). Please tell me if you do. That one goes above my head. I did, however, see some code BLISS-11 generated, which was my first case of arithmetic involving the PC. It took a moment to realize what it did, but I was impressed. I'd really like to have BLISS-11 running natively. Anyway, it went like this: MOV CASE,R0 ASL R0 ADD TABLE(R0),PC 1$: 10$: . . . 20$: . . . 30$: . . . TABLE: .WORD 10$-1$ .WORD 20$-1$ .WORD 30$-1$ In case someone wonders about this, it's a very nice way of doing a PIC case statement in PDP-11 assembler. > I personally think the 8080 is pretty good in this regard. Of > course, I'm looking at orthogonality from the viewpoint of > "toggling in instructions on a front panel and having the lights > and switches translate to consistent actions by the CPU" viewpoint, > not from "the assembler generates the action I meant" viewpoint. Well, it's hardly good enough. Take add to A for instance. (I don't know the Intel mnemonic, but no matter). You can add any other 8-bit register to that, or use (HL). But you cannot use (DE) or (BC). Yet, in other instances BC and DE can be used as pointers to memory. But apart from all that, since the registers in the 8080 (or Z80) isn't general, I don't consider orthogonality that interesting. > Different levels of abstraction to a Z80 programmer, identical > levels of abstraction to an 8080 programmer :-). I like 8080 > assembly mnemonics because, like PDP-11 mnemonics, the instrution > and operand fields translate immediately to lights and switches on > the front panel. True. But at the same time, on a PDP-11, you can always directly identify that you are doing a MOV by the bit pattern, while on the 8080, there are a number of different bit patterns which perform that operation, depending on what the source or destination is. It's always nice to be able to go both ways that easily. :-) Johnny -- Johnny Billquist | johnny.billquist@netinsight.net Net Insight AB | phone: +46 8 685 04 88 Västberga Allé 9 | fax: +46 8 685 04 20 Box 42093 | SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.net ###### Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> Organization: Daedalus Consulting X-Newsreader: trn 4.0-test72 (19 April 1999) From: don@news.daedalus.co.nz (Don Stokes) Message-ID: <958400279.905898@shelley.paradise.net.nz> Cache-Post-Path: shelley.paradise.net.nz!unknown@203-96-144-16.cable.paradise.net.nz X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 59 Date: Mon, 15 May 2000 14:18:16 GMT NNTP-Posting-Host: 203.96.152.26 X-Complaints-To: newsadmin@xtra.co.nz X-Trace: news.xtra.co.nz 958400296 203.96.152.26 (Tue, 16 May 2000 02:18:16 NZST) NNTP-Posting-Date: Tue, 16 May 2000 02:18:16 NZST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!newsfeed.berkeley.edu!enews.sgi.com!news.xtra.co.nz!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56420 Tim Shoppa wrote: >Sure, you can write them down, and MACRO-11 will even assemble them, >but that doesn't mean that what they do makes any sense, or that >it's even legal. For example, you can't JMP %R on any PDP-11 >that I'm aware of, it's trapped as an illegal instruction. What's the address of a register? I'd suggest that that this *is* behaving orthogonally; only when the processor finds itself trying to compute the address of something that doesn't have an address does it throw up its hands in horror... (yes, it *could* load 17777r into the PC, but a little reflection on the difference between virtual and physical address spaces will indicate why that would be a dumb idea.) >And many combinations don't do the same thing on all different PDP-11 >models. For example, OPR PC,@A on a 11/23, 11/15, 11/20, 11/35, or >11/40 will put (PC of OPR)+4 into location A, while the same instruction >on an 11/03, /04, /05, /10, /34, or /45 will put the (PC of OPR)+2 >into location A. In my book, if an addressing mode/register ... >Does TST -(PC) on all -11's result in an infinite loop? I don't see >any comments about autodecrement-PC modes in my books, maybe they >figured nobody would be stupid enough to try it. Or maybe I'm just >not clever enough to see a use for it! It should. MOV -(PC),-(PC) makes the PC go backwards on every 11 I know of. This differs from your OPR PC,@A example in that MOV and TST are single word instructions; there's no operand words to confuse the issue. With the OPR PC,@A example, it's not a question of whether the instruction word has been skipped (it has), but whether the PC has been retrieved as the source operand before or after the destination address has been retrieved (and the PC incremented accordingly). >I've never even tried a MUL x,R6 on an EIS PDP-11. Nothing >in my books tells me it's prohibited, but it's probably the >stupidest thing a programmer could ever try to do :-). Oh, I dunno. Hold your mouth right and it could be a rather, uh, interesting implementation of a computed GOTO... >I personally think the 8080 is pretty good in this regard. Of >course, I'm looking at orthogonality from the viewpoint of >"toggling in instructions on a front panel and having the lights >and switches translate to consistent actions by the CPU" viewpoint, >not from "the assembler generates the action I meant" viewpoint. Perhaps. I tend to regard orthogonality as consistent use of registers and and addressing modes. With an orthogonal CPU, if using one register is inconvenient (because it's already holding some thing I need), I can just use another one without thinking about it. With the Z80/8080, this isn't true. I can't just use DE in place of HL, or B instead of A. With the pdp11, if R0 is in use, I can (usually) substitute R3 for R4 with no consequences beyond having to edit the source. For real non-orthogonality, try the 6502. Two 8-bit index registers that work in different ways. Fun. -- don ###### Message-ID: <392009D0.8F49293E@netinsight.se> From: Johnny Billquist Organization: Netinsight AB X-Mailer: Mozilla 4.5 [en] (X11; I; Linux 2.2.14 i686) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> <958400279.905898@shelley.paradise.net.nz> Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Lines: 58 Date: Mon, 15 May 2000 14:29:38 GMT NNTP-Posting-Host: 194.16.221.33 X-Complaints-To: abuse@telia.com X-Trace: newsc.telia.net 958400978 194.16.221.33 (Mon, 15 May 2000 16:29:38 MET DST) NNTP-Posting-Date: Mon, 15 May 2000 16:29:38 MET DST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!newspeer.te.net!news.indigo.ie!diablo.theplanet.net!news.maxwell.syr.edu!uninett.no!newsfeed1.telia.no!masternews.telia.net!newsc.telia.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56323 Don Stokes wrote: > > What's the address of a register? I'd suggest that that this *is* > behaving orthogonally; only when the processor finds itself trying > to compute the address of something that doesn't have an address > does it throw up its hands in horror... > > (yes, it *could* load 17777r into the PC, but a little reflection > on the difference between virtual and physical address spaces will > indicate why that would be a dumb idea.) I think it was the 11/05 that actually allowed this. :-) No other machines does, however. > >I personally think the 8080 is pretty good in this regard. Of > >course, I'm looking at orthogonality from the viewpoint of > >"toggling in instructions on a front panel and having the lights > >and switches translate to consistent actions by the CPU" viewpoint, > >not from "the assembler generates the action I meant" viewpoint. > > Perhaps. I tend to regard orthogonality as consistent use of registers > and and addressing modes. With an orthogonal CPU, if using one register > is inconvenient (because it's already holding some thing I need), I can > just use another one without thinking about it. With the Z80/8080, this > isn't true. I can't just use DE in place of HL, or B instead of A. I'm all with you here, Don. This is exactly the same view that I have. The silly thing with the Intel mnemonics are that they semi-makes it look this way. You have something like ADDA (or whatever the mnemonic is that adds to A) and it can take any of the registers as an argument. The fact that (HL) is regarded as an 8-bit register do make it weak though. But I suspect the Intel mnemonics never mention (DE) or (BC). The loading and storing of A to/from these registers indirect are special instructions without arguments. But the Intel mnemonics probably *do* mention BC and DE along with HL for 16-bit stuff, which begs a person to ask where (BC) and (DE) is. More silly stuff is that PUSH/POP on the 8080 takes AF,BC,DE,HL as argument, while adding to HL takes BC,DE,HL and SP as arguments. Admittedly any other ways might seem silly, but it is a point against the 8080 being un-orthogonal. > With the pdp11, if R0 is in use, I can (usually) substitute R3 for R4 > with no consequences beyond having to edit the source. > > For real non-orthogonality, try the 6502. Two 8-bit index registers > that work in different ways. Fun. The 6502 definitely have a lot of quirks. Johnny -- Johnny Billquist | johnny.billquist@netinsight.net Net Insight AB | phone: +46 8 685 04 88 Västberga Allé 9 | fax: +46 8 685 04 20 Box 42093 | SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.net ###### Message-ID: <391FD771.4AED833@trailing-edge.com> Date: Mon, 15 May 2000 10:54:41 -0400 From: Tim Shoppa Organization: Trailing Edge Technology X-Mailer: Mozilla 3.03Gold (X11; I; OpenVMS V7.0 DEC 3000 Model 300L) MIME-Version: 1.0 Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> <958400279.905898@shelley.paradise.net.nz> <392009D0.8F49293E@netinsight.se> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 20 NNTP-Posting-Host: 63.73.218.130 X-Trace: reader0.news.uu.net 958402482 16872 63.73.218.130 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!tank.news.pipex.net!pipex!do.de.uu.net!f.de.uu.net!zur.uu.net!ffx.uu.net!spool0.news.uu.net!reader0.news.uu.net!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56364 Johnny Billquist wrote: > I'm all with you here, Don. This is exactly the same view that I have. > The silly thing with the Intel mnemonics are that they semi-makes > it look this way. > You have something like ADDA (or whatever the mnemonic is that > adds to A) and it can take any of the registers as an argument. > The fact that (HL) is regarded as an 8-bit register do make it > weak though. But I suspect the Intel mnemonics never mention > (DE) or (BC). The Intel mnemonics don't have (HL), (DE), nor (BC). They *do* have M, which is (HL) in Z80 mnemonics. For someone like me who grew up on 8080 mnemonics and opcodes, they are neat and complete. I've used them long enough that I can't even *think* of any non- existent opcodes if I think in 8080 mnemonics. OK, OK, it's true that MOV M,M doesn't do what you might think, even though some 8080 assemblers accept it! Tim. ###### Message-ID: <39201069.889D5D9D@netinsight.se> From: Johnny Billquist Organization: Netinsight AB X-Mailer: Mozilla 4.5 [en] (X11; I; Linux 2.2.14 i686) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> <958400279.905898@shelley.paradise.net.nz> <392009D0.8F49293E@netinsight.se> <391FD771.4AED833@trailing-edge.com> Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Lines: 24 Date: Mon, 15 May 2000 14:57:45 GMT NNTP-Posting-Host: 194.16.221.33 X-Complaints-To: abuse@telia.com X-Trace: newsc.telia.net 958402665 194.16.221.33 (Mon, 15 May 2000 16:57:45 MET DST) NNTP-Posting-Date: Mon, 15 May 2000 16:57:45 MET DST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!portc03.blue.aol.com!howland.erols.net!uninett.no!newsfeed1.telia.no!masternews.telia.net!newsc.telia.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56325 Tim Shoppa wrote: > > The Intel mnemonics don't have (HL), (DE), nor (BC). They *do* > have M, which is (HL) in Z80 mnemonics. For someone like me who > grew up on 8080 mnemonics and opcodes, they are neat and complete. > I've used them long enough that I can't even *think* of any non- > existent opcodes if I think in 8080 mnemonics. I suspected as much. :-) > OK, OK, it's true that MOV M,M doesn't do what you might think, > even though some 8080 assemblers accept it! Huh? But (in Zilog speech) LD (HL),(HL) is valid, isn't it? Not that meaningful, but valid, I'd say. Johnny -- Johnny Billquist | johnny.billquist@netinsight.net Net Insight AB | phone: +46 8 685 04 88 Västberga Allé 9 | fax: +46 8 685 04 20 Box 42093 | SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.net ###### From: jmaynard@thebrain.conmicro.cx (Jay Maynard) Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> <958400279.905898@shelley.paradise.net.nz> <392009D0.8F49293E@netinsight.se> <391FD771.4AED833@trailing-edge.com> <39201069.889D5D9D@netinsight.se> Reply-To: jmaynard@texas.net Message-ID: User-Agent: slrn/0.9.5.4 (UNIX) Lines: 9 NNTP-Posting-Date: Mon, 15 May 2000 10:06:13 CDT Organization: Giganews.Com - Premium News Outsourcing X-Trace: sv2-eXSwvTPVhmtt6epLQMvSMPV5y1JKSGeFotyrHSFwkB3zxegAWI0gaeHmOy+m3KyQdKcIDIiApsG3kN3!iTaXJwnUUJIvY/xXiTgQ X-Complaints-To: abuse@GigaNews.Com X-Abuse-Info: Please be sure to forward a copy of ALL headers X-Abuse-Info: Otherwise we will be unable to process your complaint properly Date: Mon, 15 May 2000 15:06:13 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!hermes.visi.com!news-out.visi.com!nntp2.giganews.com!nntp3.giganews.com!news6.giganews.com.POSTED!jmaynard Xref: chonsp.franklin.ch alt.folklore.computers:56270 On Mon, 15 May 2000 14:57:45 GMT, Johnny Billquist wrote: >> OK, OK, it's true that MOV M,M doesn't do what you might think, >> even though some 8080 assemblers accept it! >Huh? But (in Zilog speech) LD (HL),(HL) is valid, isn't it? >Not that meaningful, but valid, I'd say. Nope...that opcode is HLT. (I have no idea why Intel stuck it there, though...) ###### Message-ID: <391FE0A6.63E77169@trailing-edge.com> Date: Mon, 15 May 2000 11:33:58 -0400 From: Tim Shoppa Organization: Trailing Edge Technology X-Mailer: Mozilla 3.03Gold (X11; I; OpenVMS V7.0 DEC 3000 Model 300L) MIME-Version: 1.0 Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> <958400279.905898@shelley.paradise.net.nz> <392009D0.8F49293E@netinsight.se> <391FD771.4AED833@trailing-edge.com> <39201069.889D5D9D@netinsight.se> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 26 NNTP-Posting-Host: 63.73.218.130 X-Trace: reader0.news.uu.net 958404839 16872 63.73.218.130 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!tank.news.pipex.net!pipex!ams.uu.net!nyc.uu.net!ffx.uu.net!spool0.news.uu.net!reader0.news.uu.net!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56374 Johnny Billquist wrote: > > Tim Shoppa wrote: > > > > The Intel mnemonics don't have (HL), (DE), nor (BC). They *do* > > have M, which is (HL) in Z80 mnemonics. For someone like me who > > grew up on 8080 mnemonics and opcodes, they are neat and complete. > > I've used them long enough that I can't even *think* of any non- > > existent opcodes if I think in 8080 mnemonics. > > I suspected as much. :-) > > > OK, OK, it's true that MOV M,M doesn't do what you might think, > > even though some 8080 assemblers accept it! > > Huh? But (in Zilog speech) LD (HL),(HL) is valid, isn't it? Only in the same sense that JMP %register is valid on a PDP-11. i.e. an assembler may let you write it and even issue the matching opcode (76 hex), but the CPU won't do with it what you think it'll do. The 8080/Z80 opcode 76 hex - which you might expect to be LD (HL),(HL) or MOV M,M - is actually HALT. I don't know what happens if you precede it with a IX+offset or IY+offset prefix on a Z80. Tim. ###### Message-ID: <391FE2D6.6E4F77EE@trailing-edge.com> Date: Mon, 15 May 2000 11:43:18 -0400 From: Tim Shoppa Organization: Trailing Edge Technology X-Mailer: Mozilla 3.03Gold (X11; I; OpenVMS V7.0 DEC 3000 Model 300L) MIME-Version: 1.0 Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> <958400279.905898@shelley.paradise.net.nz> <392009D0.8F49293E@netinsight.se> <391FD771.4AED833@trailing-edge.com> <39201069.889D5D9D@netinsight.se> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 24 NNTP-Posting-Host: 63.73.218.130 X-Trace: reader0.news.uu.net 958405399 16872 63.73.218.130 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!newsfeed.mathworks.com!news.mathworks.com!uunet!nyc.uu.net!ffx.uu.net!spool0.news.uu.net!reader0.news.uu.net!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56383 Jay Maynard wrote: > > On Mon, 15 May 2000 14:57:45 GMT, Johnny Billquist > wrote: > >> OK, OK, it's true that MOV M,M doesn't do what you might think, > >> even though some 8080 assemblers accept it! > >Huh? But (in Zilog speech) LD (HL),(HL) is valid, isn't it? > >Not that meaningful, but valid, I'd say. > > Nope...that opcode is HLT. (I have no idea why Intel stuck it there, > though...) I believe the 8080 micromachine is incapable of a memory-indirect to memory-indirect operation - that data path simply doesn't exist. OK, it's even more complicated than just a data path, you'd need to special-case this kind of move from all the others into a new sequence with a temporary register that isn't otherwise used. If you were hurting for new opcodes on an 8080 successor you might think about using other apparent NOP's like MOV A,A (aka LD A,A), but Zilog didn't do this, they resorted to prefix bytes in many cases. Tim. ###### Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FEE45.CED408A2@netinsight.se> <391FBF <3920055F.C62694FD@netinsight.se> Organization: D Bit, Troy, NY From: wilson@dbit.com (John Wilson) NNTP-Posting-Host: dbit.dbit.com X-Original-NNTP-Posting-Host: dbit.dbit.com Message-ID: <39203194_1@news.wizvax.net> Date: 15 May 2000 13:19:16 -0400 X-Trace: 15 May 2000 13:19:16 -0400, dbit.dbit.com Lines: 18 XPident: wilson X-Original-NNTP-Posting-Host: 199.181.141.3 XPident: news Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!newshunter!cosy.sbg.ac.at!newsfeed.Austria.EU.net!nmaster.kpnqwest.net!npeer.kpnqwest.net!blackbush.xlink.net!news0.de.colt.net!colt.net!diablo.netcom.net.uk!netcom.net.uk!newsfeed.wizvax.net!news.wizvax.net!dbit.com!wilson Xref: chonsp.franklin.ch alt.folklore.computers:56279 In article <3920055F.C62694FD@netinsight.se>, Johnny Billquist wrote: >> I've never even tried a MUL x,R6 on an EIS PDP-11. Nothing >> in my books tells me it's prohibited, but it's probably the >> stupidest thing a programmer could ever try to do :-). > >I would expect it to do just what you expect, and after you >get the result, chances are that you'll be sorry. Odd PC -> >odd address trap. Odd SP -> Pretty soon odd address trap. I'm pretty sure I remember running into a MAINDEC that does this and depends on things landing in the right place. Pretty obnoxious!!! But if you choose your numbers right, of course it will work, just the same way you can ADD foo,PC or CLR PC, DEC was definitely serious about the PC being a general register (even the DCJ11 won't go off and execute prefetched code if you CLR PC). John Wilson D Bit ###### Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 From: no-uce@world.std.com Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Sender: news@world.std.com (Mr Usenet Himself) Message-ID: <3920718e.2838415014@news.std.com> Date: Mon, 15 May 2000 21:55:42 GMT References: <8fanf1$ih4@nnrp1.farm.idt.net> <3919F95F.35BBB64F@dallas.net> <958038783.53624@shelley.paradise.net.nz> <391A9257.52DCB66D@netinsight.se> <958084713.291883@shelley.paradise.net.nz> <391B9A17.932A239E@netinsight.se> <391BB60E.487F9FCF@trailing-edge.com> <391BFBE6.BC4122CD@netinsight.se> <391BD096.6A224D5C@trailing-edge.com> <391C1A43.C4582FB5@netinsight.se> <391BF5EC.4642D331@trailing-edge.com> <391F9BD9.4178CEE5@netinsight.se> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight NNTP-Posting-Host: ppp0a110.std.com Organization: The World @ Software Tool & Die X-Newsreader: Forte Free Agent 1.21/32.243 Lines: 24 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.datacomm.ch!newsmaster-01.atnet.at!atnet.at!newsrouter.chello.at!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!newsfeed.wirehub.nl!newsfeed.wirehub.nl!hermes.visi.com!news-out.visi.com!uunet!ffx.uu.net!world!news Xref: chonsp.franklin.ch alt.folklore.computers:56310 >> Hm, almost no architecture is even "orthogonal enough". >> Atleast not "enough" by my standards. I don't know of >> any except some DEC machines, anyway... And I know most micros >> some minis, and one or two mainframe architectures. > >I personally think the 8080 is pretty good in this regard. Of Not really. You can load the SP directly but you cant save it except by adding it to a zeroed HL. Z80 improved on that. >Different levels of abstraction to a Z80 programmer, identical >levels of abstraction to an 8080 programmer :-). I like 8080 >assembly mnemonics because, like PDP-11 mnemonics, the instrution >and operand fields translate immediately to lights and switches on >the front panel. the more generic naming of the z80 is annoying as you can generate an instruction that would seem possible but is not in the instruction set. I'd say the PDP-11, ti9900 are most orthougnal of the 16bit set. of the 8bitters z80, better yet z280 would fit. Allison ###### Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 From: no-uce@world.std.com Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Sender: news@world.std.com (Mr Usenet Himself) Message-ID: <392072bb.2838716228@news.std.com> Date: Mon, 15 May 2000 21:59:30 GMT References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> <958400279.905898@shelley.paradise.net.nz> <392009D0.8F49293E@netinsight.se> <391FD771.4AED833@trailing-edge.com> <39201069.889D5D9D@netinsight.se> <391FE2D6.6E4F77EE@trailing-edge.com> NNTP-Posting-Host: ppp0a110.std.com Organization: The World @ Software Tool & Die X-Newsreader: Forte Free Agent 1.21/32.243 Lines: 14 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!tank.news.pipex.net!pipex!ams.uu.net!ffx.uu.net!world!news Xref: chonsp.franklin.ch alt.folklore.computers:56318 >I believe the 8080 micromachine is incapable of a memory-indirect to >memory-indirect operation - that data path simply doesn't exist. Big time correct, z80 cant within limites either. >OK, it's even more complicated than just a data path, you'd need to >special-case this kind of move from all the others into a new >sequence with a temporary register that isn't otherwise used. Likely the most interesting PDP11 addressing mode that is missing in most 8bitters is indexed indirect mode. this makes most compilers Esp C very efficient but, C on 8080/z80 gens a lot of code to do that. Allison ###### Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 From: mbg@world.std.com (Megan) Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Message-ID: Date: Tue, 16 May 2000 01:47:13 GMT References: <8fanf1$ih4@nnrp1.farm.idt.net> <3919F95F.35BBB64F@dallas.net> <958038783.53624@shelley.paradise.net.nz> <391A9257.52DCB66D@netinsight.se> <958084713.291883@shelley.paradise.net.nz> <391B9A17.932A239E@netinsight.se> <391BB60E.487F9FCF@trailing Organization: The World Public Access UNIX, Brookline, MA Lines: 29 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!newsfeed.mathworks.com!nycmny1-snh1.gtei.net!news.gtei.net!hermes.visi.com!news-out.visi.com!uunet!ffx.uu.net!world!mbg Xref: chonsp.franklin.ch alt.folklore.computers:56275 Tim Shoppa writes: >it's even legal. For example, you can't JMP %R on any PDP-11 >that I'm aware of, it's trapped as an illegal instruction. (answering several posts at once) Yes you can... on the 11/05,10... you can jump to the registers. When code is executed from registers on the 11/05,10, the PC increments by 1, not 2. The addresses of the registers are 177700 - 177707 (for R0 - PC) but there are also several additional registers which save information about the decoded instruction (I wonder how many of the 11/05,10 implementations get this correct)... Those registers are 177710 - 177715 (IIRC)... Megan Gentry Former RT-11 Developer +--------------------------------+-------------------------------------+ | Megan Gentry, EMT/B, PP-ASEL | Internet (work): gentry!zk3.dec.com | | Unix Support Engineering Group | (home): mbg!world.std.com | | Compaq Computer Corporation | addresses need '@' in place of '!' | | 110 Spitbrook Rd. ZK03-2/T43 | URL: http://world.std.com/~mbg/ | | Nashua, NH 03062 | "pdp-11 programmer - some assembler | | (603) 884 1055 | required." - mbg | +--------------------------------+-------------------------------------+ ###### Message-ID: <39207220.17031AAB@trailing-edge.com> Date: Mon, 15 May 2000 21:54:41 -0400 From: Tim Shoppa Organization: Trailing Edge Technology X-Mailer: Mozilla 3.03Gold (X11; I; OpenVMS V7.0 DEC 3000 Model 300L) MIME-Version: 1.0 Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <8fanf1$ih4@nnrp1.farm.idt.net> <3919F95F.35BBB64F@dallas.net> <958038783.53624@shelley.paradise.net.nz> <391A9257.52DCB66D@netinsight.se> <958084713.291883@shelley.paradise.net.nz> <391B9A17.932A239E@netinsight.se> <391BB60E.487F9FCF@trailing Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 13 NNTP-Posting-Host: 63.73.218.130 X-Trace: reader2.news.uu.net 958442082 26531 63.73.218.130 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!newsfeed.icl.net!diablo.theplanet.net!iol.ie!newsfeed2.news.nl.uu.net!sun4nl!ams.uu.net!ffx.uu.net!spool0.news.uu.net!reader2.news.uu.net!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56362 Megan wrote: > > Tim Shoppa writes: > >it's even legal. For example, you can't JMP %R on any PDP-11 > >that I'm aware of, it's trapped as an illegal instruction. > > (answering several posts at once) > > Yes you can... on the 11/05,10... you can jump to the registers. You can, but not with JMP %R. It traps to 4. Try it, I just did. Tim. ###### Message-ID: <3920BCFF.75040C79@boutel.co.nz> From: Brian Boutel Organization: X X-Mailer: Mozilla 4.7 [en] (Win98; U) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <8fanf1$ih4@nnrp1.farm.idt.net> <3919F95F.35BBB64F@dallas.net> <958038783.53624@shelley.paradise.net.nz> <391A9257.52DCB66D@netinsight.se> <958084713.291883@shelley.paradise.net.nz> <391B9A17.932A239E@netinsight.se> <391BB60E.487F9FCF@trailing <39207220.17031AAB@trailing-edge.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cache-Post-Path: shelley.paradise.net.nz!unknown@boutel.co.nz X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 28 Date: Tue, 16 May 2000 15:14:07 +1200 NNTP-Posting-Host: 203.96.152.26 X-Complaints-To: newsadmin@xtra.co.nz X-Trace: news.xtra.co.nz 958446847 203.96.152.26 (Tue, 16 May 2000 15:14:07 NZST) NNTP-Posting-Date: Tue, 16 May 2000 15:14:07 NZST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!feed2.news.luth.se!luth.se!skynet.be!newsfeedZ.netscum.dQ!netscum.int!enews.sgi.com!news.xtra.co.nz!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56287 Tim Shoppa wrote: > > Megan wrote: > > > > Tim Shoppa writes: > > >it's even legal. For example, you can't JMP %R on any PDP-11 > > >that I'm aware of, it's trapped as an illegal instruction. > > > > (answering several posts at once) > > > > Yes you can... on the 11/05,10... you can jump to the registers. > > You can, but not with JMP %R. It traps to 4. Try it, I just did. > > Tim. And the book supports you. PDPll 04/05/10/35/40/45 processor handbook 1975-76 says, (and the isp confirms): Execution of a jump with mode O will cause an "illegal instruction" condition. (Program control cannot be transferred to a register.) Doesn't "illegal instruction" trap to 8 though? --brian ###### From: John Holden Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Date: Tue, 16 May 2000 13:27:50 +1000 Organization: University of Sydney, Australia Lines: 47 Message-ID: <3920C036.C43DF90D@psychwarp.psych.usyd.edu.au> References: <8fanf1$ih4@nnrp1.farm.idt.net> <3919F95F.35BBB64F@dallas.net> <958038783.53624@shelley.paradise.net.nz> <391A9257.52DCB66D@netinsight.se> <958084713.291883@shelley.paradise.net.nz> <391B9A17.932A239E@netinsight.se> <391BB60E.487F9FCF@trailing Reply-To: johnh@psych.usyd.edu.au NNTP-Posting-Host: psychalpha.psych.usyd.edu.au Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: metro.ucc.usyd.edu.au 958447671 12962 129.78.83.6 (16 May 2000 03:27:51 GMT) X-Complaints-To: usenet@news.usyd.edu.au NNTP-Posting-Date: 16 May 2000 03:27:51 GMT X-Mailer: Mozilla 4.7 [en] (X11; I; OSF1 V4.0 alpha) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!intgwpad.nntp.telstra.net!news1.optus.net.au!optus!news.usyd.edu.au!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56443 Megan wrote: > > Tim Shoppa writes: > >it's even legal. For example, you can't JMP %R on any PDP-11 > >that I'm aware of, it's trapped as an illegal instruction. > > (answering several posts at once) > > Yes you can... on the 11/05,10... you can jump to the registers. > When code is executed from registers on the 11/05,10, the PC > increments by 1, not 2. The addresses of the registers are > > 177700 - 177707 (for R0 - PC) > > but there are also several additional registers which save > information about the decoded instruction (I wonder how many > of the 11/05,10 implementations get this correct)... > > Those registers are 177710 - 177715 (IIRC)... > You couldn't jump to a register (ie JMP R4), but the register file is decoded as a valid Unibus address from 0177700-177707, and you could execute instructions in these locations. Very handy to scope out memory faults. 0177700 0057153 tst (r3) ; read location pointed to by r5 0177701 000240 nop ; do nothing, needed because of branch 0177702 000777 br .-2 ; goes to 177700 0177703 xxxxxx ; address of test location Start execution at 0177700. Note that the CPU will allow an odd PC value (normally a byte) as a true 16 bit address. The registers are stored in the SPM (scratch pad memory) as follows :- R0-R5 General Registers R6 Stack Pointer R7 Program Counter R8,R9 Unused R10 Source operand storage R11 Destination operand storage R12 Interrupt vector R13-R16 Unused R17 Load address storage All in 256 microcode instructions (40 bits wide)! ###### From: Michael Davidson Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Date: Mon, 15 May 2000 21:59:10 -0700 Organization: SCO Lines: 19 Message-ID: <3920D59E.37E968BC@sco.com> References: <8fanf1$ih4@nnrp1.farm.idt.net> <3919F95F.35BBB64F@dallas.net> <958038783.53624@shelley.paradise.net.nz> <391A9257.52DCB66D@netinsight.se> <958084713.291883@shelley.paradise.net.nz> <391B9A17.932A239E@netinsight.se> <391BB60E.487F9FCF@trailing <39207220.17031AAB@trailing-edge.com> <3920BCFF.75040C79@boutel.co.nz> Reply-To: md@sco.com NNTP-Posting-Host: nermal.sco.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.5 [en] (Win95; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!newshunter!cosy.sbg.ac.at!newsfeed.Austria.EU.net!nmaster.kpnqwest.net!npeer.kpnqwest.net!howland.erols.net!news.pbi.net.MISMATCH!cyclone-transit.snfc21.pbi.net!132.147.128.45!hobbes.sco.com!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56445 Brian Boutel wrote: > > And the book supports you. > PDPll 04/05/10/35/40/45 processor handbook 1975-76 says, (and the isp > confirms): > > Execution of a jump with mode O will cause an "illegal instruction" > condition. (Program control cannot be transferred to a register.) > > Doesn't "illegal instruction" trap to 8 though? "8" ... what the heck kind of a number is "8" ???? oh ... OK ... you mean "10" don't you ... According to Appendix D (PDP-11 family differences) of the Microcomputers and Memories handbook only the 11/45 traps to 10 for this particular error - everything else traps to 4.. ###### From: bruce+usenet2@NOSPAMfanboy.net (Bruce Tomlin) Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Message-ID: References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> <958400279.905898@shelley.paradise.net.nz> <392009D0.8F49293E@netinsight.se> <391FD771.4AED833@trailing-edge.com> <39201069.889D5D9D@netinsight.se> <391FE2D6.6E4F77EE@trailing-edge.com> <392072bb.2838716228@news.std.com> Organization: San Antonio, TX Lines: 16 NNTP-Posting-Date: Tue, 16 May 2000 00:22:06 CDT X-Trace: sv2-TuG5e8bVz2ZJeizHdR4PQ8UG5EY0+3AKLAmpsSzCp8A9L5TO35tmBkejsXT81imnpMuC7jL+0+sxd+g!EcVsSDRYpKH4O5/2+QI= X-Complaints-To: abuse@GigaNews.Com X-Abuse-Info: Please be sure to forward a copy of ALL headers X-Abuse-Info: Otherwise we will be unable to process your complaint properly Date: Tue, 16 May 2000 00:22:57 -0500 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!cyclone.bc.net!newsfeed.direct.ca!nntp.giganews.com!nntp3.giganews.com!news5.giganews.com.POSTED!atuin.bruce!user Xref: chonsp.franklin.ch alt.folklore.computers:56427 In article <392072bb.2838716228@news.std.com>, no-uce@world.std.com wrote: > Likely the most interesting PDP11 addressing mode that is missing in > most 8bitters is indexed indirect mode. this makes most compilers > Esp C very efficient but, C on 8080/z80 gens a lot of code to do that. In comparison, the 6809 is rich in indexed modes. So much so that the Forth inner loop can be done in two instructions, where it takes like 15 or so on an 8080/Z80. And while it's not quite as orthogonal as CPUs with numbered registers, it's more so than the Z80 is. -- "God uses a Z80 when He can't get a 6809" -- old bumper sticker I saw back in the mid '80s ###### Message-ID: <3920DCD4.DEC6B41F@netinsight.se> From: Johnny Billquist Organization: Netinsight AB X-Mailer: Mozilla 4.5 [en] (X11; I; Linux 2.2.14 i686) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <8fanf1$ih4@nnrp1.farm.idt.net> <3919F95F.35BBB64F@dallas.net> <958038783.53624@shelley.paradise.net.nz> <391A9257.52DCB66D@netinsight.se> <958084713.291883@shelley.paradise.net.nz> <391B9A17.932A239E@netinsight.se> <391BB60E.487F9FCF@trailing <39207220.17031AAB@trailing-edge.com> <3920BCFF.75040C79@boutel.co.nz> <3920D59E.37E968BC@sco.com> Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Lines: 36 Date: Tue, 16 May 2000 05:29:56 GMT NNTP-Posting-Host: 194.16.221.33 X-Complaints-To: abuse@telia.com X-Trace: newsc.telia.net 958454996 194.16.221.33 (Tue, 16 May 2000 07:29:56 MET DST) NNTP-Posting-Date: Tue, 16 May 2000 07:29:56 MET DST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!newsfeedZ.netscum.dQ!netscum.int!uninett.no!newsfeed1.telia.no!masternews.telia.net!newsc.telia.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56342 Michael Davidson wrote: > > Brian Boutel wrote: > > > > And the book supports you. > > PDPll 04/05/10/35/40/45 processor handbook 1975-76 says, (and the isp > > confirms): > > > > Execution of a jump with mode O will cause an "illegal instruction" > > condition. (Program control cannot be transferred to a register.) > > > > Doesn't "illegal instruction" trap to 8 though? > > "8" ... what the heck kind of a number is "8" ???? > > oh ... OK ... you mean "10" don't you ... He must be an IBMmer in disguise. Talking HEX and all... :-) > According to Appendix D (PDP-11 family differences) of the > Microcomputers and Memories handbook only the 11/45 traps > to 10 for this particular error - everything else traps to 4.. "Odd address, or other trap 4" like the old saying goes. Trap 4 is a kind of "everything else" trap. If a processor don't have a more specific trap address for a certain kind of error, it will go through trap 4. Johnny -- Johnny Billquist | johnny.billquist@netinsight.net Net Insight AB | phone: +46 8 685 04 88 Västberga Allé 9 | fax: +46 8 685 04 20 Box 42093 | SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.net ###### From: "Geoffrey G. Rochat" Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Date: Tue, 16 May 2000 11:23:50 -0400 Organization: Kersur Technologies Lines: 8 Message-ID: <8frp38$e3g$1@news.kersur.net> References: <8fanf1$ih4@nnrp1.farm.idt.net> <3919F95F.35BBB64F@dallas.net> <958038783.53624@shelley.paradise.net.nz> <391A9257.52DCB66D@netinsight.se> <958084713.291883@shelley.paradise.net.nz> <391B9A17.932A239E@netinsight.se> <391BB60E.487F9FCF@trailing NNTP-Posting-Host: nas-74-106.boston.navipath.net X-Trace: news.kersur.net 958490536 14448 216.67.74.106 (16 May 2000 15:22:16 GMT) X-Complaints-To: usenet@kersur.net NNTP-Posting-Date: 16 May 2000 15:22:16 GMT X-Newsreader: Microsoft Outlook Express 4.72.3110.1 X-MimeOLE: Produced By Microsoft MimeOLE V4.72.3110.3 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!newspeer.te.net!news.indigo.ie!diablo.theplanet.net!newsfeed.icl.net!diablo.netcom.net.uk!netcom.net.uk!tank.news.pipex.net!pipex!ams.uu.net!ffx.uu.net!news.kersur.net!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56346 A general question open to all PDP-11 folks (ie; "Thems what knows."): What happens if you use R7 in auto-decrement or auto-decrement-deferred mode (mode 4 or 5)? And does this vary by model number, source vs. destination address, etc.? My copy of the "PDP-1104/05/10/35/40/45 Processor Handbook", circa 1975, very carefully skirts this issue. ###### From: Michael Davidson Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Date: Tue, 16 May 2000 09:27:30 -0700 Organization: SCO Lines: 30 Message-ID: <392176F2.92B9F8BC@sco.com> References: <8fanf1$ih4@nnrp1.farm.idt.net> <3919F95F.35BBB64F@dallas.net> <958038783.53624@shelley.paradise.net.nz> <391A9257.52DCB66D@netinsight.se> <958084713.291883@shelley.paradise.net.nz> <391B9A17.932A239E@netinsight.se> <391BB60E.487F9FCF@trailing <8frp38$e3g$1@news.kersur.net> Reply-To: md@sco.com NNTP-Posting-Host: nermal.sco.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.5 [en] (Win95; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!newspeer.te.net!news.indigo.ie!diablo.theplanet.net!europa.netcrusader.net!205.252.116.205!howland.erols.net!news.pbi.net.MISMATCH!cyclone-transit.snfc21.pbi.net!132.147.128.45!hobbes.sco.com!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56444 "Geoffrey G. Rochat" wrote: > > A general question open to all PDP-11 folks (ie; "Thems what knows."): > What happens if you use R7 in auto-decrement or auto-decrement-deferred > mode (mode 4 or 5)? And does this vary by model number, source vs. > destination address, etc.? My copy of the "PDP-1104/05/10/35/40/45 > Processor Handbook", circa 1975, very carefully skirts this issue. What happens is "exactly what you would expect to happen" ... For example there is the single instruction self-replicating program: 014747 MOV -(%7),-(%7) which will copy itself down in memory There is also a single instruction "fill all of memory" program: 015720 MOV @-(%7),(%0)+ which fills memory starting at whatever address R0 points to with the contents of address 015720 OK, it isn't *quite* a single instruction program since you have to load R0 with a value and set up the contents of location 015720, but it's *close* ;-) If you set both R0 and 015720 to 0 and put the 015720 instruction in the last address in memory then this is a neat "clear memory" program which wipes itself out and halts cleanly. ###### From: Michael Davidson Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Date: Tue, 16 May 2000 09:44:37 -0700 Organization: SCO Lines: 24 Message-ID: <39217AF5.71209DB@sco.com> References: <8fanf1$ih4@nnrp1.farm.idt.net> <3919F95F.35BBB64F@dallas.net> <958038783.53624@shelley.paradise.net.nz> <391A9257.52DCB66D@netinsight.se> <958084713.291883@shelley.paradise.net.nz> <391B9A17.932A239E@netinsight.se> <391BB60E.487F9FCF@trailing <8frp38$e3g$1@news.kersur.net> <392176F2.92B9F8BC@sco.com> Reply-To: md@sco.com NNTP-Posting-Host: nermal.sco.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.5 [en] (Win95; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!howland.erols.net!news.pbi.net.MISMATCH!cyclone-transit.snfc21.pbi.net!132.147.128.45!hobbes.sco.com!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56437 Michael Davidson wrote: > > > For example there is the single instruction self-replicating program: > > 014747 MOV -(%7),-(%7) > > which will copy itself down in memory > > There is also a single instruction "fill all of memory" program: > > 015720 MOV @-(%7),(%0)+ > > which fills memory starting at whatever address R0 points to > with the contents of address 015720 > Something which I forgot to mention is that, to the best of my knowledge, these are perfectly well defined instructions which will work in exactly the same way on any PDP-11. What will vary with different processors is the precise manner in which things like the "self-replicating program" will trap after it has written to address 0. ###### From: "Adrian Lumsden" Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Date: Tue, 16 May 2000 18:33:50 +0100 Organization: XDT Computer Systems Ltd. Lines: 33 Message-ID: <8fs0vl$e57$1@newsg1.svr.pol.co.uk> References: <8fanf1$ih4@nnrp1.farm.idt.net> <3919F95F.35BBB64F@dallas.net> <958038783.53624@shelley.paradise.net.nz> <391A9257.52DCB66D@netinsight.se> <958084713.291883@shelley.paradise.net.nz> <391B9A17.932A239E@netinsight.se> <391BB60E.487F9FCF@trailing <8frp38$e3g$1@news.kersur.net> Reply-To: "Adrian Lumsden" NNTP-Posting-Host: modem-201.fluorine.dialup.pol.co.uk X-Trace: newsg1.svr.pol.co.uk 958498613 14503 62.136.8.201 (16 May 2000 17:36:53 GMT) NNTP-Posting-Date: 16 May 2000 17:36:53 GMT X-Complaints-To: abuse@theplanet.net X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2615.200 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!diablo.theplanet.net!news.theplanet.net!newspost.theplanet.net!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56392 I only remember finding two uses for -(PC). One was planting 014747, MOV -(PC), -(PC), in memory with ODT and then starting from that location. It was a useful trick for zapping memory quickly. The other was something to do with the challenge to write a routine which would completely zero all of memory. This reduces down to "How do I get rid of the last few words?" I remember figuring it out but not how it was done. It depended on planting an instruction at the address formed by it's opcode and executing it. I seem to remember the address and opcode started 015... Anybody know if this trick can be done for other architectures? Adrian -- Adrian Lumsden, XDT Computer Systems, UK A dot Lumsden at xdt dot co dot uk Geoffrey G. Rochat wrote in message news:8frp38$e3g$1@news.kersur.net... > A general question open to all PDP-11 folks (ie; "Thems what knows."): > What happens if you use R7 in auto-decrement or auto-decrement-deferred > mode (mode 4 or 5)? And does this vary by model number, source vs. > destination address, etc.? My copy of the "PDP-1104/05/10/35/40/45 > Processor Handbook", circa 1975, very carefully skirts this issue. > > > ###### X-Originating-Host: 157.190.12.105 Organization: http://www.remarq.com: The World's Usenet/Discussions Start Here Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Lines: 32 From: Keith Gaughan Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Message-ID: <04b3f5d3.1a49ed11@usw-ex0103-019.remarq.com> References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> <958400279.905898@shelley.paradise.net.nz> <392009D0.8F49293E@netinsight.se> <391FD771.4AED833@trailing-edge.com> <39201069.889D5D9D@netinsight.se> <391FE2D6.6E4F77EE@trailing-edge.com> <392072bb.2838716228@news.std.com> Bytes: 1147 X-Wren-Trace: eMzpwcDZntSfh93N3YTKxMvY1MjH6JXbwc/MgcbX2MySn9uDk9WJjJGfhpiS2Q== Date: Tue, 16 May 2000 11:56:24 -0700 NNTP-Posting-Host: 10.0.2.19 X-Complaints-To: wrenabuse@remarq.com X-Trace: WReNphoon4 958503457 10.0.2.19 (Tue, 16 May 2000 11:57:37 PDT) NNTP-Posting-Date: Tue, 16 May 2000 11:57:37 PDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news-fra1.dfn.de!news0.de.colt.net!colt.net!news-lond.gip.net!news-peer.gip.net!news.gsl.net!gip.net!cpk-news-hub1.bbnplanet.com!crtntx1-snh1.gtei.net!news.gtei.net!news-feeder.wcg.net!WCG!sn-xit-01!supernews.com!sn-inject-01!WReNclone!WReNphoon4.POSTED!WReN!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56426 In article , bruce+usenet2@NOSPAMfanboy.net (Bruce Tomlin) wrote: > In article <392072bb.2838716228@news.std.com>, > no-uce@world.std.com wrote: > > In comparison, the 6809 is rich in indexed modes. So much so > that the Forth inner loop can be done in two instructions, > where it takes like 15 or so on an 8080/Z80. > > And while it's not quite as orthogonal as CPUs with numbered > registers, it's more so than the Z80 is. Orthogonal is what you'd call a distant relative of the 6809 - the ARM. Damned funky instruction set, especially on the old ARM2s and ARM3s. >-- > "God uses a Z80 when He can't get a 6809" -- old bumper > sticker I saw back in the mid '80s The 6800 family and all their kin are pretty damned good pedigree, but look at what the Z80 is related to... K. -- In the land of the blind, the one-eyed man is murdered for heresy. mailto: keithgaughan AG yahoo STAD com ; ag = @ and stad = . * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free! ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Date: 16 May 2000 23:08:45 +0200 Organization: My own Private Self Lines: 50 Message-ID: <6uzopqfbj6.fsf@chonsp.franklin.ch> References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> <958400279.905898@shelley.paradise.net.nz> <392009D0.8F49293E@netinsight.se> <391FD771.4AED833@trailing-edge.com> <39201069.889D5D9D@netinsight.se> <391FE2D6.6E4F77EE@trailing-edge.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 958511330 794 10.0.3.2 (16 May 2000 21:08:50 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 16 May 2000 21:08:50 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch alt.folklore.computers:56453 Tim Shoppa writes: > Jay Maynard wrote: > > > > On Mon, 15 May 2000 14:57:45 GMT, Johnny Billquist > > wrote: > > >> OK, OK, it's true that MOV M,M doesn't do what you might think, > > >Huh? But (in Zilog speech) LD (HL),(HL) is valid, isn't it? > > > > Nope...that opcode is HLT. (I have no idea why Intel stuck it there, > > I believe the 8080 micromachine is incapable of a memory-indirect to > memory-indirect operation - that data path simply doesn't exist. > OK, it's even more complicated than just a data path, you'd need to > special-case this kind of move from all the others into a new > sequence with a temporary register that isn't otherwise used. Its definitely neither the data path (its simply in and out on the data bus), nor the special case of registers (any MOV d,s does s->temp and temp->d because the 8080s internal register file is single ported (so says this partial reprint of an Intel document I have here, in Rodney Zaks "Programming the Z80")). So it can only be something to do with the state machine used for instruction decoding. Or simply an silly scrunching on opcodes. > If you were hurting for new opcodes on an 8080 successor > you might think about using other apparent NOP's like MOV A,A (aka LD > A,A), But as Intel had still 12 unused opcodes that is certainly not the reason. Now why Intel did not make MOV d,s into 00dddsss and then have ADDA A as its NOP (instead of an special instruction). Just a messy design I suppose, but they were training for the 80x86:-). > but Zilog didn't do this, they resorted to prefix bytes in many > cases. They had _way_ more than 12 new instruction variants. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, Mystic Use a WIMP (Windows Icons Mouse Pulldowns) interface - or get one with a CLUE (Command Line User Environment)? ###### From: mwilson@the-wire.com (Mel Wilson) Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality Message-ID: References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> <958400279.905898@shelley.paradise.net.nz> <392009D0.8F49293E@netinsight.se> <391FD771.4AED833@trailing-edge.com> <39201069.889D5D9D@netinsight.se> <391FE2D6.6E4F77EE@trailing-edge.com> <6uzopqfbj6.fsf@chonsp.franklin.ch> Lines: 9 X-Newsreader: VSoup v1.2.9.37Beta [95/NT] Date: Wed, 17 May 2000 09:31:49 -0400 NNTP-Posting-Host: 205.206.39.144 X-Trace: nnrp1.uunet.ca 958575671 205.206.39.144 (Wed, 17 May 2000 11:01:11 EDT) NNTP-Posting-Date: Wed, 17 May 2000 11:01:11 EDT Organization: UUNET Canada News Reader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news-fra1.dfn.de!news0.de.colt.net!colt.net!newspeer.clara.net!news.clara.net!ldn-newsfeed.speedport.net!newsfeed.speedport.net!diablo.theplanet.net!news.maxwell.syr.edu!newsfeed.cwix.com!prairie.attcanada.net!newsfeed.attcanada.net!142.77.1.188!news.uunet.ca!nnrp1.uunet.ca.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56488 In article <6uzopqfbj6.fsf@chonsp.franklin.ch>, Neil Franklin wrote: >Now why Intel did not make MOV d,s into 00dddsss and then have ADDA A >as its NOP (instead of an special instruction). Just a messy design I >suppose, but they were training for the 80x86:-). ADDA A will change the status flags. Regards. Mel. ###### Message-ID: <3922D15B.78F3F0F2@jetnet.ab.ca> Date: Wed, 17 May 2000 11:05:31 -0600 From: Ben Franchuk X-Mailer: Mozilla 4.72 [en] (X11; I; Linux 2.2.14 i486) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> <958400279.905898@shelley.paradise.net.nz> <392009D0.8F49293E@netinsight.se> <391FD771.4AED833@trailing-edge.com> <39201069.889D5D9D@netinsight.se> <391FE2D6.6E4F77EE@trailing-edge.com> <6uzopqfbj6.fsf@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 207.153.6.57 X-Trace: 17 May 2000 11:00:35 -0700, 207.153.6.57 Organization: OA Internet Lines: 20 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!isdnet!netnews.com!howland.erols.net!newsfeed.direct.ca!west2.newsfeed.sprint-canada.net!news.oanet.com!207.153.6.57 Xref: chonsp.franklin.ch alt.folklore.computers:56462 Mel Wilson wrote: > > In article <6uzopqfbj6.fsf@chonsp.franklin.ch>, > Neil Franklin wrote: > Now why Intel did not make MOV d,s into 00dddsss and then have ADDA A > as its NOP (instead of an special instruction). Just a messy design I > suppose, but they were training for the 80x86:-). I like 8080 instruction set. The messy design flaw was with the 80x86. The 8080/80x86...80786 are all in my mind still in/out processers because 1) 64k segmented adress space 2) Character data cannot be used in aritmitic operations as word data.Rather than: add ax,(byte pointer) foobar you have go: mov bx,ax; ld al,(byte pointer) foobar;sex al;add ax,bx 3) No stack operations ie:add ax,(sp++) Ben. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Ancient Logic" http://www.jetnet.ab.ca/users/bfranchuk/al/index.html ###### From: Charles Richmond Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Date: Tue, 16 May 2000 16:30:23 -0700 Organization: Cannine Computer Center Lines: 22 Message-ID: <3921DA0F.CC4F161F@dallas.net> References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> <958400279.905898@shelley.paradise.net.nz> <392009D0.8F49293E@netinsight.se> <391FD771.4AED833@trailing-edge.com> <39201069.889D5D9D@netinsight.se> <391FE2D6.6E4F77EE@trailing-edge.com> <392072bb.2838716228@news.std.com> Reply-To: richmond@dallas.net X-Complaints-To: newsabuse@supernews.com X-Mailer: Mozilla 4.7C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; I; PPC) X-Accept-Language: en MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!newshunter!cosy.sbg.ac.at!newsfeed.Austria.EU.net!nmaster.kpnqwest.net!npeer.kpnqwest.net!news.maxwell.syr.edu!feed2.onemain.com!feed1.onemain.com!feeder.qis.net!sn-xit-01!supernews.com!sn-inject-01!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56457 Bruce Tomlin wrote: > > In article <392072bb.2838716228@news.std.com>, no-uce@world.std.com wrote: > > > Likely the most interesting PDP11 addressing mode that is missing in > > most 8bitters is indexed indirect mode. this makes most compilers > > Esp C very efficient but, C on 8080/z80 gens a lot of code to do that. > > In comparison, the 6809 is rich in indexed modes. So much so that the > Forth inner loop can be done in two instructions, where it takes like 15 > or so on an 8080/Z80. > Which coincidentally is the same number needed by the PDP-11... two instructions. The 6809 is great for Forth because of this, since the "inner loop" (i.e. docol) is executed once for each secondary word that is called. Also, since the 6809 has *two* hardware stack pointers, it is easier to manage the *two* stacks that Forth maintains. -- +-------------------------------------------------------------+ | Charles and Francis Richmond | +-------------------------------------------------------------+ ###### From: "Mike Yankus" Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Date: Wed, 17 May 2000 09:03:14 -0500 Organization: Sterling Software, Inc. Lines: 25 Message-ID: <8fu8rb$ckr$1@reuters.plano.sterling.com> References: <8fanf1$ih4@nnrp1.farm.idt.net> <3919F95F.35BBB64F@dallas.net> <958038783.53624@shelley.paradise.net.nz> <391A9257.52DCB66D@netinsight.se> <958084713.291883@shelley.paradise.net.nz> <391B9A17.932A239E@netinsight.se> <391BB60E.487F9FCF@trailing <8frp38$e3g$1@news.kersur.net> <8fs0vl$e57$1@newsg1.svr.pol.co.uk> NNTP-Posting-Host: pc-504.itd.sterling.com X-Trace: reuters.plano.sterling.com 958572203 12955 10.1.27.104 (17 May 2000 14:03:23 GMT) X-Complaints-To: usenet@reuters.plano.sterling.com NNTP-Posting-Date: 17 May 2000 14:03:23 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2615.200 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!isdnet!netnews.com!feeder.qis.net!feed2.onemain.com!feed1.onemain.com!uunet!ffx.uu.net!hype.plano.sterling.com!news.plano.sterling.com!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56520 Adrian Lumsden wrote in message news:8fs0vl$e57$1@newsg1.svr.pol.co.uk... > I only remember finding two uses for -(PC). > > One was planting 014747, MOV -(PC), -(PC), in memory with ODT and then > starting from that location. It was a useful trick for zapping memory > quickly. > > The other was something to do with the challenge to write a routine > which would completely zero all of memory. This reduces down to "How do > I get rid of the last few words?" I remember figuring it out but not how > it was done. It depended on planting an instruction at the address > formed by it's opcode and executing it. I seem to remember the address > and opcode started 015... > I remember putting a CLR (R0)+ , BR *-2 (5020, 776) at loc 0/2 and letting it go. When the cpu halted locations 0 and 2 were zeros. I don't remember what mechanism made this happen. Mike ###### Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 From: ns8rl@bath.ac.uk (R Lucas) Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Content-Type: text/plain; charset=us-ascii X-Newsreader: knews 1.0b.1 Organization: School of Natural Sciences, University of Bath, UK Message-ID: References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> <958400279.905898@shelley.paradise.net.nz> <392009D0.8F49293E@netinsight.se> <391FD771.4AED833@trailing-edge.com> <39201069.889D5D9D@netinsight.se> <391FE0A6.63E77169@trailing-edge.com> Mime-Version: 1.0 Date: Wed, 17 May 2000 16:05:44 GMT Lines: 20 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newscore.univie.ac.at!194.25.134.126.MISMATCH!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!newsfeed.wirehub.nl!skynet.be!tank.news.pipex.net!pipex!server1.netnews.ja.net!hgmp.mrc.ac.uk!pegasus.csx.cam.ac.uk!bath.ac.uk!ns8rl Xref: chonsp.franklin.ch alt.folklore.computers:56486 In article <391FE0A6.63E77169@trailing-edge.com>, Tim Shoppa writes: > The 8080/Z80 opcode 76 hex - which you might expect to be LD (HL),(HL) > or MOV M,M - is actually HALT. I don't know what happens if you > precede it with a IX+offset or IY+offset prefix on a Z80. I can't test these myself at the moment, but AFAIK: 76 HALT DD 76 HALT CB 76 BIT 6,(HL) ED 76 IM 1 (undocumented) DD CB 76 BIT 6,(IX+d) Rayner -- Home pages: http://www.bath.ac.uk/~ns8rl/ Lumber Cartel Member #2133 (TINLC) ###### Message-ID: <3922CBBF.DF117D5B@jetnet.ab.ca> Date: Wed, 17 May 2000 10:41:35 -0600 From: Ben Franchuk X-Mailer: Mozilla 4.72 [en] (X11; I; Linux 2.2.14 i486) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <8fanf1$ih4@nnrp1.farm.idt.net> <3919F95F.35BBB64F@dallas.net> <958038783.53624@shelley.paradise.net.nz> <391A9257.52DCB66D@netinsight.se> <958084713.291883@shelley.paradise.net.nz> <391B9A17.932A239E@netinsight.se> <391BB60E.487F9FCF@trailing <8frp38$e3g$1@news.kersur.net> <8fs0vl$e57$1@newsg1.svr.pol.co.uk> <8fu8rb$ckr$1@reuters.plano.sterling.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 207.153.6.57 X-Trace: 17 May 2000 10:36:40 -0700, 207.153.6.57 Organization: OA Internet Lines: 29 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!news-feeder2.wcg.net!WCG!cyclone-sf.pbi.net!207.211.168.17!pln-w!extra.newsguy.com!lotsanews.com!west2.newsfeed.sprint-canada.net!news.oanet.com!207.153.6.57 Xref: chonsp.franklin.ch alt.folklore.computers:56464 Mike Yankus wrote: > > Adrian Lumsden wrote in message > news:8fs0vl$e57$1@newsg1.svr.pol.co.uk... > > The other was something to do with the challenge to write a routine > > which would completely zero all of memory. This reduces down to "How do > > I get rid of the last few words?" I remember figuring it out but not how > > it was done. It depended on planting an instruction at the address > > formed by it's opcode and executing it. I seem to remember the address > > and opcode started 015... > > > > I remember putting a CLR (R0)+ , BR *-2 (5020, 776) at loc 0/2 and > letting it go. When the cpu halted locations 0 and 2 were zeros. > I don't remember what mechanism made this happen. > > Mike If I remember in the back issues of BYTE (The real early ones ) had that way of doing that for the 8080. I think it was a multi pass process - fill memory up instructions to clear memory and then clear it several passes. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Ancient Logic" http://www.jetnet.ab.ca/users/bfranchuk/al/index.html ###### From: Andrew Paul Cadley Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Date: Wed, 17 May 2000 18:15:10 +0100 Organization: University of East Anglia, Norwich, Norfolk, NR47TJ, UK Lines: 15 Message-ID: References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> <958400279.905898@shelley.paradise.net.nz> <392009D0.8F49293E@netinsight.se> <391FD771.4AED833@trailing-edge.com> <39201069.889D5D9D@netinsight.se> <391FE2D6.6E4F77EE@trailing-edge.com> NNTP-Posting-Host: cpca7.uea.ac.uk Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Trace: cpca14.uea.ac.uk 958583711 26745 139.222.130.7 (17 May 2000 17:15:11 GMT) X-Complaints-To: news@uea.ac.uk NNTP-Posting-Date: 17 May 2000 17:15:11 GMT In-Reply-To: <391FE2D6.6E4F77EE@trailing-edge.com> Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!newspeer.clara.net!news.clara.net!nntp.news.xara.net!xara.net!gxn.net!server6.netnews.ja.net!server1.netnews.ja.net!news.uea.ac.uk!cpca7.uea.ac.uk!a962115 Xref: chonsp.franklin.ch alt.folklore.computers:56521 On Mon, 15 May 2000, Tim Shoppa wrote: > If you were hurting for new opcodes on an 8080 successor > you might think about using other apparent NOP's like MOV A,A (aka LD > A,A), but Zilog didn't do this, they resorted to prefix bytes in many > cases. This was, I believe, done for compatability reasons. Zilog didn't want to risk code not working by redefining opcodes (even ones unlikely to be used) so the plumped for the prefix option instead. AndyC ###### Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FE2D6.6E4F77EE@trailing-edge.com> Organization: D Bit, Troy, NY From: wilson@dbit.com (John Wilson) NNTP-Posting-Host: dbit.dbit.com X-Original-NNTP-Posting-Host: dbit.dbit.com Message-ID: <3922d5aa_1@news.wizvax.net> Date: 17 May 2000 13:23:54 -0400 X-Trace: 17 May 2000 13:23:54 -0400, dbit.dbit.com Lines: 11 XPident: wilson X-Original-NNTP-Posting-Host: 199.181.141.3 XPident: news Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!colt.net!diablo.netcom.net.uk!netcom.net.uk!newsfeed.wizvax.net!news.wizvax.net!dbit.com!wilson Xref: chonsp.franklin.ch alt.folklore.computers:56474 In article , Andrew Paul Cadley wrote: >This was, I believe, done for compatability reasons. Zilog didn't want to >risk code not working by redefining opcodes (even ones unlikely to be >used) so the plumped for the prefix option instead. Didn't they already get burned by the RIM and SIM instructions that Intel added to the 8085A? My notes say they conflict with JR NZ and JR NC, could be wrong. John Wilson D Bit ###### From: jmaynard@thebrain.conmicro.cx (Jay Maynard) Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FE2D6.6E4F77EE@trailing-edge.com> <3922d5aa_1@news.wizvax.net> Reply-To: jmaynard@texas.net Message-ID: User-Agent: slrn/0.9.5.4 (UNIX) Lines: 6 NNTP-Posting-Date: Wed, 17 May 2000 12:51:57 CDT Organization: Giganews.Com - Premium News Outsourcing X-Trace: sv2-255uuto4REib3peqUj9RQhq9FqWeP0lNKMdG80VimHDm+cMrwb+dvagEbFmFaM51IZn5X+Q+8cdTCa8!3iIYwqo8bInHROnESRQa X-Complaints-To: abuse@GigaNews.Com X-Abuse-Info: Please be sure to forward a copy of ALL headers X-Abuse-Info: Otherwise we will be unable to process your complaint properly Date: Wed, 17 May 2000 17:51:57 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newscore.univie.ac.at!fu-berlin.de!nf1.mgmt.sympatico.ca!news1.bellglobal.com!nntp.giganews.com!nntp3.giganews.com!news5.giganews.com.POSTED!jmaynard Xref: chonsp.franklin.ch alt.folklore.computers:56458 On 17 May 2000 13:23:54 -0400, John Wilson wrote: >Didn't they already get burned by the RIM and SIM instructions that Intel >added to the 8085A? My notes say they conflict with JR NZ and JR NC, could >be wrong. Yes, except that Intel did this after the Z-80 was on the market. ###### From: rde@tavi.co.uk (Bob Eager) Organization: Tavi Systems Message-ID: <176uZD2KcidF-pn2-i2P9gr7Uisws@rikki.tavi.co.uk> Newsgroups: vmsnet.pdp-11,alt.sys.pdp11,alt.folklore.computers Subject: Re: Orthogonality References: <8fanf1$ih4@nnrp1.farm.idt.net> <3922D15B.78F3F0F2@jetnet.ab.ca> X-Newsreader: ProNews/2 Version 1.50á1/02 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8bit X-Punge: Micro$oft Date: 17 May 2000 23:47:33 GMT Lines: 14 NNTP-Posting-Host: man-a059.dialup.zetnet.co.uk X-Trace: news.zetnet.co.uk 958607253 31674 194.247.44.59 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!isdnet!diablo.theplanet.net!news-hub.cableinet.net!peernews.manap.net!peer.news.zetnet.net!master.news.zetnet.net!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56529 On Wed, 17 May 2000 17:05:31, Ben Franchuk wrote: > processers because 1) 64k segmented adress space Not on a 386 and above in protected mode. Multiple 4GB address spaces with either 4KB or 4MB pages. -- Bob Eager rde at tavi.co.uk PC Server 325; PS/2s 8595*3, 9595*3 (2*P60 + P90), 8535, 8570, 9556*2, 8580*6, 8557*2, 8550, 9577, 8530, P70, PC/AT.. ###### Message-ID: <39235443.739920F5@jetnet.ab.ca> Date: Wed, 17 May 2000 20:24:03 -0600 From: Ben Franchuk X-Mailer: Mozilla 4.72 [en] (X11; I; Linux 2.2.14 i486) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: vmsnet.pdp-11,alt.sys.pdp11,alt.folklore.computers To: Bob Eager Subject: Re: Orthogonality References: <8fanf1$ih4@nnrp1.farm.idt.net> <3922D15B.78F3F0F2@jetnet.ab.ca> <176uZD2KcidF-pn2-i2P9gr7Uisws@rikki.tavi.co.uk> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 207.153.6.40 X-Trace: 17 May 2000 20:19:03 -0700, 207.153.6.40 Organization: OA Internet Lines: 25 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newscore.univie.ac.at!194.25.134.126.MISMATCH!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!newscore.gigabell.net!newsfeed.icl.net!triton.skycache.com!128.230.129.106!news.maxwell.syr.edu!east1.newsfeed.sprint-canada.net!west2.newsfeed.sprint-canada.net!news.oanet.com!207.153.6.40 Xref: chonsp.franklin.ch alt.folklore.computers:56532 Bob Eager wrote: > > On Wed, 17 May 2000 17:05:31, Ben Franchuk > wrote: > > > processers because 1) 64k segmented adress space > > Not on a 386 and above in protected mode. Multiple 4GB address spaces > with either 4KB or 4MB pages. Yes But only after you BOOT the system from the brain dead REAL mode.Some software is still limited to 80x86 modes. DOS for example does not support 32 mode addressing as we all know. Ben. > Bob Eager > rde at tavi.co.uk > PC Server 325; PS/2s 8595*3, 9595*3 (2*P60 + P90), 8535, 8570, 9556*2, > 8580*6, > 8557*2, 8550, 9577, 8530, P70, PC/AT.. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Ancient Logic" http://www.jetnet.ab.ca/users/bfranchuk/al/index.html ###### From: j1234@sfsu.savemydomain.edu Newsgroups: alt.folklore.computers Subject: Re: Orthogonality Followup-To: vmsnet.pdp-11,alt.sys.pdp11,alt.folklore.computers Date: 18 May 2000 04:08:38 GMT Organization: CSUnet Lines: 16 Message-ID: <8fvqc6$ev1o$1@hades.csu.net> References: <8fanf1$ih4@nnrp1.farm.idt.net> <3922D15B.78F3F0F2@jetnet.ab.ca> <176uZD2KcidF-pn2-i2P9gr7Uisws@rikki.tavi.co.uk> <39235443.739920F5@jetnet.ab.ca> NNTP-Posting-Host: hou157-229.sfsu.edu User-Agent: tin/1.4.2-20000205 ("Possession") (UNIX) (SunOS/5.7 (sun4m)) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!isdnet!howland.erols.net!usc.edu!newshub.csu.net!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56562 In alt.folklore.computers Ben Franchuk wrote: > Bob Eager wrote: > Yes But only after you BOOT the system from the brain dead > REAL mode.Some software is still limited to 80x86 modes. > DOS for example does not support 32 mode addressing as we all know. > Ben. But there is nothing to stop a program from switching to another mode. The port of gcc to DOS by D.J. Delorie uses a program to do this prior to executing the compiled code. If this is too much of a kludge, I believe that intel makes IA32 processors that boot into 32bit protected mode. IIRC they are targeted at imbedded applications. jeremy ###### From: rde@tavi.co.uk (Bob Eager) Organization: Tavi Systems Message-ID: <176uZD2KcidF-pn2-q2WVdu0RuMch@rikki.tavi.co.uk> Newsgroups: alt.sys.pdp11,alt.folklore.computers,vmsnet.pdp-11 Subject: Re: Orthogonality References: <8fanf1$ih4@nnrp1.farm.idt.net> <3922D15B.78F3F0F2@jetnet.ab.ca> <176uZD2KcidF-pn2-i2P9gr7Uisws@rikki.tavi.co.uk> <39235443.739920F5@jetnet.ab.ca> X-Newsreader: ProNews/2 Version 1.50á1/02 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8bit X-Punge: Micro$oft Date: 18 May 2000 08:14:43 GMT Lines: 22 NNTP-Posting-Host: man-a118.dialup.zetnet.co.uk X-Trace: news.zetnet.co.uk 958637683 31675 194.247.44.118 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.datacomm.ch!newscore.gigabell.net!newsfeed00.sul.t-online.de!t-online.de!diablo.theplanet.net!newspeer.clara.net!news.clara.net!peer.news.zetnet.net!master.news.zetnet.net!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56528 On Thu, 18 May 2000 02:24:03, Ben Franchuk wrote: > Yes But only after you BOOT the system from the brain dead > REAL mode.Some software is still limited to 80x86 modes. > DOS for example does not support 32 mode addressing as we all know. > Ben. Oh, I realise that. I was just pointing out that it wasn't, as implied, a real limitation. The real mode boot is just for backwards compatibility. In practice, no-one uses DOS except for that backwards compatibility. One might as well argue that some VAXes were brain dead because they supported PDP-11 compatibility mode! -- Bob Eager rde at tavi.co.uk PC Server 325; PS/2s 8595*3, 9595*3 (2*P60 + P90), 8535, 8570, 9556*2, 8580*6, 8557*2, 8550, 9577, 8530, P70, PC/AT.. ###### From: David Wragg Newsgroups: alt.folklore.computers Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Lines: 18 Message-ID: References: <8fanf1$ih4@nnrp1.farm.idt.net> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> <958400279.905898@shelley.paradise.net.nz> <392009D0.8F49293E@netinsight.se> <391FD771.4AED833@trailing-edge.com> <39201069.889D5D9D@netinsight.se> <391FE2D6.6E4F77EE@trailing-edge.com> <392072bb.2838716228@news.std.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii User-Agent: Gnus/5.0806 (Gnus v5.8.6) XEmacs/20.4 (Emerald) Date: 17 May 2000 16:15:56 +0000 NNTP-Posting-Host: 194.119.176.228 X-Complaints-To: news@u-net.net X-Trace: newsr2.u-net.net 958603274 194.119.176.228 (Wed, 17 May 2000 23:41:14 BST) NNTP-Posting-Date: Wed, 17 May 2000 23:41:14 BST Organization: (Posted via) U-NET Internet Ltd. Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!feed2.news.luth.se!luth.se!news-peer-europe.sprintlink.net!news.sprintlink.net!howland.erols.net!europa.netcrusader.net!194.176.220.129!newsfeed.icl.net!newsfeed.icl.net!diablo.theplanet.net!peer.news.th.u-net.net!u-net!newsr2.u-net.net!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56590 no-uce@world.std.com writes: > >OK, it's even more complicated than just a data path, you'd need to > >special-case this kind of move from all the others into a new > >sequence with a temporary register that isn't otherwise used. > > Likely the most interesting PDP11 addressing mode that is missing in > most 8bitters is indexed indirect mode. this makes most compilers > Esp C very efficient but, C on 8080/z80 gens a lot of code to do that. On the Z80, this is the point of IX and IY, isn't it? I never used any Z80 C compilers, so I don't know whether any of them made reasonable use of IX and IY. (I later wondered what the calling convention might have been, and decided that they probably used IX or IY as a frame pointer with "PUSH SP ; EX (SP), IX" to set it up.) David Wragg ###### From: ian@hammo.com (paramucho) Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Date: Thu, 18 May 2000 19:59:04 GMT Organization: www.hammo.com Lines: 18 Message-ID: <39254a92.946886@news.supernews.com> References: <958038783.53624@shelley.paradise.net.nz> <391A9257.52DCB66D@netinsight.se> <958084713.291883@shelley.paradise.net.nz> <391B9A17.932A239E@netinsight.se> <391BB60E.487F9FCF@trailing-edge.com> <391BFBE6.BC4122CD@netinsight.se> <391BD096.6A224D5C@trailing-edge.com> <391C1A43.C4582FB5@netinsight.se> <391BF5EC.4642D331@trailing-edge.com> <391F9BD9.4178CEE5@netinsight.se> <391FA4B6.53954D31@trailing-edge.com> <391FEE45.CED408A2@netinsight.se> <391FBFAA.1530B784@trailing-edge.com> Reply-To: ian@hammo.com X-Complaints-To: newsabuse@supernews.com X-Newsreader: Forte Agent 1.5/32.451 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news-fra1.dfn.de!news0.de.colt.net!colt.net!diablo.theplanet.net!newsfeed.direct.ca!sn-xit-03!sn-xit-01!supernews.com!sn-inject-01!news.supernews.com!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56627 On Mon, 15 May 2000 09:13:14 -0400, Tim Shoppa wrote: >Along those lines: > >I've never even tried a MUL x,R6 on an EIS PDP-11. Nothing >in my books tells me it's prohibited, but it's probably the >stupidest thing a programmer could ever try to do :-). I seem to recall that the microcode of one of the early chip versions of the PDP-11s used the RAM stack for an intermediate result. That might just complicate this marginal operation just enough to make it interesting :-) Ian ###### Newsgroups: alt.folklore.computers,vmsnet.pdp-11,alt.sys.pdp11 Subject: Re: Orthogonality References: <8fanf1$ih4@nnrp1.farm.idt.net> <6uzopqfbj6.fsf@chonsp.franklin.ch> <3922D15B.78F3F0F2@jetnet.ab.ca> Organization: None X-Newsreader: trn 4.0-test72 (19 April 1999) From: kragen@dnaco.net (Kragen Sitaker) Lines: 20 Message-ID: X-Abuse-Info: Please be sure to forward a copy of ALL headers X-Abuse-Info: Otherwise we will be unable to process your complaint properly X-Complaints-To: support@usenetserver.com NNTP-Posting-Date: Fri, 19 May 2000 17:28:07 EDT Date: Fri, 19 May 2000 21:28:07 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!cyclone2.usenetserver.com!news-out.usenetserver.com!cyclone1.usenetserver.com!cyclone1.usenetserver.com!news-east.usenetserver.com.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56724 In article <3922D15B.78F3F0F2@jetnet.ab.ca>, Ben Franchuk wrote: > I like 8080 instruction set. The messy design flaw was with the >80x86. The 8080/80x86...80786 are all in my mind still in/out >processers because 1) 64k segmented adress space Not past the 386. You might as well complain that they aren't 32-bit processors because their registers are 16-bit. >2) Character data cannot be used in aritmitic operations as >word data.Rather than: add ax,(byte pointer) foobar >you have go: mov bx,ax; ld al,(byte pointer) foobar;sex al;add ax,bx >3) No stack operations ie:add ax,(sp++) True enough, even if expressed in idiosyncratic opcodes. :) -- Kragen Sitaker The Internet stock bubble didn't burst on 1999-11-08. Hurrah! The power didn't go out on 2000-01-01 either. :) ###### Message-ID: <3928EEEF.45FC8165@trailing-edge.com> Date: Mon, 22 May 2000 08:25:20 -0400 From: Tim Shoppa Organization: Trailing Edge Technology X-Mailer: Mozilla 3.03Gold (X11; I; OpenVMS V7.0 DEC 3000 Model 300L) MIME-Version: 1.0 Newsgroups: vmsnet.pdp-11,alt.sys.pdp11,alt.folklore.computers Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 52 NNTP-Posting-Host: 63.73.218.130 X-Trace: reader2.news.uu.net 958998321 12446 63.73.218.130 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!isdnet!howland.erols.net!npeer.kpnqwest.net!newsfeed2.news.nl.uu.net!sun4nl!ams.uu.net!ffx.uu.net!spool0.news.uu.net!reader2.news.uu.net!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56851 Johnny Billquist wrote: > > On Fri, 19 May 2000, Adrian Lumsden wrote: > > > I did the same sort of thing. I defined them as Jxx though to achieve > > the > > same result. I felt that this made it clear to me that I was using a > > jump. > > In the unlikely event that the code was changed to bring a BR back > > in range I could review the Jxx and convert them back to branches. > > > > .MACRO JNE ADR > > BEQ .+6 > > JMP ADR > > .ENDM > > > > .MACRO JEQ ADR > > BNE .+6 > > JMP ADR > > .ENDM > > Whoa! Those are dangerous macros... Works fine if the destination is an > address, but what if someone figure to do a JNE (R0)... NOBODY expects the MACRO ARGUMENT INQUISITION! Our chief weapon is unexpected addressing modes... unexpected addressing modes and local branches out of range. Our two weapons are unexpected addressing modes and local branches out of range and quoted argument lists. Our *three* weapons are unexpected addressing modes, local branches out of range, quoted argument lists, and an almost fanatical devotion to the pope. *Amongst* our weapons are such elements as unexpected addressing modes, local branches out of range... I'll come in again. I agree, you gotta be careful with Macros, as often the Macro will take addressing modes or arguments that you'd never considered and do "interesting" things with them. For example, I often use Macros to build static null-terminated data structures, and allowing a zero in the data itself of course screws up the data structure. This is more of a fundamental design error than an implementation error, though. (In the same way that null terminated strings are an implementation error of C, too...) Adrian seems to use JNE as nothing more than a long-range version of BNE, so it's probably never seen anything other than the single address mode that is legal with BNE. That said, the simple solution if you want to do JNE (R0) is to replace the target of the BNE .+6 with a local label in the macro. Or put some .ASSUME's on relative PC position before and after. Tim. ###### From: ab528@FreeNet.Carleton.CA (Heinz W. Wiggeshoff) Newsgroups: alt.folklore.computers Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Date: 22 May 2000 14:26:12 GMT Organization: The National Capital FreeNet Lines: 10 Message-ID: <8gbg24$4ql$1@freenet9.carleton.ca> References: <3928EEEF.45FC8165@trailing-edge.com> Reply-To: ab528@FreeNet.Carleton.CA (Heinz W. Wiggeshoff) NNTP-Posting-Host: freenet10 X-Trace: freenet9.carleton.ca 959005572 4949 134.117.136.30 (22 May 2000 14:26:12 GMT) X-Complaints-To: complaints@ncf.ca NNTP-Posting-Date: 22 May 2000 14:26:12 GMT X-Given-Sender: ab528@freenet10.carleton.ca (Heinz W. Wiggeshoff) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!isdnet!howland.erols.net!cpk-news-hub1.bbnplanet.com!news.gtei.net!news.new-york.net!news.kjsl.com!xcski.com!freenet-news!FreeNet.Carleton.CA!ab528 Xref: chonsp.franklin.ch alt.folklore.computers:56858 Tim Shoppa (shoppa@trailing-edge.com) writes: > > NOBODY expects the MACRO ARGUMENT INQUISITION! Our chief > weapon is unexpected addressing modes... unexpected addressing > modes and local branches out of range. Our two weapons are > unexpected addressing modes and local branches out of range > and quoted argument lists. Our *three* weapons are unexpected ... etc. Would this be considered a Palindrome? ###### Message-ID: <39295062.45187E25@netinsight.se> From: Johnny Billquist Organization: Netinsight AB X-Mailer: Mozilla 4.5 [en] (X11; I; Linux 2.2.14 i686) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.folklore.computers Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <3928EEEF.45FC8165@trailing-edge.com> <8gbg24$4ql$1@freenet9.carleton.ca> Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Lines: 26 Date: Mon, 22 May 2000 15:21:15 GMT NNTP-Posting-Host: 194.16.221.33 X-Complaints-To: abuse@telia.com X-Trace: newsc.telia.net 959008875 194.16.221.33 (Mon, 22 May 2000 17:21:15 MET DST) NNTP-Posting-Date: Mon, 22 May 2000 17:21:15 MET DST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newscore.univie.ac.at!uninett.no!news.ost.eltele.no!newsfeed1.telia.no!masternews.telia.net!newsc.telia.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56829 "Heinz W. Wiggeshoff" wrote: > > Tim Shoppa (shoppa@trailing-edge.com) writes: > > > > NOBODY expects the MACRO ARGUMENT INQUISITION! Our chief > > weapon is unexpected addressing modes... unexpected addressing > > modes and local branches out of range. Our two weapons are > > unexpected addressing modes and local branches out of range > > and quoted argument lists. Our *three* weapons are unexpected > ... etc. > > Would this be considered a Palindrome? No. But it was a very good spin on an old MP skit. Made my face twist and turn. Now! Cardinal Fang. Bring.... the comfy chair! Johnny -- Johnny Billquist | johnny.billquist@netinsight.net Net Insight AB | phone: +46 8 685 04 88 Västberga Allé 9 | fax: +46 8 685 04 20 Box 42093 | SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.net ###### Message-ID: <39291A3B.56BED406@trailing-edge.com> Date: Mon, 22 May 2000 11:30:04 -0400 From: Tim Shoppa Organization: Trailing Edge Technology X-Mailer: Mozilla 3.03Gold (X11; I; OpenVMS V7.0 DEC 3000 Model 300L) MIME-Version: 1.0 Newsgroups: alt.folklore.computers Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <3928EEEF.45FC8165@trailing-edge.com> <8gbg24$4ql$1@freenet9.carleton.ca> <39295062.45187E25@netinsight.se> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 29 NNTP-Posting-Host: 63.73.218.130 X-Trace: reader2.news.uu.net 959009405 12451 63.73.218.130 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!colt.net!diablo.netcom.net.uk!netcom.net.uk!tank.news.pipex.net!pipex!zur.uu.net!ffx.uu.net!spool0.news.uu.net!reader2.news.uu.net!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56847 Johnny Billquist wrote: > > "Heinz W. Wiggeshoff" wrote: > > > > Tim Shoppa (shoppa@trailing-edge.com) writes: > > > > > > NOBODY expects the MACRO ARGUMENT INQUISITION! Our chief > > > weapon is unexpected addressing modes... unexpected addressing > > > modes and local branches out of range. Our two weapons are > > > unexpected addressing modes and local branches out of range > > > and quoted argument lists. Our *three* weapons are unexpected > > ... etc. > > > > Would this be considered a Palindrome? > > No. But it was a very good spin on an old MP skit. To quote a different skit, "it's a pun" :-) Cardinal Ximinez was played by Michael Palin ... Palindrome! > Made my face twist and turn. > > Now! Cardinal Fang. Bring.... the comfy chair! Okay, stop. Stop. Stop there - stop there. Stop. Phew! Ah! ...our chief weapons are surprise...blah blah blah. Cardinal, read the charges. Tim. ###### Newsgroups: vmsnet.pdp-11,alt.sys.pdp11,alt.folklore.computers Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <3928EEEF.45FC8165@trailing-edge.com> Organization: D Bit, Troy, NY From: wilson@dbit.com (John Wilson) NNTP-Posting-Host: dbit.dbit.com X-Original-NNTP-Posting-Host: dbit.dbit.com Message-ID: <39295802_1@news.wizvax.net> Date: 22 May 2000 11:53:38 -0400 X-Trace: 22 May 2000 11:53:38 -0400, dbit.dbit.com Lines: 11 XPident: wilson X-Original-NNTP-Posting-Host: 199.181.141.3 XPident: news Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newscore.univie.ac.at!uninett.no!news.netscum.dk.MISMATCH!CensurBot!news.tele.dk!CensurBot.NetScum.Dk!newsfeedZ.netscum.dQ!netscum.int!news.he.net!newspeer1.nac.net!news.mv.net!newspeer.phoen-x.net!news.wizvax.net!dbit.com!wilson Xref: chonsp.franklin.ch alt.folklore.computers:56824 In article <3928EEEF.45FC8165@trailing-edge.com>, Tim Shoppa wrote: >That said, the simple solution if you want to do JNE (R0) is to >replace the target of the BNE .+6 with a local label in the macro. >Or put some .ASSUME's on relative PC position before and after. If you hated yourself enough, you could probably do it with .NTYPE and a bunch of conditionals too... John Wilson D Bit ###### From: "Adrian Lumsden" Newsgroups: vmsnet.pdp-11,alt.sys.pdp11,alt.folklore.computers Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Date: Mon, 22 May 2000 17:14:21 +0100 Organization: XDT Computer Systems Ltd. Lines: 31 Message-ID: <8gbofe$5ii$2@newsg3.svr.pol.co.uk> References: <3928EEEF.45FC8165@trailing-edge.com> Reply-To: "Adrian Lumsden" NNTP-Posting-Host: modem-59.amitriptyline.dialup.pol.co.uk X-Trace: newsg3.svr.pol.co.uk 959014190 5714 62.136.77.187 (22 May 2000 16:49:50 GMT) NNTP-Posting-Date: 22 May 2000 16:49:50 GMT X-Complaints-To: abuse@theplanet.net X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2615.200 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!isdnet!diablo.theplanet.net!news.theplanet.net!newspost.theplanet.net!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56860 Tim Shoppa wrote in message news:3928EEEF.45FC8165@trailing-edge.com... > Adrian seems to use JNE as nothing more than a long-range version > of BNE, so it's probably never seen anything other than the single > address mode that is legal with BNE. > > That said, the simple solution if you want to do JNE (R0) is to > replace the target of the BNE .+6 with a local label in the macro. > Or put some .ASSUME's on relative PC position before and after. > > Tim. Yes. That's exactly what I was doing. When I went back to the source code to fix it today, there's even a comment that says "This is for addressing mode 2 only". However I should have made _sure_ that it was for addressing mode 2 only. It now does the local label thing. I might even start to use Jxx (R0). That way I get more code per line of code! I have a local standard that if the lines of code in a routine don't fit onto the screen then it needs splitting into smaller peices. Mind you I do cheat a little and use an editing window that's 48 lines long :-) Adrian ###### From: ab528@FreeNet.Carleton.CA (Heinz W. Wiggeshoff) Newsgroups: alt.folklore.computers Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Date: 22 May 2000 16:21:23 GMT Organization: The National Capital FreeNet Lines: 7 Message-ID: <8gbmq3$eed$1@freenet9.carleton.ca> References: <3928EEEF.45FC8165@trailing-edge.com> <8gbg24$4ql$1@freenet9.carleton.ca> <39295062.45187E25@netinsight.se> <39291A3B.56BED406@trailing-edge.com> Reply-To: ab528@FreeNet.Carleton.CA (Heinz W. Wiggeshoff) NNTP-Posting-Host: freenet10 X-Trace: freenet9.carleton.ca 959012483 14797 134.117.136.30 (22 May 2000 16:21:23 GMT) X-Complaints-To: complaints@ncf.ca NNTP-Posting-Date: 22 May 2000 16:21:23 GMT X-Given-Sender: ab528@freenet10.carleton.ca (Heinz W. Wiggeshoff) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!newspeer.te.net!news.indigo.ie!diablo.theplanet.net!news.maxwell.syr.edu!nntp.frontiernet.net!nntp.gctr.net!xcski.com!freenet-news!FreeNet.Carleton.CA!ab528 Xref: chonsp.franklin.ch alt.folklore.computers:56862 Tim Shoppa (shoppa@trailing-edge.com) writes: > > To quote a different skit, "it's a pun" :-) Cardinal Ximinez was > played by Michael Palin ... Palindrome! It gets worse: I meant to type 'Palindrone'. I guess I have a 286 brain in a 486 world. (Ob a.f.c. tie-in) ###### From: nailed_barnacleSPAMFREE@hotmail.com (barnacle) Newsgroups: alt.folklore.computers Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Date: Mon, 22 May 2000 19:13:23 GMT Organization: [posted via Easynet Ltd] Lines: 18 Message-ID: <8gc0u8$185j$1@quince.news.easynet.net> References: <3928EEEF.45FC8165@trailing-edge.com> <8gbg24$4ql$1@freenet9.carleton.ca> NNTP-Posting-Host: nbarnes.easynet.co.uk X-Trace: quince.news.easynet.net 959022856 41139 194.154.98.206 (22 May 2000 19:14:16 GMT) X-Complaints-To: abuse@easynet.net NNTP-Posting-Date: 22 May 2000 19:14:16 GMT X-Newsreader: News Xpress 2.01 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.datacomm.ch!newscore.gigabell.net!news-x.support.nl!psinet-eu-nl!newspeer.ebone.net!easynet-tele!easynet.net!quince.news.easynet.net!egbert Xref: chonsp.franklin.ch alt.folklore.computers:56923 In article <8gbg24$4ql$1@freenet9.carleton.ca>, ab528@FreeNet.Carleton.CA (Heinz W. Wiggeshoff) wrote: >Tim Shoppa (shoppa@trailing-edge.com) writes: >> >> NOBODY expects the MACRO ARGUMENT INQUISITION! Our chief >> weapon is unexpected addressing modes... unexpected addressing >> modes and local branches out of range. Our two weapons are >> unexpected addressing modes and local branches out of range >> and quoted argument lists. Our *three* weapons are unexpected >.... etc. > > Would this be considered a Palindrome? I don't wish to know that. Kindly leave the stage! -- barnacle http://www.nailed-barnacle.co.uk ###### Message-ID: <392A2068.B05FA212@netinsight.se> From: Johnny Billquist Organization: Netinsight AB X-Mailer: Mozilla 4.5 [en] (X11; I; Linux 2.2.14 i686) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: alt.folklore.computers Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) References: <3928EEEF.45FC8165@trailing-edge.com> <8gbg24$4ql$1@freenet9.carleton.ca> <39295062.45187E25@netinsight.se> <39291A3B.56BED406@trailing-edge.com> Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Lines: 32 Date: Tue, 23 May 2000 06:08:40 GMT NNTP-Posting-Host: 194.16.221.33 X-Complaints-To: abuse@telia.com X-Trace: newsc.telia.net 959062120 194.16.221.33 (Tue, 23 May 2000 08:08:40 MET DST) NNTP-Posting-Date: Tue, 23 May 2000 08:08:40 MET DST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news-fra1.dfn.de!news0.de.colt.net!blackbush.xlink.net!uni-erlangen.de!newsfeed1.telenordia.se!news.algonet.se!algonet!uninett.no!newsfeed1.telia.no!masternews.telia.net!newsc.telia.net.POSTED!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56899 Tim Shoppa wrote: > > Johnny Billquist wrote: > > > > "Heinz W. Wiggeshoff" wrote: > > > > > > Tim Shoppa (shoppa@trailing-edge.com) writes: > > > > > > > > NOBODY expects the MACRO ARGUMENT INQUISITION! Our chief > > > > weapon is unexpected addressing modes... unexpected addressing > > > > modes and local branches out of range. Our two weapons are > > > > unexpected addressing modes and local branches out of range > > > > and quoted argument lists. Our *three* weapons are unexpected > > > ... etc. > > > > > > Would this be considered a Palindrome? > > > > No. But it was a very good spin on an old MP skit. > > To quote a different skit, "it's a pun" :-) Cardinal Ximinez was > played by Michael Palin ... Palindrome! Argh! Missed that one. Ouch! :-) Johnny -- Johnny Billquist | johnny.billquist@netinsight.net Net Insight AB | phone: +46 8 685 04 88 Västberga Allé 9 | fax: +46 8 685 04 20 Box 42093 | SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.net ###### From: Eric Chomko Newsgroups: alt.folklore.computers Subject: Re: Orthogonality (was Re: Motorola/Intel Wars) Date: 23 May 2000 16:03:19 GMT Organization: IDT Internet Services Lines: 21 Message-ID: <8gea47$sfn@nnrp4.farm.idt.net> References: <3928EEEF.45FC8165@trailing-edge.com> <8gbg24$4ql$1@freenet9.carleton.ca> NNTP-Posting-Host: u3.farm.idt.net X-Newsreader: TIN [UNIX 1.3 unoff BETA release 961025] Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-feed.fnsi.net!news.idt.net!nntp.farm.idt.net!u3.farm.idt.net!not-for-mail Xref: chonsp.franklin.ch alt.folklore.computers:56906 Heinz W. Wiggeshoff wrote: : Tim Shoppa (shoppa@trailing-edge.com) writes: : > : > NOBODY expects the MACRO ARGUMENT INQUISITION! Our chief : > weapon is unexpected addressing modes... unexpected addressing : > modes and local branches out of range. Our two weapons are : > unexpected addressing modes and local branches out of range : > and quoted argument lists. Our *three* weapons are unexpected : ... etc. : Would this be considered a Palindrome? What? No, a palindrome is a word of phrase that spells the same way forward and backward. Take your name and change a few things: Shoppa => Shoppohs Now THAT is a palindrome. The above is a form of verbal recursion. Eric