From: Jim Stewart <jstewart@jkmicro.com>
Newsgroups: alt.folklore.computers
Subject: PDP 8 gate count
Date: Wed, 29 Sep 1999 11:18:08 -0700
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I was told by a group of engineers that if you could come up with a
Verilog discription of a usable microprocessor with less than 3K gates,
you'd have a very useful design.  In my youth, I spent many hours
chasing gates in PDP 8/i's and 8/L's and I'm convinced their gate count
couldn't exceed 1K.  Anyone have an opinion on this?  Admittedly, the
async design of the 8/i and 8/L probably couldn't be directly
implemented in the decidedly synchronous environment of HDL, but a
minimal design should still be possible.

Jim

######

From: David M. Razler <david.razler@worldnet.att.net>
Newsgroups: alt.folklore.computers
Subject: Re: PDP 8 gate count
Date: Wed, 29 Sep 1999 18:24:21 -0400
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Jim Stewart <jstewart@jkmicro.com> wrote:

| I was told by a group of engineers that if you could come up with a
| Verilog discription of a usable microprocessor with less than 3K gates,
| you'd have a very useful design.  In my youth, I spent many hours
| chasing gates in PDP 8/i's and 8/L's and I'm convinced their gate count
| couldn't exceed 1K.  Anyone have an opinion on this?  Admittedly, the
| async design of the 8/i and 8/L probably couldn't be directly
| implemented in the decidedly synchronous environment of HDL, but a
| minimal design should still be possible.
| 
| Jim

I know it's buried in Bell et. al.'s book, but am damned if I can find it
right now - my guess is, outside of memory circuits and other places where
they are used simply to amplify but not modify a signal, I doubt my Straight-8
has 1,000 transistors! (base CPU).

I'm almost positive the PDP-8/s has well under 1,000 transistors total (try
about 250-500 as it was a serial machine pricessing 1 bit of a 12-bit word at
a time.

In early computer design, it was hardware that cost money and software that
was almost free (we're talking the $1 to $5 transistor here, remember? <plus
board real estate, power and cooling>)

So a trip back in history may turn up dozens of what are now called "RISC"
designs with fewer than 1K gates.

Then again, with individual transistors costing next to nothing, why *not* use
more of them?

					dmr
 
David M. Razler
david.razler@worldnet.att.net

######

From: jones@cs.uiowa.edu (Douglas W. Jones,201H MLH,3193350740,3193382879)
Newsgroups: alt.folklore.computers
Subject: Re: PDP 8 gate count
Date: 1 Oct 1999 14:22:40 GMT
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From article <4165BF93280A3D6A.F943026BB2DD9497.B7F6D6B9B1DD1139@lp.airnews.net>, by Jim Stewart <jstewart@jkmicro.com>:
> I was told by a group of engineers that if you could come up with a
> Verilog discription of a usable microprocessor with less than 3K gates,
> you'd have a very useful design.

See http://www.cs.uiowa.edu/~jones/arch/risc for an appallingly simple
general purpose computer architecture.  Several have been built, both
by students here or there, and I believe possibly by someone at SGI
(I got an inquiry from SGI several years ago about support software for
this little monster).

I don't recommend making the absolute minimal version given in the paper.
Make it with a few more registers attached to the ALU (for example, decode
a few bits of the address path for register select), and most importantly,
make sure at least one of the registers are available for use as an index
register (for example, decode the top bits of the address to select the
index register, where addresses starting with 1111 are un-indexed).

				Doug Jones
				jones@cs.uiowa.edu