From: mww@microfocus.com (Michael Wojcik) Newsgroups: alt.folklore.computers Subject: RISC philosophy (was Re: Transmeta's Little Secret) Date: 8 Oct 1998 20:55:10 GMT Organization: Micro Focus Inc. Lines: 89 Message-ID: <6vj8re$6s7@news3.newsguy.com> References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> <6vdtpa$3qf@news3.newsguy.com> NNTP-Posting-Host: p-329.newsdawg.com X-Newsreader: xrn 9.00 Originator: mww@raederle.microfocus.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.berkeley.edu!pln-w!spln!extra.newsguy.com!newsp.newsguy.com!mww In article , Neil Franklin writes: > mww@microfocus.com (Michael Wojcik) writes: > > > > In article , Neil Franklin > > writes: > > > > > > [re RISC design philosophy: where's the cutoff] > > In the case of the PPC the "small and often" is actually quite > large. Mainly due to its aim at commercial processing (it was invented > by IBM), where the "cut off" line for "still an advantage" is higher > than for engineering/scientific calculations that the Mips and Sparc > were optimised for. It is the old 7040 vs 1130 (or 360/xx vs 360/yy) > issue. True, true. The _RISC System/6000 Technology_ book I mentioned in my previous post and a lot of early _AIXpert_ articles and similar IBM materials go to some length to push the RIOS / POWER architecture (on which POWER2 and PPC were based, though PPC had some notable contribu- tions from Motorola as well) as an appropriate engine for business applications. The original RIOS didn't have wildly impressive integer performance, but being able to move 8 bytes of string data per cycle made it great for DP that didn't involve a lot of number crunching. When the 6000 first went into limited-availability, I was working at IBM in the same building - same floor, in fact - as the Cambridge (Massachusetts) RS/6000 Porting Center. Much of the software being ported was commercial rather than scientific or engineering. > > Others disagree. > > I don't. It is horses for courses. You need to be fast on _your_ > job. I run xterm/Emacs/Netscape im my Mips, my neighbor runs > Office/Filemaker on his PPC. Yes, though I'm running xterm/some other editor/Netscape on PPC myself. (But very little I do on this machine - an RS/6000 25T that I use as a development workstation - is compute-bound. The most compute-intensive jobs I run on a regular basis are optimizing compiles, which do run faster on newer machines like my UltraSPARC 5, but don't take prohibitively long here.) The point's well taken; so many factors besides CPU throughput (for a particular instruction mix and data layout - things like cache associativity can make or break performance too) can be the bottleneck that design principles like "reduce complexity" are relevant in only the broadest of contexts. Michael Swaine reported (in the August _Dr. Dobb's_) that David Patterson is now interested in vector processors and ALUs built into RAM chips, for example. Patterson, the guy behind SPARC, is now working on an even more "reduced" CPU design. (Actually, it's not really a CPU at all; it's decentralized.) Here, the target application is multimedia: real-time DSP-like processing of large amounts of data in limited precision. This suggests a variation of an a.f.c chestnut: whom would people nominate for "the inventor of RISC"? (That's a deliberately perverse question, of course - it has to be "inventors" - but I thought I'd keep it parallel to the perennial "who invented the computer" thread.) Swaine describes Patterson as "best known as the inventor of RISC", for the Berkeley RISC I project. Back at IBM, folks liked to pin the ribbon on the 801 (which I believe dates back to the 1970s, though Radin's ACM paper on it was 1982). I'm pretty sure the 801 predated the ROMP (Research/Office Microprocessor), which was the basis for the IBM PC RT's CPU. It seems to me that some IBM ad credited Phil Hester or John Cocke or someone like that with inventing RISC and (later) superscalar RISC architectures, but I don't have a citation. Other takers? Michael Wojcik mww@microfocus.com AAI Development, Micro Focus Inc. Department of English, Miami University Company Secretary Finance Manager 1) Half-grey haired executives. 2) Must be waist-deep in their field of activities. 3) Must be having the know-how and the do-how of the latest developments in their respective fields. -- from "Appointments Vacant" section of Business India ###### From: Kin Hoong CHUNG Newsgroups: alt.folklore.computers Subject: Re: RISC philosophy (was Re: Transmeta's Little Secret) Date: 9 Oct 1998 06:30:07 GMT Organization: University of New South Wales Lines: 18 Message-ID: <6vkahf$80q$1@mirv.unsw.edu.au> References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> <6vdtpa$3qf@news3.newsguy.com> <6vj8re$6s7@news3.newsguy.com> NNTP-Posting-Host: alpha.maths.unsw.edu.au User-Agent: tin/pre-1.4-980618 (UNIX) (OSF1/V4.0 (alpha)) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newscore.univie.ac.at!btnet-peer!btnet!news.maxwell.syr.edu!sunqbc.risq.qc.ca!news.uow.edu.au!news.usyd.edu.au!unsw.edu.au!not-for-mail Michael Wojcik wrote: : This suggests a variation of an a.f.c chestnut: whom would people : nominate for "the inventor of RISC"? (That's a deliberately : perverse question, of course - it has to be "inventors" - but I : thought I'd keep it parallel to the perennial "who invented the : computer" thread.) [contenders deleted] How about the late Seymour Cray? Was there not a story that one of his earlier CPU's did not have an unconditional branch? This raises the next question: what did Cray _not_ invent :-). Cheers, Kin Hoong ###### From: hnsngr@sirius.com (Ron Hunsinger) Newsgroups: alt.folklore.computers Subject: Re: RISC philosophy (was Re: Transmeta's Little Secret) Date: Fri, 09 Oct 1998 13:04:29 -0700 Organization: ErsteSoft Lines: 10 Message-ID: References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> <6vdtpa$3qf@news3.newsguy.com> <6vj8re$6s7@news3.newsguy.com> <6vkahf$80q$1@mirv.unsw.edu.au> NNTP-Posting-Host: ppp-asok02--062.sirius.net Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Newsreader: Yet Another NewsWatcher 2.3.1 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.belnet.be!212.63.192.161.MISMATCH!newshub.bart.net!news.tele2.nl!newsfeed1.swip.net!swipnet!newsfeed.berkeley.edu!su-news-hub1.bbnplanet.com!news.bbnplanet.com!news1.best.com!newshub.sirius.com!newsfiler.sirius.com!hnsngr In article <6vkahf$80q$1@mirv.unsw.edu.au>, Kin Hoong CHUNG wrote: > This raises the next question: what did Cray _not_ invent :-). Virtual memory. Bloatware. -Ron Hunsinger ###### From: info@fdhoekstra.nl Newsgroups: alt.folklore.computers Subject: Re: RISC philosophy (was Re: Transmeta's Little Secret) Date: Fri, 09 Oct 1998 15:16:41 +0200 Organization: Drukkerij Uitgeverij F. D. Hoekstra bv Lines: 12 Message-ID: <361E0CB9.627D@fdhoekstra.nl> References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> <6vdtpa$3qf@news3.newsguy.com> <6vj8re$6s7@news3.newsguy.com> NNTP-Posting-Host: zwl1-p97.worldonline.nl Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 3.01Gold (Win95; I) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.belnet.be!newsgate.cistron.nl!het.net!news.worldonline.nl!not-for-mail Michael Wojcik wrote: > This suggests a variation of an a.f.c chestnut: whom would people > nominate for "the inventor of RISC"? (That's a deliberately > perverse question, of course - it has to be "inventors" - but I > thought I'd keep it parallel to the perennial "who invented the > computer" thread.) Charles Babbage. Only two operations: addition and repetition. Even multiplication was done in soft- (well, really wet-) ware. Richard ###### From: jones@cs.uiowa.edu (Douglas W. Jones,201H MLH,3193350740,3193382879) Newsgroups: alt.folklore.computers Subject: Re: RISC philosophy (was Re: Transmeta's Little Secret) Date: 9 Oct 1998 15:07:57 GMT Organization: The University of Iowa Lines: 46 Message-ID: <6vl8sd$cmi$1@flood.weeg.uiowa.edu> References: <361E0CB9.627D@fdhoekstra.nl> NNTP-Posting-Host: pyrite.cs.uiowa.edu Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.belnet.be!newsfeed.wirehub.nl!btnet-peer!btnet!newsfeed.cwix.com!207.172.3.37!feed1.news.rcn.net!rcn!newsfeed.enteract.com!news-xfer.siscom.net!streamer1.cleveland.iagnet.net!NewsNG.Chicago.Qual.Net!news.uiowa.edu!not-for-mail Michael Wojcik wrote: > This suggests a variation of an a.f.c chestnut: whom would people > nominate for "the inventor of RISC"? (That's a deliberately > perverse question, of course - it has to be "inventors" - but I > thought I'd keep it parallel to the perennial "who invented the > computer" thread.) All early computers had comparatively simple instruction sets, but to call them RISC machines misuses the term. I can think of two major computer architectures developed in the 1960's that had RISC style load-store instruction sets. The CDC 6600, designed by Seymour Cray, had a wierd instruction set, with 15 and 30 bit instructions packed into 60 bit words, but it had a pure load-store architecture, and it had wildly parallel instruction execution inside the CPU, although not based on the pipelined model we use today. The Data General Nova, designed by Edison DeCastro, has a very clear load-store architecture and the potential for single-cycle execution, but the possibility of pipelining the design was not what motivated this; rather, the goal was to build a very inexpensive yet effective minicomputer. Gordon Bell's comparative evaluation of the Data General Nova and the DEC PDP-11 is one of the first papers I've read that clearly points out the difference between what we now call the RISC and CISC philosophies. The terms had not yet been invented, however. Bell pointed out the fact that the Nova and the PDP-11 achieved comparable price-performance using vastly different methods, and his paper may have pointed out how simple it would be to pipeline a machine with a Nova-like architecture. In any case, the modern RISC revolution grew out of that era, with parallel ventures at IBM, Berkeley and Stanford. The IBM 801 begat the Power PC, with a few generations of work between then and now. The Stanford MIPS begat the current SGI architecture, with a few generations between, and the Berkeley people coined the term RISC, as near as I can tell. I believe that there may be some interesting connections between the Berkely RISC and the HP-PA RISC, but they're not as strong as those connecting the IBM 801 to the PPC or the Stanford MIPS to the SGI CPU family. Doug Jones jones@cs.uiowa.edu ###### From: crosby@nag.cs.colorado.edu (Matthew Crosby) Newsgroups: alt.folklore.computers Subject: Re: RISC philosophy (was Re: Transmeta's Little Secret) Date: 9 Oct 1998 21:24:45 GMT Organization: University of Colorado, Boulder Lines: 17 Message-ID: <6vluut$ptt$1@csnews.cs.colorado.edu> References: <87g1dc92pd.fsf@dogbert.io.nu> <6vj8re$6s7@news3.newsguy.com> <6vkahf$80q$1@mirv.unsw.edu.au> NNTP-Posting-Host: nag.cs.colorado.edu Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!denver-news-feed1.bbnplanet.com!news.bbnplanet.com!coop.net!csnews!nag.cs.colorado.edu!crosby In article , Ron Hunsinger wrote: >In article <6vkahf$80q$1@mirv.unsw.edu.au>, Kin Hoong CHUNG > wrote: > >> This raises the next question: what did Cray _not_ invent :-). > >Virtual memory. > >Bloatware. > Parity. It's for farmers. -- Matthew Crosby crosby@cs.colorado.edu Disclaimer: It was in another country, and besides, the wench is dead. ###### Path: chonsp.franklin.ch!usenet From: Neil Franklin Newsgroups: alt.folklore.computers Subject: Re: RISC philosophy (was Re: Transmeta's Little Secret) Date: 09 Oct 1998 22:56:59 +0200 Organization: My own Private Self Lines: 66 Message-ID: References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> <6vdtpa$3qf@news3.newsguy.com> <6vj8re$6s7@news3.newsguy.com> X-Newsreader: Gnus v5.3/Emacs 19.34 mww@microfocus.com (Michael Wojcik) writes: > > The original RIOS didn't have wildly impressive integer performance, > but being able to move 8 bytes of string data per cycle made it > great for DP that didn't involve a lot of number crunching. 8 Bytes? The diagram I have here (in Microprosessors - a Programmers View, by Robert Dewar and Matthew Smosna) shows an 128 bit memory data bus, that would make it 16 bytes at a time. And then not forget them multi register block load instructions. Interestingly it was an very good superscalar processor (4 instructions at once) and so managed 100MFLOPS on ideally dynamically (!) vectorable code. Faster than any other microprocessor at that time. OK it was an 5/7 chip set (1 instruction, 1 integer, 1 float, 2/4 cache). > When the 6000 first went into limited-availability, I was working at > IBM in the same building - same floor, in fact - as the Cambridge > (Massachusetts) RS/6000 Porting Center. Much of the software being > ported was commercial rather than scientific or engineering. Not surprising with IBMs heritage, and the Power/PPC use in AS/400s. The virtual memory system design also shows commercial usage (larger address space 52 bit). > 5, but don't take prohibitively long here.) The point's well taken; > so many factors besides CPU throughput (for a particular instruction > mix and data layout - things like cache associativity can make or > break performance too) can be the bottleneck that design principles > like "reduce complexity" are relevant in only the broadest of > contexts. Of course memory speed today dominates processors. And IO speed dominates the entire system. One reason why I dislike the current Intel "you need more processor" attitude. I am writing this on an Cx486DX/4-100 - with 32MByte RAM an Matrox Millennium 8MB, SCSI. > This suggests a variation of an a.f.c chestnut: whom would people > nominate for "the inventor of RISC"? (That's a deliberately > > for the Berkeley RISC I project. Back at IBM, folks liked to pin > the ribbon on the 801 (which I believe dates back to the 1970s, > though Radin's ACM paper on it was 1982). I would nominate the 801, started in 1974. > I'm pretty sure the 801 > predated the ROMP (Research/Office Microprocessor), which was the > basis for the IBM PC RT's CPU. ROMP was an widened (24->32 bit) 801 with virtual memory and floating point added. Source same as above. -- *** New home Addresses Mail and Web *** home: neil@franklin.ch.remove http://neil.franklin.ch/ work: franklin@arch.ethz.ch.remove http://caad.arch.ethz.ch/~franklin/ Microsoft is Software Communism, Fight for GNU Freedom! ###### Path: chonsp.franklin.ch!usenet From: Neil Franklin Newsgroups: alt.folklore.computers Subject: Re: RISC philosophy (was Re: Transmeta's Little Secret) Date: 09 Oct 1998 22:59:59 +0200 Organization: My own Private Self Lines: 24 Message-ID: References: <361E0CB9.627D@fdhoekstra.nl> <6vl8sd$cmi$1@flood.weeg.uiowa.edu> X-Newsreader: Gnus v5.3/Emacs 19.34 jones@cs.uiowa.edu (Douglas W. Jones,201H MLH,3193350740,3193382879) writes: > > parallel ventures at IBM, Berkeley and Stanford. The IBM 801 begat > the Power PC, with a few generations of work between then and now. > The Stanford MIPS begat the current SGI architecture, with a few > generations between, Yes. > and the Berkeley people coined the term RISC, > as near as I can tell. I believe that there may be some interesting > connections between the Berkely RISC and the HP-PA RISC, but they're > not as strong as those connecting the IBM 801 to the PPC or the > Stanford MIPS to the SGI CPU family. Of course the major Berkely offshot is the Sun Sparc. -- *** New home Addresses Mail and Web *** home: neil@franklin.ch.remove http://neil.franklin.ch/ work: franklin@arch.ethz.ch.remove http://caad.arch.ethz.ch/~franklin/ Microsoft is Software Communism, Fight for GNU Freedom! ###### From: abaum@pa.dec.com (Allen J. Baum) Newsgroups: alt.folklore.computers Subject: Re: RISC philosophy (was Re: Transmeta's Little Secret) Date: Mon, 12 Oct 1998 16:58:07 -0700 Organization: Compaq Computer Lines: 13 Message-ID: References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> <6vdtpa$3qf@news3.newsguy.com> <6vj8re$6s7@news3.newsguy.com> NNTP-Posting-Host: althea.pa.dec.com X-Newsreader: MT-NewsWatcher 2.4 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.belnet.be!news-raspail.gip.net!news-peer.gip.net!news.gsl.net!gip.net!mr.net!data.pa.vix.com!news1.digital.com!pa.dec.com!src.dec.com!abaum In article , Neil Franklin wrote: > mww@microfocus.com (Michael Wojcik) writes: > > > > The original RIOS didn't have wildly impressive integer performance, > > but being able to move 8 bytes of string data per cycle .... > > 8 Bytes? The diagram I have here ..... shows an 128 bit memory data > bus, that would make it 16 bytes at a time. So, 16 bytes read in a cycle, and 16 bytes written in a cycle means 16 bytes moved in 2 cycles, or 8 bytes moved in 1 cycle.... ###### Newsgroups: alt.folklore.computers Subject: Re: RISC philosophy (was Re: Transmeta's Little Secret) References: <87g1dc92pd.fsf@dogbert.io.nu> <6vj8re$6s7@news3.newsguy.com> <6vkahf$80q$1@mirv.unsw.edu.au> <6vluut$ptt$1@csnews.cs.colorado.edu> From: Shaw Terwilliger Date: 12 Oct 1998 23:49:18 -0500 Message-ID: <87hfx9qd69.fsf@dogbert.io.nu> Lines: 9 X-Newsreader: Gnus v5.5/XEmacs 20.4 - "Emerald" NNTP-Posting-Host: dogbert.advancenet.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.belnet.be!news-raspail.gip.net!news-peer.gip.net!news.gsl.net!gip.net!news.maxwell.syr.edu!news.central.agis.net!agis!news.advancenet.net!dogbert.advancenet.net crosby@nag.cs.colorado.edu (Matthew Crosby) writes: > In article , > Parity. It's for farmers. Farmers buy a lot of computers. -- Shaw Terwilliger (twig@advancenet.net) ###### From: mww@microfocus.com (Michael Wojcik) Newsgroups: alt.folklore.computers Subject: Re: RISC philosophy (was Re: Transmeta's Little Secret) Date: 15 Oct 1998 01:14:52 GMT Organization: Micro Focus Inc. Lines: 41 Message-ID: <703iac$17u@news3.newsguy.com> References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> <6vdtpa$3qf@news3.newsguy.com> <6vj8re$6s7@news3.newsguy.com> NNTP-Posting-Host: p-727.newsdawg.com X-Newsreader: xrn 9.00 Originator: mww@raederle.microfocus.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!cyclone.bc.net!logbridge.uoregon.edu!pln-w!spln!extra.newsguy.com!newsp.newsguy.com!mww (I'm rather late on this, but...) In article , Neil Franklin writes: > mww@microfocus.com (Michael Wojcik) writes: > > > > The original RIOS didn't have wildly impressive integer performance, > > but being able to move 8 bytes of string data per cycle made it > > great for DP that didn't involve a lot of number crunching. > > 8 Bytes? The diagram I have here (in Microprosessors - a Programmers > View, by Robert Dewar and Matthew Smosna) shows an 128 bit memory data > bus, that would make it 16 bytes at a time. And then not forget them > multi register block load instructions. Yes, I have no idea what I was thinking. The original RIOS multiple- register load-store ("move assist") instructions moved up to 32, not 8, bytes at a time. Moving 8 bytes at a time was no great shakes when the RIOS came out, obviously. (Probably I was thinking "8 4- byte words" or something. Drat.) > Interestingly it was an very good superscalar processor (4 > instructions at once) and so managed 100MFLOPS on ideally dynamically > (!) vectorable code. Faster than any other microprocessor at that > time. OK it was an 5/7 chip set (1 instruction, 1 integer, 1 float, > 2/4 cache). Those floating point multiply-adds were nice, weren't they? Michael Wojcik mww@microfocus.com AAI Development, Micro Focus Inc. Department of English, Miami University This year's runner-up in the All-Usenet Creative Use Of English In A Quasi-Legal But Probably Completely Ineffectual Signature Statement: Disclaimer : I am a free denizen of this world and statements are of mine and solly mine. Nobody dare sue me as you may end up even loosing your attorney fees. -- Sridhar (holagundas@hotmail.com)