Sender: sterwill@dogbert.io.nu Newsgroups: alt.folklore.computers Subject: Transmeta's Little Secret From: Shaw Terwilliger Date: 28 Sep 1998 01:22:06 -0500 Message-ID: <87g1dc92pd.fsf@dogbert.io.nu> Lines: 19 X-Newsreader: Gnus v5.5/XEmacs 20.4 - "Emerald" NNTP-Posting-Host: dogbert.advancenet.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.belnet.be!news-raspail.gip.net!news-dc.gip.net!news-peer.gip.net!news.gsl.net!gip.net!news.maxwell.syr.edu!news.central.agis.net!agis!news.advancenet.net!dogbert.advancenet.net Linus Torvalds, I'm sure many of you know this name, has been with Transmeta for a few years now, and they've got what seems like a stockpile of very well-known, talented, and respected individuals, in addition to those who've contributed to Linux. Like most everyone else out there, I'm wondering just exactly what they're producing. Is it a new threaded processor? Something raw RISC with an x86 emulation? Just low power, low cost clones (I hope not)? Yes, this isn't really folklore, but I figured there would be no better place than my favorite group of old computer hackers to gather (qualified?) speculation. I'd dig up a few links, but slashd^Wreference material is currently unavailable. -- Shaw Terwilliger (twig@advancenet.net) ###### From: andrewsmith@earthlink.net Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: Wed, 30 Sep 1998 18:51:55 GMT Organization: Deja News - The Leader in Internet Discussion Lines: 105 Message-ID: <6utukb$3an$1@nnrp1.dejanews.com> References: <87g1dc92pd.fsf@dogbert.io.nu> NNTP-Posting-Host: 204.146.164.37 X-Article-Creation-Date: Wed Sep 30 18:51:55 1998 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.0b1; Windows NT 5.0) X-Http-Proxy: 1.0 x7.dejanews.com:80 (Squid/1.1.22) for client 204.146.164.37 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.belnet.be!newspump.monmouth.com!newspeer.monmouth.com!nntp.giganews.com!nntp2.dejanews.com!nnrp1.dejanews.com!not-for-mail Interesting. Very interesting. With Linus in charge, I assume they would give away machines for the good of the community? ( :-) ) anyway this is what I dug up "Another clone contender, Transmeta, will also reveal their product plans. Transmeta is expected to show off a Reduced Instruction Set Chip (RISC) that can read instructions written for an Intel chip, said sources. " http://www.news.com/News/Item/0,4,26648,00.html and "Two newcomers, Transmeta and Rise, are working on low-cost, low-powered chips for desktops and portables. A third, Metaflow, is planning an Intel clone with parent company ST Microelectronics." http://www.news.com/News/Item/0,4,25960,00.html The RISC thing sounds the most likely. But they are also doing some sort of kernel development. Check out the job postings at http://www.uwsg.indiana.edu/hypermail/linux/kernel/9706.2/0223.html they are looking for "Kernel Development,Compiler’s,Systems Administration,Compatibility Testing,3D Graphics,and Verification." http://www.theregister.co.uk/980928-000002.html of course tells a bit also. They say that since Linus was hired "Reliable sources said that the company has re-engineered itself and is now preparing a Risc processor which will be optimised for Windows NT 5.0, and which will effectively abandon legacy support for Dos and 16 bit Windows. " This seems to say that Linus & Microsoft will be in bed together!! What a kick! This will take the zealots for a schock by using dejanews you can see what these guys are looking for. But it may not be work related. In particular do a search on hpa@transmeta.com, who seems to answer a lot of questions. But is also having trouble setting up a Windows 95 computer.... interesting also I saw that people say Paul Allen is behind Transmeta's financing. In a big way. In my mind that means Transmeta is a "black" project -- (you know like a top secret operation) secretly funded by Microsoft. Prediction: Transmeta will introduce a RISC Based processor, and a Custom Operating System The Operating System will be capable of running all things NT (not dos, not windows 16 bit, and maybe not even some windows 95 junk) The box will be under $1,500 It will provide speeds comparable to and better than Alpha systems It will carry a transmeta logo, carry a linus' signature, and be the greatest thing for Microsoft (because it's competition that they have a lot to do with) Enraged Linux zealots will jump out of buildings because Linus' has sold out and is now playing golf with the big Bill. The OS will be Be, but with marketing and software. Rhapsodey, but it really gets here. NT, but with complete unix compatability built in -- Linux is building a software base, Oracle and IBM are already talking about making their products fully available on Linux -- you know what that means? They will be running native on the Transmeta box without a blink of the eye. In article <87g1dc92pd.fsf@dogbert.io.nu>, Shaw Terwilliger wrote: > > Linus Torvalds, I'm sure many of you know this name, has > been with Transmeta for a few years now, and they've got > what seems like a stockpile of very well-known, talented, > and respected individuals, in addition to those who've contributed > to Linux. Like most everyone else out there, I'm wondering > just exactly what they're producing. Is it a new threaded > processor? Something raw RISC with an x86 emulation? > Just low power, low cost clones (I hope not)? > > Yes, this isn't really folklore, but I figured there would be > no better place than my favorite group of old computer hackers > to gather (qualified?) speculation. > > I'd dig up a few links, but slashd^Wreference material is > currently unavailable. > > -- > Shaw Terwilliger (twig@advancenet.net) > ‰ -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own ###### From: lucvdv@null.net (Luc Van der Veken) Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: Thu, 01 Oct 1998 17:10:31 GMT Organization: . Lines: 10 Message-ID: <3613b3c9.725353@news.innet.be> References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> NNTP-Posting-Host: pool02b-194-7-145-38.uunet.be Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Newsreader: Forte Agent 1.5/32.451 X-No-Archive: yes Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.belnet.be!isdnet!news-raspail.gip.net!netnews.globalip.ch!news-lond.gip.net!news.gsl.net!gip.net!rill.news.pipex.net!pipex!join.news.pipex.net!pipex!krypton.inbe.net!INbe.net!not-for-mail Also sprach andrewsmith@earthlink.net on Wed, 30 Sep 1998 18:51:55 GMT to alt.folklore.computers: > This seems to say that Linus & Microsoft will be in bed together!! What a > kick! Archived for future reference. If only 1/4 of what you seem to expect comes true, it would _still_ be a Good Thing. ###### From: spam@orion-com.com (Joe Thompson) Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: Sun, 04 Oct 1998 13:33:27 -0400 Organization: Orion Computer Consulting Lines: 19 Message-ID: References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> NNTP-Posting-Host: user-37kba9t.dialup.mindspring.com X-Server-Date: 4 Oct 1998 17:33:14 GMT X-Newsreader: MT-NewsWatcher 2.4.4 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!news.bbnplanet.com!firehose.mindspring.com!spam In article , Bruce Cook wrote: > andrewsmith@earthlink.net writes: > > [...] > > Transmeta is expected to show off a Reduced Instruction Set Chip (RISC) that > > can read instructions written for an Intel chip, said sources. " > > Hmmm... is it me or does this seem a little self contradictory. Not really. The PowerPC is a RISC chip that can read instructions written for a Motorola 68000-series chip, so it can be done. Granted, you get better performance out of a 66-MHz 68040 than you do out of a first-generation PPC running at 66 MHz. -- Joe -- Joe Thompson | "Boiling, carbonated coffee." -- Thorfinn spam@orion-com.com | http://kensey.home.mindspring.com/ Charlottesville, VA | O- He-Who-Grinds-the-Unworthy | I have brown eyes AND I VOTE! ###### From: Bruce Cook Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: 05 Oct 1998 00:53:37 -0800 Organization: Synonet Corporation - The Bicycle Factory Lines: 14 Message-ID: References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> NNTP-Posting-Host: per4-224.wantree.com.au X-Newsreader: Gnus v5.3/Emacs 19.34 Cache-Post-Path: cletus.smithst!unknown@donal.tara X-Cache: nntpcache 2.3.3b3 (see http://www.nntpcache.org/) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!news.mel.connect.com.au!news.per.connect.com.au!news.waia.asn.au!news.wantree.com.au!not-for-mail andrewsmith@earthlink.net writes: [...] > Transmeta is expected to show off a Reduced Instruction Set Chip (RISC) that > can read instructions written for an Intel chip, said sources. " Hmmm... is it me or does this seem a little self contradictory. -- ...BRU Bruce Cook, Synonet Corp. E-Mail: bruce@bicycle.synonet.com Phone: +61 147 967 468 Fax: +61 8 9227 7390 ###### Path: chonsp.franklin.ch!usenet From: Neil Franklin Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: 04 Oct 1998 21:01:45 +0200 Organization: My own Private Self Lines: 23 Message-ID: References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> X-Newsreader: Gnus v5.3/Emacs 19.34 spam@orion-com.com (Joe Thompson) writes: > > Not really. The PowerPC is a RISC chip that can read instructions written > for a Motorola 68000-series chip, so it can be done. Granted, you get > better performance out of a 66-MHz 68040 than you do out of a > first-generation PPC running at 66 MHz. -- Joe Error. No PPC chip can read 68k instructions. The PPC 615 was intended to run 80x86 instructions but that project was scrapped before seeing the daylight. Macs can run 68k software because Apple put into the PPC Mac OS an emulator. But this is normal PPC software external to the PPC chip. The PPC is simply so fast that running an emulator is acceptable for not too often used pieces of the Mac OS and not too processor intensive applications. -- *** New home Addresses Mail and Web *** home: neil@franklin.ch.remove http://neil.franklin.ch/ work: franklin@arch.ethz.ch.remove http://caad.arch.ethz.ch/~franklin/ Microsoft is Software Communism, Fight for GNU Freedom! ###### From: spam@orion-com.com (Joe Thompson) Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: Mon, 05 Oct 1998 00:35:44 -0400 Organization: Orion Computer Consulting Lines: 28 Message-ID: References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> NNTP-Posting-Host: user-37kba8u.dialup.mindspring.com X-Server-Date: 5 Oct 1998 04:32:26 GMT X-Newsreader: MT-NewsWatcher 2.4.4 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.belnet.be!news-raspail.gip.net!news-peer.gip.net!news.gsl.net!gip.net!cpk-news-hub1.bbnplanet.com!news.bbnplanet.com!firehose.mindspring.com!spam In article , Neil Franklin wrote: > spam@orion-com.com (Joe Thompson) writes: > > > > Not really. The PowerPC is a RISC chip that can read instructions written > > for a Motorola 68000-series chip, so it can be done. Granted, you get > > better performance out of a 66-MHz 68040 than you do out of a > > first-generation PPC running at 66 MHz. -- Joe > > Error. No PPC chip can read 68k instructions. The PPC 615 was intended > to run 80x86 instructions but that project was scrapped before seeing > the daylight. > > Macs can run 68k software because Apple put into the PPC Mac OS an > emulator. But this is normal PPC software external to the PPC chip. > The PPC is simply so fast that running an emulator is acceptable for > not too often used pieces of the Mac OS and not too processor > intensive applications. OK, my mistake. The point being: running CISC instructions on a RISC chip via hardware emulation is not that far-fetched at all. Anything that can be done in software can also be done in hardware. -- Joe -- Joe Thompson | "Boiling, carbonated coffee." -- Thorfinn spam@orion-com.com | http://kensey.home.mindspring.com/ Charlottesville, VA | O- He-Who-Grinds-the-Unworthy | I have brown eyes AND I VOTE! ###### From: bayko@borealis.cs.uregina.ca (John Bayko) Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: 5 Oct 1998 02:36:08 GMT Organization: University of Regina, Dept. of Computer Science Lines: 15 Message-ID: <6v9bao$goi$1@sue.cc.uregina.ca> References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> NNTP-Posting-Host: borealis.cs.uregina.ca Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!cyclone.news.idirect.com!island.idirect.com!cyclone.mbnet.mb.ca!canopus.cc.umanitoba.ca!mongol.sasknet.sk.ca!news.uregina.ca!not-for-mail In article , Bruce Cook wrote: >andrewsmith@earthlink.net writes: >[...] >> Transmeta is expected to show off a Reduced Instruction Set Chip (RISC) that >> can read instructions written for an Intel chip, said sources. " > >Hmmm... is it me or does this seem a little self contradictory. It's marketing-speak - of course it's contradictory. -- John Bayko (Tau). bayko@cs.uregina.ca http://www.cs.uregina.ca/~bayko ###### From: bayko@borealis.cs.uregina.ca (John Bayko) Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: 5 Oct 1998 02:38:43 GMT Organization: University of Regina, Dept. of Computer Science Lines: 24 Message-ID: <6v9bfj$goq$1@sue.cc.uregina.ca> References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> NNTP-Posting-Host: borealis.cs.uregina.ca Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!sunqbc.risq.qc.ca!cyclone.mbnet.mb.ca!canopus.cc.umanitoba.ca!mongol.sasknet.sk.ca!news.uregina.ca!not-for-mail In article , Joe Thompson wrote: >In article , > Bruce Cook wrote: >> andrewsmith@earthlink.net writes: >> [...] >>> Transmeta is expected to show off a Reduced Instruction Set Chip (RISC) that >>> can read instructions written for an Intel chip, said sources. " >> >> Hmmm... is it me or does this seem a little self contradictory. > >Not really. The PowerPC is a RISC chip that can read instructions written >for a Motorola 68000-series chip, so it can be done. Granted, you get >better performance out of a 66-MHz 68040 than you do out of a >first-generation PPC running at 66 MHz. -- Joe No it can't. Don't mistake the 68040 emulator which Apple included in the Power Macintoshes for anything that the PowerPC itself can do (I've noticed a few people make this mistake... I wonder why). -- John Bayko (Tau). bayko@cs.uregina.ca http://www.cs.uregina.ca/~bayko ###### From: Hugo Pozzanski Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: Mon, 05 Oct 1998 10:15:50 +0100 Organization: =?iso-8859-1?Q?=A0?= Lines: 20 Message-ID: <36188E46.580E31B2@mindless.com> References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> NNTP-Posting-Host: boletus.atml.co.uk Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Server-Date: 5 Oct 1998 09:16:42 GMT X-Mailer: Mozilla 4.5b2 [en] (Win95; I) X-Accept-Language: en,ja Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!btnet-peer!btnet!newsfeed.ecrc.net!join.news.pipex.net!pipex!virata.com!not-for-mail Bruce Cook wrote: > > andrewsmith@earthlink.net writes: > > [...] > > Transmeta is expected to show off a Reduced Instruction Set Chip (RISC) that > > can read instructions written for an Intel chip, said sources. " > > Hmmm... is it me or does this seem a little self contradictory. Intel and HP once said they'll have a VLIW chip for 1998, which will be able to execute it's own native opcodes, Intel's 80x86 family, and also HP PA RISC! All that on one chip!! BTW, What year is it? -- Hugo Pozzanski... ###### From: Hugo Pozzanski Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: Mon, 05 Oct 1998 10:18:48 +0100 Organization: =?iso-8859-1?Q?=A0?= Message-ID: <36188EF8.F4F39239@mindless.com> References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> NNTP-Posting-Host: boletus.atml.co.uk Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Server-Date: 5 Oct 1998 09:19:40 GMT X-Mailer: Mozilla 4.5b2 [en] (Win95; I) X-Accept-Language: en,ja Lines: 19 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newscore.univie.ac.at!btnet-peer!btnet!dispose.news.demon.net!demon!newsfeed.icl.net!join.news.pipex.net!pipex!virata.com!not-for-mail Neil Franklin wrote: > > > Macs can run 68k software because Apple put into the PPC Mac OS an > emulator. But this is normal PPC software external to the PPC chip. > The PPC is simply so fast that running an emulator is acceptable for > not too often used pieces of the Mac OS and not too processor > intensive applications. Was it not the case when the PPC based Apples came out, the OS had to switch to 68K mode (by means of emulation - of course ;-) 80% of the time? -- Hugo Pozzanski... ###### From: "Samael" Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: Mon, 5 Oct 1998 13:26:21 +0100 Lines: 27 Message-ID: <3618baee.0@122.122.122.1> References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> <6v9bao$goi$1@sue.cc.uregina.ca> NNTP-Posting-Host: 195.147.8.88 X-Newsreader: Microsoft Outlook Express 4.72.3110.5 X-MimeOLE: Produced By Microsoft MimeOLE V4.72.3110.3 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newscore.univie.ac.at!newsfeed.ecrc.net!nntp.news.xara.net!xara.net!news.itg.net.uk!122.122.122.1!122.122.122.1 John Bayko wrote in message <6v9bao$goi$1@sue.cc.uregina.ca>... >In article , > Bruce Cook wrote: >>andrewsmith@earthlink.net writes: >>[...] >>> Transmeta is expected to show off a Reduced Instruction Set Chip (RISC) that >>> can read instructions written for an Intel chip, said sources. " >> >>Hmmm... is it me or does this seem a little self contradictory. > > It's marketing-speak - of course it's contradictory. Theres no reason you couldn't design a chip with two modes, emulator and real. Then have the amulator mode do calls to the real mode using a translator in real-time. Programs using the emulator will run more slowly than programs that write direct to the metal, but hey, it will still work and 5 years later, you can take the emulators out of the new chips because all recent software will runn direct to the real mode. Samael ###### From: tph@longhorn.uucp (Tom Harrington) Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: 5 Oct 1998 16:21:06 GMT Organization: Mechanist Industries Lines: 22 Message-ID: <6varli$fjs3@eccws1.dearborn.ford.com> References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> <6v9bfj$goq$1@sue.cc.uregina.ca> Reply-To: tph@rmi.net NNTP-Posting-Host: cs0053.eld.ford.com X-Newsreader: TIN [version 1.2 PL2] Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!howland.erols.net!newsxfer.itd.umich.edu!news2.acs.oakland.edu!jobone!dailyplanet.srl.ford.com!eccws1.dearborn.ford.com!longhorn!tph John Bayko (bayko@borealis.cs.uregina.ca) wrote: : In article , : Joe Thompson wrote: : > : >Not really. The PowerPC is a RISC chip that can read instructions written : >for a Motorola 68000-series chip, so it can be done. Granted, you get : >better performance out of a 66-MHz 68040 than you do out of a : >first-generation PPC running at 66 MHz. -- Joe : No it can't. Don't mistake the 68040 emulator which Apple included : in the Power Macintoshes for anything that the PowerPC itself can do : (I've noticed a few people make this mistake... I wonder why). Apple did such a good job integrating the 68k emulation into the overall system that it provided a pretty convincing illusion of binary compatibility. Older 68k code just ran, without trouble, though (as noted above) not at optimal speeds. -- Tom Harrington --------- tph@rmii.com -------- http://rainbow.rmii.com/~tph This message was printed on all-new, 100% virgin electrons Cookie's Revenge: ftp://ftp.rmi.net/pub2/tph/cookie/cookies-revenge.sit.hqx ###### From: $spam$@orion-com.com (Joe Thompson) Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: Mon, 05 Oct 1998 21:28:29 -0400 Organization: Orion Computer Consulting Lines: 34 Message-ID: <$spam$-0510982128300001@user-37kba8a.dialup.mindspring.com> References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> NNTP-Posting-Host: user-37kba8a.dialup.mindspring.com X-Server-Date: 6 Oct 1998 01:28:14 GMT X-Newsreader: MT-NewsWatcher 2.4.4 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.belnet.be!isdnet!news-raspail.gip.net!news-peer.gip.net!news.gsl.net!gip.net!cpk-news-hub1.bbnplanet.com!news.bbnplanet.com!firehose.mindspring.com!$spam$ In article , Neil Franklin wrote: > spam@orion-com.com (Joe Thompson) writes: > > > OK, my mistake. The point being: running CISC instructions on a RISC chip > > via hardware emulation is not that far-fetched at all. Anything that can > > be done in software can also be done in hardware. -- Joe > > Just the small problem that doing it in hardware violates the entire > RISC design philosophy (make the basic stuff fast in hardware, do the > rest in software. It should be faster in hardware. You could have a "mode switch" that flips you from RISC to CISC, or the other way. I'm not saying it's necessarily the *best* idea, or even a *good* idea -- just that it can be done. > > | I have brown eyes AND I VOTE! > > This must be some non-portable U.S.ism. Could you enlight us outsiders? There are a ton of bumper stickers here in the US that say things like "I'm Pro-Life AND I VOTE", and other such. Since I consider single-issue voting rather... less than intelligent, this is my subtle way of spoofing it. Really it's just there because I couldn't think of a good quote while I was redesigning my sig. -- Joe -- Joe Thompson | "Boiling, carbonated coffee." -- Thorfinn $spam$@orion-com.com | http://kensey.home.mindspring.com/ Charlottesville, VA | O- He-Who-Grinds-the-Unworthy | I have brown eyes AND I VOTE! ###### Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret References: <87g1dc92pd.fsf@dogbert.io.nu> Organization: Plethora . Net - More Net, Less Spam! X-Newsreader: trn 4.0-test62 (21 February 1998) From: seebs@plethora.net (Peter Seebach) Lines: 22 Message-ID: Date: Mon, 05 Oct 1998 23:28:41 GMT NNTP-Posting-Host: 205.166.146.8 X-Trace: ptah.visi.com 907630121 205.166.146.8 (Mon, 05 Oct 1998 18:28:41 CDT) NNTP-Posting-Date: Mon, 05 Oct 1998 18:28:41 CDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!chippy.visi.com!news-out.visi.com!ptah.visi.com!not-for-mail In article , Neil Franklin wrote: >> | I have brown eyes AND I VOTE! >This must be some non-portable U.S.ism. Could you enlight us outsiders? I assume it's just a take-off on the vast array of "I believe in X and I vote" bumper stickers one sees, which are intended to tell politicians that this belief is held by someone whose opinions may affect their next election. My favorite of all time is a friend's brilliant I eat my young and I vote. I love silly bumper stickers. Another friend came up with Unplanned Pregnancy What a Beautiful Choice -s -- Copyright 1998, All rights reserved. Peter Seebach / seebs@plethora.net C/Unix wizard, Pro-commerce radical, Spam fighter. Boycott Spamazon! Seeking interesting programming projects. Not interested in commuting. Visit my new ISP --- More Net, Less Spam! ###### Path: chonsp.franklin.ch!usenet From: Neil Franklin Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: 05 Oct 1998 23:55:35 +0200 Organization: My own Private Self Lines: 36 Message-ID: References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> X-Newsreader: Gnus v5.3/Emacs 19.34 spam@orion-com.com (Joe Thompson) writes: > > wrote: > > > Error. No PPC chip can read 68k instructions. The PPC 615 was intended > > to run 80x86 instructions but that project was scrapped before seeing > > the daylight. > > > > Macs can run 68k software because Apple put into the PPC Mac OS an > > emulator. But this is normal PPC software external to the PPC chip. > > OK, my mistake. The point being: running CISC instructions on a RISC chip > via hardware emulation is not that far-fetched at all. Anything that can > be done in software can also be done in hardware. -- Joe Just the small problem that doing it in hardware violates the entire RISC design philosophy (make the basic stuff fast in hardware, do the rest in software. The MIPS R4600 RISC I use at work can not even do virtual address translation without calling OS routines! The hardware only has an small associative RAM translation table for the last 32..64 translated pages. If the desired page is not one of them you get an exeption trap to the OS (IRIX). > | I have brown eyes AND I VOTE! This must be some non-portable U.S.ism. Could you enlight us outsiders? -- *** New home Addresses Mail and Web *** home: neil@franklin.ch.remove http://neil.franklin.ch/ work: franklin@arch.ethz.ch.remove http://caad.arch.ethz.ch/~franklin/ Microsoft is Software Communism, Fight for GNU Freedom! ###### Path: chonsp.franklin.ch!usenet From: Neil Franklin Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: 05 Oct 1998 23:57:09 +0200 Organization: My own Private Self Lines: 21 Message-ID: References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> <36188EF8.F4F39239@mindless.com> X-Newsreader: Gnus v5.3/Emacs 19.34 Hugo Pozzanski writes: > > Neil Franklin wrote: > > > > The PPC is simply so fast that running an emulator is acceptable for > > not too often used pieces of the Mac OS and not too processor > > intensive applications. > > Was it not the case when the PPC based Apples came out, the OS had to > switch to 68K mode (by means of emulation - of course ;-) 80% of the > time? I don't know the exact number, but it was certainly the majority in early System 7 variants. It is still above 0% in System 8.1. -- *** New home Addresses Mail and Web *** home: neil@franklin.ch.remove http://neil.franklin.ch/ work: franklin@arch.ethz.ch.remove http://caad.arch.ethz.ch/~franklin/ Microsoft is Software Communism, Fight for GNU Freedom! ###### From: mww@microfocus.com (Michael Wojcik) Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: 6 Oct 1998 19:03:37 GMT Organization: Micro Focus Inc. Lines: 44 Message-ID: <6vdpi9$2gk@news3.newsguy.com> References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> NNTP-Posting-Host: p-823.newsdawg.com X-Newsreader: xrn 9.00 Originator: mww@raederle.microfocus.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.belnet.be!212.63.192.161.MISMATCH!newshub.bart.net!news.tele2.nl!newsfeed1.swip.net!swipnet!newsfeed.berkeley.edu!su-news-hub1.bbnplanet.com!news.bbnplanet.com!pln-w!spln!extra.newsguy.com!newsp.newsguy.com!mww In article , spam@orion-com.com (Joe Thompson) writes: > In article , Neil Franklin > wrote: > > > spam@orion-com.com (Joe Thompson) writes: > > > > > > Not really. The PowerPC is a RISC chip that can read instructions written > > > for a Motorola 68000-series chip, so it can be done. Granted, you get > > > better performance out of a 66-MHz 68040 than you do out of a > > > first-generation PPC running at 66 MHz. -- Joe > > > > Error. No PPC chip can read 68k instructions. The PPC 615 was intended > > to run 80x86 instructions but that project was scrapped before seeing > > the daylight. > > > > [snip] > > OK, my mistake. The point being: running CISC instructions on a RISC chip > via hardware emulation is not that far-fetched at all. Anything that can > be done in software can also be done in hardware. -- Joe The PPC 615 never made it out the door (anyone at IBM / Motorola / Sommerset know if they ever had a working prototype, even?), but IIRC, according to _Byte_, the NexGen nx586 architecture used a RISC core with a decoding unit that converted x86 instructions into a variable number (1-7, I think) of "real" nx586 operations. Isn't this still used by AMD in its 586-class CPUs? Of course, the 615 was supposed to expose both the x86 instruction set and the PPC (much like the memory-access-endianness bit in the MSR), selected as part of a context switch, whereas AFAIK the NexGen did not permit nx586-RISC binaries. Michael Wojcik mww@microfocus.com AAI Development, Micro Focus Inc. Department of English, Miami University Unlikely predition o' the day: Eventually, every programmer will have to write a Java or distributed object program. -- Orfali and Harkey, _Client / Server Programming with Java and CORBA_ ###### From: lisard@zetnet.co.uk Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: 6 Oct 1998 19:55:39 GMT Message-ID: <6vdsjr$fil$9@irk.zetnet.co.uk> References: <3618baee.0@122.122.122.1> NNTP-Posting-Host: man-150.dialup.zetnet.co.uk X-Trace: irk.zetnet.co.uk 907703739 15957 194.247.40.191 (6 Oct 1998 19:55:39 GMT) NNTP-Posting-Date: 6 Oct 1998 19:55:39 GMT X-Everything: Net-Tamer V 1.08X Lines: 14 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!btnet-peer!btnet!dispose.news.demon.net!demon!peer.news.zetnet.net!zetnet.co.uk!not-for-mail On 1998-10-05 samael@dial.pipex.com said: :Theres no reason you couldn't design a chip with two modes, :emulator and real. Then have the amulator mode do calls to the :real mode using a translator in real-time. qv. Cyrix M1. Unfortunately, it isn't going to happen when every x86 maker that takes this approach uses their own RISC engine, which has its own set of "real" instructions. Whilst there's a lowest common denominator it will be used exclusively. -- Communa (together) we remember... we'll see you falling you know soft spoken changes nothing to sing within her... ###### From: lisard@zetnet.co.uk Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: 6 Oct 1998 19:55:41 GMT Message-ID: <6vdsjt$fil$10@irk.zetnet.co.uk> References: NNTP-Posting-Host: man-150.dialup.zetnet.co.uk X-Trace: irk.zetnet.co.uk 907703741 15957 194.247.40.191 (6 Oct 1998 19:55:41 GMT) NNTP-Posting-Date: 6 Oct 1998 19:55:41 GMT X-Everything: Net-Tamer V 1.08X Lines: 12 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!btnet-peer!btnet!dispose.news.demon.net!demon!peer.news.zetnet.net!zetnet.co.uk!not-for-mail On 1998-10-05 spam@orion-com.com(JoeThompson) said: :OK, my mistake. The point being: running CISC instructions on a :RISC chip via hardware emulation is not that far-fetched at all. :Anything that can be done in software can also be done in hardware. Not far fetched? It's the way most contemporary x86 clones work these days (including the PII in all its various, er, configurations). -- Communa (together) we remember... we'll see you falling you know soft spoken changes nothing to sing within her... ###### From: mww@microfocus.com (Michael Wojcik) Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: 6 Oct 1998 20:15:38 GMT Organization: Micro Focus Inc. Lines: 38 Message-ID: <6vdtpa$3qf@news3.newsguy.com> References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> NNTP-Posting-Host: p-280.newsdawg.com X-Newsreader: xrn 9.00 Originator: mww@raederle.microfocus.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.belnet.be!news-raspail.gip.net!news-peer.gip.net!news.gsl.net!gip.net!logbridge.uoregon.edu!pln-w!spln!extra.newsguy.com!newsp.newsguy.com!mww In article , Neil Franklin writes: > spam@orion-com.com (Joe Thompson) writes: > > > > OK, my mistake. The point being: running CISC instructions on a RISC chip > > via hardware emulation is not that far-fetched at all. Anything that can > > be done in software can also be done in hardware. -- Joe > > Just the small problem that doing it in hardware violates the entire > RISC design philosophy (make the basic stuff fast in hardware, do the > rest in software. Except that there isn't any "entire RISC design philosophy". The PPC has three or four hundred operations, some of which are hardly "basic" (like "load string word indexed", which loads 1-32 bytes into the register file, and "floating point negate multiply subtract double-precision", which does just what it says). Yet many people consider it a RISC processor. Phil Hester, for one, and he has a certain amount of authority in this arena. In "RISC System/6000 Hardware Background and Philosophies" (_IBM RISC System/6000 Technology_, IBM 1990, 2-7), Phil explicitly redefines "RISC" as "reduced instruction set cycles", defined as "the optimal value of path length times cycles per second". Others disagree. Michael Wojcik mww@microfocus.com AAI Development, Micro Focus Inc. Department of English, Miami University The lark is exclusively a Soviet bird. The lark does not like the other countries, and lets its harmonious song be heard only over the fields made fertile by the collective labor of the citizens of the happy land of the Soviets. -- D. Bleiman ###### Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> <6vdpi9$2gk@news3.newsguy.com> Date: 06 Oct 1998 21:13:49 -0700 Message-ID: Organization: Brouhaha Computer Mercenary Services Lines: 14 X-Newsreader: Gnus v5.5/Emacs 20.2 NNTP-Posting-Host: ruckus.brouhaha.com X-Trace: 6 Oct 1998 21:18:55 -0800, ruckus.brouhaha.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!logbridge.uoregon.edu!enews.sgi.com!news.sgi.com!news.spies.com!ruckus.brouhaha.com mww@microfocus.com (Michael Wojcik) writes: > Of course, the 615 was supposed to expose both the x86 instruction > set and the PPC (much like the memory-access-endianness bit in the > MSR), selected as part of a context switch, whereas AFAIK the NexGen > did not permit nx586-RISC binaries. Actually, Nexgen said that there was a way to run their RISC-ops directly from memory. However, they never chose to publish the necessary docs to allow third parties to do so. Since the processor was optimized for high performance running x86 code, I might hypothesize that the performance runing RICS-ops directly from memory may not have been too good, due to the much higher memory bandwidth needed to achieve the same results as an equivalent x86 instruction stream. ###### Path: chonsp.franklin.ch!usenet From: Neil Franklin Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: 07 Oct 1998 00:22:34 +0200 Organization: My own Private Self Lines: 59 Message-ID: References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> <$spam$-0510982128300001@user-37kba8a.dialup.mindspring.com> X-Newsreader: Gnus v5.3/Emacs 19.34 $spam$@orion-com.com (Joe Thompson) writes: > > wrote: > > > Just the small problem that doing it in hardware violates the entire > > RISC design philosophy (make the basic stuff fast in hardware, do the > > rest in software. > > It should be faster in hardware. You could have a "mode switch" that > flips you from RISC to CISC, or the other way. I'm not saying it's > necessarily the *best* idea, or even a *good* idea -- just that it can be > done. That is exactly CISC thinking. The whole idea in RISC ist that implementing "one additional feature" (repeatedly for many features in actual CISC designs) in hardware will speed up that one (or few) feature(s), but at the same time slow down all other features (by more complicated circuits having more delay or by reducing cache sizes). Resulting in an overall slower performance of the entire system. THe RISC ideology solves this by implementing an fundamental set of often used features at high speed and then implementing the rest in software which will still be faster because some of the time gained on the often used features can be sacrificed in the slower seldom used ones (which aren't that slow either because their software gets fastly executed). Weighing off what should be in the "small and often" set is the crucial thing in designing RISC instruction sets. Full PPC code runs explosively fast on an G3 333 (office neighbor has one). Leaves my R4600 (SGI Indy) in the dust. An 68k or x86 emulator would be fairly special purpose (only for emulating) and large (AFAIK 20..30% of an 568/686 class CPU), so it is done in software on RISC machines. As the important OS routines are ported to PPC in the Mac OS, it runs faster than on an real 68k. And there exist x86/PC/DOS/Windows emulators for PPC Macs which run on an G3 about at P133 speed with _all_ the code in x86. An Windows with the crucial parts in PPC code would most likely outrun an PII. Of course the 586/686 CPUs have running x86 software as their only purpose, so adding such an hardware CISC->RISC translarot makes sense there. Intel P+/PII, AMD K6, Cyrix 6x86 are all RISCs with such hardware translators - faster than RISC+software for pure x86 code. ut with an RISC/x86 mix they would be faster without the translator. Using an Alpha with native OS and FX/32 simulating x86 for applications shows the potential. I suspect that the Merced will also solve this problem this way - 5 years after PPC. -- *** New home Addresses Mail and Web *** home: neil@franklin.ch.remove http://neil.franklin.ch/ work: franklin@arch.ethz.ch.remove http://caad.arch.ethz.ch/~franklin/ Microsoft is Software Communism, Fight for GNU Freedom! ###### Path: chonsp.franklin.ch!usenet From: Neil Franklin Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: 07 Oct 1998 00:31:52 +0200 Organization: My own Private Self Lines: 48 Message-ID: References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> <6vdtpa$3qf@news3.newsguy.com> X-Newsreader: Gnus v5.3/Emacs 19.34 mww@microfocus.com (Michael Wojcik) writes: > > In article , Neil Franklin writes: > > > > Just the small problem that doing it in hardware violates the entire > > RISC design philosophy (make the basic stuff fast in hardware, do the > > rest in software. > > Except that there isn't any "entire RISC design philosophy". The PPC > has three or four hundred operations, some of which are hardly > "basic" (like "load string word indexed", which loads 1-32 bytes into > the register file, and "floating point negate multiply subtract > double-precision", which does just what it says). Yet many people > consider it a RISC processor. Phil Hester, for one, and he has a > certain amount of authority in this arena. > > In "RISC System/6000 Hardware Background and Philosophies" (_IBM RISC > System/6000 Technology_, IBM 1990, 2-7), Phil explicitly redefines > "RISC" as "reduced instruction set cycles", defined as "the optimal > value of path length times cycles per second". As I said in my follow up to Joe: : Weighing off what should be in the "small and often" set is the crucial : thing in designing RISC instruction sets. In the case of the PPC the "small and often" is actually quite large. Mainly due to its aim at commercial processing (it was invented by IBM), where the "cut off" line for "still an advantage" is higher than for engineering/scientific calculations that the Mips and Sparc were optimised for. It is the old 7040 vs 1130 (or 360/xx vs 360/yy) issue. At long last an folklore discussion after all the advocacy flaming!!! > Others disagree. I don't. It is horses for courses. You need to be fast on _your_ job. I run xterm/Emacs/Netscape im my Mips, my neighbor runs Office/Filemaker on his PPC. -- *** New home Addresses Mail and Web *** home: neil@franklin.ch.remove http://neil.franklin.ch/ work: franklin@arch.ethz.ch.remove http://caad.arch.ethz.ch/~franklin/ Microsoft is Software Communism, Fight for GNU Freedom! ###### From: David Wragg Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Organization: French Toast! Lines: 30 Message-ID: References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> <6vdpi9$2gk@news3.newsguy.com> Mime-Version: 1.0 (generated by tm-edit 7.108) Content-Type: text/plain; charset=US-ASCII X-Newsreader: Gnus v5.5/XEmacs 20.4 - "Emerald" Date: 07 Oct 1998 14:30:53 +0000 NNTP-Posting-Host: 194.119.176.228 X-Complaints-To: news@u-net.net X-Trace: newsr2.u-net.net 907802086 194.119.176.228 (Thu, 08 Oct 1998 00:14:46 BST) NNTP-Posting-Date: Thu, 08 Oct 1998 00:14:46 BST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!ayres.ftech.net!news.ftech.net!peer.news.zetnet.net!peer.news.bb.u-net.net!u-net!newsr2.u-net.net.POSTED!gatsby.u-net.com!not-for-mail mww@microfocus.com (Michael Wojcik) writes: > The PPC 615 never made it out the door (anyone at IBM / Motorola / > Sommerset know if they ever had a working prototype, even?), I read an article recently (probably in www.theregister.co.uk, which had a couple of 615 related articles recently) saying that the 615 actually made it to prototype silicon. > but IIRC, > according to _Byte_, the NexGen nx586 architecture used a RISC core > with a decoding unit that converted x86 instructions into a variable > number (1-7, I think) of "real" nx586 operations. Isn't this still > used by AMD in its 586-class CPUs? Intel could claim exactly the same about the P6 core. > Of course, the 615 was supposed to expose both the x86 instruction > set and the PPC (much like the memory-access-endianness bit in the > MSR), selected as part of a context switch, whereas AFAIK the NexGen > did not permit nx586-RISC binaries. The same story I mentioned above said that the motive behind the 615 was that someone within IBM believed that Intel's P6 would have a RISC instruction set, and it was a partly response to that. Of course, we all now know that it is in fact the P7, jointly developed with HP, which will have two instruction sets, to be released in 97^H^H98^H^H99^H^Hmid 2000. Dave Wragg ###### From: jsavard@tenMAPSONeerf.edmonton.ab.ca (John Savard) Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: Thu, 08 Oct 1998 21:49:38 GMT Organization: Videotron Communications Ltd. Lines: 18 Message-ID: <361d3294.1801992@news.prosurfr.com> References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> NNTP-Posting-Host: c9169-002.prosurfr.com X-Newsreader: Forte Free Agent 1.11/32.235 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.belnet.be!news-raspail.gip.net!news-peer.gip.net!news.gsl.net!gip.net!newsfeed.direct.ca!news.insinc.net!stimpy.cal.sfl.net!news.videotron.ab.ca!not-for-mail Neil Franklin wrote, in part: >Just the small problem that doing it in hardware violates the entire >RISC design philosophy (make the basic stuff fast in hardware, do the >rest in software. Well, one can design a chip so that the complexity of an instruction set is confined to a small section that decodes opcodes, and everything else resembles a RISC chip. Or one can design a chip that normally runs as a RISC chip, but can handle one CISC instruction set - or several - with hardware assistance, when desired. Because doing anything in software involves fetching from memory, which is slow, it does make sense to use what one can from RISC, but not to try for purity at the expense of performance. John Savard http://members.xoom.com/quadibloc/index.html ###### Path: chonsp.franklin.ch!usenet From: Neil Franklin Newsgroups: alt.folklore.computers Subject: Re: Transmeta's Little Secret Date: 09 Oct 1998 23:15:52 +0200 Organization: My own Private Self Lines: 47 Message-ID: References: <87g1dc92pd.fsf@dogbert.io.nu> <6utukb$3an$1@nnrp1.dejanews.com> <361d3294.1801992@news.prosurfr.com> X-Newsreader: Gnus v5.3/Emacs 19.34 jsavard@tenMAPSONeerf.edmonton.ab.ca (John Savard) writes: > > Neil Franklin wrote, in part: > > >Just the small problem that doing it in hardware violates the entire > >RISC design philosophy (make the basic stuff fast in hardware, do the > >rest in software. > > Well, one can design a chip so that the complexity of an instruction > set is confined to a small section that decodes opcodes, and > everything else resembles a RISC chip. Or one can design a chip that > normally runs as a RISC chip, but can handle one CISC instruction set > - or several - with hardware assistance, when desired. But even this has an problem. The (possibly seldom used) CISC part uses up chip space that could else be used to speed up other often used instructions (multiplication, virtual memory) or even the entire operation (such as an large cache, less misses). This impact must be compared with the gain the CISC part brings and how often it happens. > Because doing anything in software involves fetching from memory, > which is slow, it does make sense to use what one can from RISC, but > not to try for purity at the expense of performance. Which is why an larger cache may be an better use of chip space. Balancing how much of a chip is devoted to what functional units is an difficult tradeoff. IBM (the inventor of RISC, the 801 processor) decided on RISC after analysing lots of real production code and then extensively simulating alternative approaches to executing it. FOr an more modern case, compare Inten/AMD (strond FPU) with Cyrix (strong integer) 486/586/686 processors. Cyrix is fast in Unix or Office stuff, but it sinks on CAD or 3D games. Writing this on an Cyrix 486. Linux is fast, Quake is slow. -- *** New home Addresses Mail and Web *** home: neil@franklin.ch.remove http://neil.franklin.ch/ work: franklin@arch.ethz.ch.remove http://caad.arch.ethz.ch/~franklin/ Microsoft is Software Communism, Fight for GNU Freedom!