Mail-from: From neil Sat Sep 6 23:28:57 2003 Return-Path: Received: from localhost by localhost with POP3 (fetchmail-5.1.2) for neil@localhost (single-drop); Sat, 06 Sep 2003 23:28:57 +0200 (MEST) Received: from moria.seul.org (MORIA.MIT.EDU [18.244.0.188]) by island.ethz.ch (8.12.9/8.12.9) with ESMTP id h86LOIKY048274 for ; Sat, 6 Sep 2003 23:24:19 +0200 (MDT) Received: by moria.seul.org (Postfix, from userid 648) id F20C533B7F; Sat, 6 Sep 2003 17:24:17 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by moria.seul.org (Postfix) with ESMTP id F07DCFA984 for ; Sat, 6 Sep 2003 17:24:17 -0400 (EDT) Date: Sat, 6 Sep 2003 17:24:17 -0400 (EDT) From: Graham Seaman X-X-Sender: graham@moria.mit.edu To: neil@franklin.ch Subject: [oc] Free Place & Route (fwd) Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Spam-Status: No, hits=-5.7 required=5.0 tests=CASHCASHCASH,USER_AGENT_PINE autolearn=ham version=2.50 X-Spam-Level: X-Spam-Checker-Version: SpamAssassin 2.50 (1.173-2003-02-20-exp) Hi Neil, I don't know if you're subscribed to the opencores list but if not thought you might be interested in this thread which just started; it's also archived on http://www.opencores.org/forums/cores/2003/09/ Also, for some time I've been wondering whether I should add your virtextools to the lists on opencollector.org; given the sensitivity of xilinx to their bitstream info being generally available, do you prefer more publicity for what you're doing or would you rather just carry on (relatively) quietly? Regards Graham Seaman (http://opencollector.org) ---------- Forwarded message ---------- Date: 07 Sep 2003 00:21:57 +0700 From: Rudolf Usselmann Reply-To: cores@opencores.org To: cores@opencores.org Subject: [oc] Free Place & Route I don't know about you guys, but I always find it to be a pain in the neck using Xilinx or Altera back-end tools. I usually use a 3rd party Synthesis tool, but have no choice but to fight vendor proprietary tools for the back-end. So I would like to start a new project: The development of a FREE parameterizable Place & Route tool, that could be used with any FPGA architecture out there. Further, this tool MUST run under linux, other OS's optional. Now I am not a software guy so I can not write this, nor manage this project. But I am willing to put some cashe in to the project in terms of funding. What I have in mind is to hire a professional software team that can develop this project in a professional and timely manner. Of course the result of this project will be placed under GPL. However, I don't think I can finance a project of this magnitude on my own. Quite honestly I don't even have the slightest idea how much such a development would cost. So, I would like to start by specifying/outlining the features of such a tool, and then submit it for bidding to various software development companies for a quote. Once we have a quote I will try to raise money by begging all you good guys for donations ! So what do you guys think of this so far ? Am I going crazy in my old days or will we all benefit from such a tool ? Do we have a chance to compete with the proprietary tools from the vendors ? Will they hate or love us ? I am thinking only to include support for Xilinx and Altera in the initial tool. This should capture well over 80% of the market. Since this will be all open source other FPGA vendors can add code to support their FPGA architectures as they wish. Would you guys be willing to donate some $$$ to such a project if you are guaranteed that it will come through ? First Round of Specifications ----------------------------- - Accept a FPGA architecture description file - Accept EDIF netlist - No Synthesis Included - Accept a user constrain file - Do automatic place & route - Graphical Floorplaner/Editor - "bit-file" generator - support for various down-load cables/options Comments, Suggestions ? Best Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA Tools -- To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml ###### Mail-from: From neil@franklin.ch Sun Sep 7 00:44:27 2003 Return-Path: Received: (from neil@localhost) by franklin.ch (8.9.3/19991231-neil@franklin.ch) id AAA02323; Sun, 7 Sep 2003 00:44:27 +0200 Date: Sun, 7 Sep 2003 00:44:27 +0200 Message-Id: <200309062244.AAA02323@franklin.ch> From: Neil Franklin To: graham@seul.org In-reply-to: (message from Graham Seaman on Sat, 6 Sep 2003 17:24:17 -0400 (EDT)) Subject: Re: [oc] Free Place & Route (fwd) Cc: Rudolf Usselmann References: Graham Seaman wrote: > > I don't know if you're subscribed to the opencores list No, I am not. VHDL/Verilog code is outside of my interests, as I am an old style 74((L)S)(x)xx TTL style thinker, so I am not on their list. Thanks for the pointer. > you might be interested in this thread which just started; it's also > archived on > http://www.opencores.org/forums/cores/2003/09/ Interesting, also the followups. Hmmm, JBits 3.0 for Virtex-II is out? Now why did I never recieve notification (I am using JBits 2.8 (Virtex), and Xilinx knows that)? OTOH I am not on the official JBits Yahoogroups list, not enough low level stuff there to interest me. > Also, for some time I've been wondering whether I should add your > virtextools to the lists on opencollector.org; given the sensitivity of > xilinx to their bitstream info being generally available, do you prefer > more publicity for what you're doing or would you rather just carry on > (relatively) quietly? Xilinx definitely knows about the project. I have mentioned it a few time on c.a.f, where multiple Xilinx people read/post. In the words of Peter Alfke (of Xilinx), paraphrased: they do not like it, but they can and will not do anything to stop it (but also will not do anything to support it in any way either). So it is no secret, you can mention it. > ---------- Forwarded message ---------- > From: Rudolf Usselmann > Reply-To: cores@opencores.org Does not seem to have an reply mechanism on the Web archive. So I am normally replying this and Cc:-ing to Rudolf Usselmann. Perhaps you could forward this to the list? > I don't know about you guys, but I always find it to > be a pain in the neck using Xilinx or Altera back-end > tools. I usually use a 3rd party Synthesis tool, but > have no choice but to fight vendor proprietary tools > for the back-end. Now where do I know that from :-). > So I would like to start a new project: The development > of a FREE parameterizable Place & Route tool, Not to forget mapping and bitgen. (Map+Place) + Route + Bitgen is roughly the codegen + link + assemble phases of an software compiler. Both of above assume already intermediate code (compiled from HLL source, or synthesis), which is what the EDIF level about is. > that could > be used with any FPGA architecture out there. Further, > this tool MUST run under linux, other OS's optional. I am targetting any open OS, Linux or BSD. > Now I am not a software guy so I can not write this, nor My advantage of being trained BSc EE and professional programmer. > manage this project. But I am willing to put some cashe > in to the project in terms of funding. What I have in mind > is to hire a professional software team that can develop > this project in a professional and timely manner. Hmmm. Has that ever been done successfully? I remember the original Debian project worked like that and got nowhere. Extending a project (adding mising features) works that way, but from scratch design? > Of course > the result of this project will be placed under GPL. Preferrably PD (public domain) for my taste. Or if you need copyright (for what? making money? control freak?) then dual license GPL and modified BSD. > However, I don't think I can finance a project of this > magnitude on my own. Quite honestly I don't even have the > slightest idea how much such a development would cost. If my present VT (VirtexTools) work is anything to go by, I am at about 4 months of avg 5h/day productive worktime. I expect to end at around 2 (man)years. That is just for "assembler" level tools. I expect any HLL->asm stuff to come from other projects (so more time, no estimate how much, for M+P+R). > So, I would like to start by specifying/outlining the > features of such a tool, You may want to looks at the VT docs[1] for my outline for the low level stuff. [1] http://neil.franklin.ch/Projects/VirtexTools/README > and then submit it for bidding > to various software development companies for a quote. > Once we have a quote I will try to raise money by begging > all you good guys for donations ! Hmmm. The Blender "rescue" operation managed to get the asked $100'000 in about 2-3 months, IIRC. That was for an program with much larger user population, and with many users already using the program and not wanting to lose their investment in training and files. > So what do you guys think of this so far ? Am I going > crazy in my old days or will we all benefit from such > a tool ? Benefit surely. But I doubt the time/cost (3-4 man years?) vs user/payment (way under $100'000) is going to work out. > Do we have a chance to compete with the > proprietary tools from the vendors ? Only if we clearly focus on "what can we realistically deliver". Do the things good that they can not do. Then we are an alternative, with pros (open source, freely distributable, compile on any architecture/OS, will not cease to work or even be retracted, no license keys, no size restrictions) and cons (small, less comfort, less models supported, playing catch up, no helpdesk). For me that was the main thing deciding for an "assembler" lever toolset. I simply am not up to complicated compiler algorithms. Nor do I comprehend either VHDL or Verilog. > Will they hate or > love us ? More likely laugh about us. If my experiences[2] on the c.a.f newsgroup are anything to go by, most people there (vendors and users) do not comprehend what makes open source stuff interesting to its users. They have got used to an broken world for too long a time. [2] http://neil.franklin.ch/Projects/VirtexTools/#usenet > I am thinking only to include support for Xilinx and > Altera in the initial tool. I am focussing on one single architecture, for which I have at least some docu (XAPP138 + XAPP151 + JBits 2.8). The Virtex(-E)/Spartan-II(E) series. Older will vanish too quickly form the market. Newer the XAPPs are lacking and JBits may also be, given what the newer features direction in JBits 2.x look like. Altera I have never seen anything comparable in docs (but not really looked either). > This should capture well > over 80% of the market. Above will fit what I want to do with it, clone historical computers and perhaps one day escape from the "industry standard" crap PCs. > Since this will be all open > source other FPGA vendors can add code to support > their FPGA architectures as they wish. Only after they see large amounts of customers wandering off. That seems unlikely to happen for a long time. At present their minds seem to be 100% poisoned with the "got to make money from secret knowledge (a.k.a. intellectual property)" virus. > Would you guys be willing to donate some $$$ to such a > project if you are guaranteed that it will come through ? My donation is working part time (salary loss), so I have more time for hobbys (far too many of them), including making VT. > - Accept EDIF netlist I am starting with assembler like level, my own "vas" source or lower down Xilinxes machine code level XDL. Possibly _way_ into the future something graphical like FPGA Editor. > - Accept a user constrain file > - Do automatic place & route That is above my level. > - Graphical Floorplaner/Editor At what level? EDIF or XDL? EDIT level requires hinting to the mapper/placer. XDL level requires understanding M+P output and redoing on each compile. > - "bit-file" generator That is my centerpiece. Should be usable by others higher up tools. Is intended as foundation (in house building sense of the word). > - support for various down-load cables/options Should be in also, as required for an graphical display/debugger of an running FPGA. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith - hardware runs the world, software controls the hardware code generates the software, have you coded today? ###### Mail-from: From neil Sun Sep 7 13:36:28 2003 Return-Path: Received: from localhost by localhost with POP3 (fetchmail-5.1.2) for neil@localhost (single-drop); Sun, 07 Sep 2003 13:36:28 +0200 (MEST) Received: from lithium.websiteproviders.net ([209.50.251.171]) by island.ethz.ch (8.12.9/8.12.9) with ESMTP id h874U6nl059499 for ; Sun, 7 Sep 2003 06:30:11 +0200 (MDT) Received: from [203.154.159.253] (helo=[10.30.1.42]) by lithium.websiteproviders.net with esmtp (Exim 4.20) id 19vr9J-000Ap1-Me; Sun, 07 Sep 2003 00:27:43 -0400 Subject: Re: [oc] Free Place & Route (fwd) From: Rudolf Usselmann Reply-To: rudi@asics.ws To: Neil Franklin Cc: graham@seul.org In-Reply-To: <200309062244.AAA02323@franklin.ch> References: <200309062244.AAA02323@franklin.ch> Content-Type: text/plain Organization: ASICS.ws - Solutions for your ASICS & FPGA needs - Message-Id: <1062908995.1560.85.camel@linux8k> Mime-Version: 1.0 X-Mailer: Ximian Evolution 1.2.2 (1.2.2-4) Date: 07 Sep 2003 11:29:55 +0700 Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - lithium.websiteproviders.net X-AntiAbuse: Original Domain - franklin.ch X-AntiAbuse: Originator/Caller UID/GID - [0 0] / [26 6] X-AntiAbuse: Sender Address Domain - asics.ws X-Spam-Status: No, hits=-28.5 required=5.0 tests=CASHCASHCASH,EMAIL_ATTRIBUTION,IN_REP_TO,QUOTED_EMAIL_TEXT, QUOTE_TWICE_1,RCVD_IN_OPM,REFERENCES,REPLY_WITH_QUOTES, USER_AGENT_XIMIAN autolearn=ham version=2.50 X-Spam-Level: X-Spam-Checker-Version: SpamAssassin 2.50 (1.173-2003-02-20-exp) Hi Graham ! Hi Neil ! On Sun, 2003-09-07 at 05:44, Neil Franklin wrote: > Graham Seaman wrote: > > ... > > > Also, for some time I've been wondering whether I should add your > > virtextools to the lists on opencollector.org; given the sensitivity of I think you really should ! Also to the gEDA page ! ... > In the words of Peter Alfke (of Xilinx), paraphrased: they do not like > it, but they can and will not do anything to stop it (but also will > not do anything to support it in any way either). I wonder why that is. They should be happy ?! > > So it is no secret, you can mention it. > > > > ---------- Forwarded message ---------- > > From: Rudolf Usselmann > > Reply-To: cores@opencores.org > > Does not seem to have an reply mechanism on the Web archive. So I am > normally replying this and Cc:-ing to Rudolf Usselmann. Perhaps you > could forward this to the list? If you like to post to the list just send an email to cores@opencores.org and it should go to the list. > > I don't know about you guys, but I always find it to > > be a pain in the neck using Xilinx or Altera back-end > > tools. I usually use a 3rd party Synthesis tool, but > > have no choice but to fight vendor proprietary tools > > for the back-end. > > Now where do I know that from :-). > > > So I would like to start a new project: The development > > of a FREE parameterizable Place & Route tool, > > Not to forget mapping and bitgen. (Map+Place) + Route + Bitgen > is roughly the codegen + link + assemble phases of an software > compiler. > > Both of above assume already intermediate code (compiled from HLL > source, or synthesis), which is what the EDIF level about is. > > > > that could > > be used with any FPGA architecture out there. Further, > > this tool MUST run under linux, other OS's optional. > > I am targetting any open OS, Linux or BSD. > > > > Now I am not a software guy so I can not write this, nor > > My advantage of being trained BSc EE and professional programmer. > > > > manage this project. But I am willing to put some cashe > > in to the project in terms of funding. What I have in mind > > is to hire a professional software team that can develop > > this project in a professional and timely manner. > > Hmmm. Has that ever been done successfully? I remember the original > Debian project worked like that and got nowhere. Extending a project > (adding mising features) works that way, but from scratch design? > > > > Of course > > the result of this project will be placed under GPL. > > Preferrably PD (public domain) for my taste. Or if you need copyright > (for what? making money? control freak?) then dual license GPL and > modified BSD. > > > > However, I don't think I can finance a project of this > > magnitude on my own. Quite honestly I don't even have the > > slightest idea how much such a development would cost. > > If my present VT (VirtexTools) work is anything to go by, I am at > about 4 months of avg 5h/day productive worktime. I expect to end at > around 2 (man)years. That is just for "assembler" level tools. I > expect any HLL->asm stuff to come from other projects (so more time, > no estimate how much, for M+P+R). > > > > So, I would like to start by specifying/outlining the > > features of such a tool, > > You may want to looks at the VT docs[1] for my outline for the low level > stuff. > > [1] http://neil.franklin.ch/Projects/VirtexTools/README > > > > and then submit it for bidding > > to various software development companies for a quote. > > Once we have a quote I will try to raise money by begging > > all you good guys for donations ! > > Hmmm. The Blender "rescue" operation managed to get the asked $100'000 > in about 2-3 months, IIRC. That was for an program with much larger > user population, and with many users already using the program and not > wanting to lose their investment in training and files. > > > > So what do you guys think of this so far ? Am I going > > crazy in my old days or will we all benefit from such > > a tool ? > > Benefit surely. But I doubt the time/cost (3-4 man years?) vs > user/payment (way under $100'000) is going to work out. > > > > Do we have a chance to compete with the > > proprietary tools from the vendors ? > > Only if we clearly focus on "what can we realistically deliver". > Do the things good that they can not do. Then we are an alternative, > with pros (open source, freely distributable, compile on any > architecture/OS, will not cease to work or even be retracted, no > license keys, no size restrictions) and cons (small, less comfort, > less models supported, playing catch up, no helpdesk). > > For me that was the main thing deciding for an "assembler" lever > toolset. I simply am not up to complicated compiler algorithms. Nor > do I comprehend either VHDL or Verilog. > > > > Will they hate or > > love us ? > > More likely laugh about us. If my experiences[2] on the c.a.f newsgroup > are anything to go by, most people there (vendors and users) do not > comprehend what makes open source stuff interesting to its users. > They have got used to an broken world for too long a time. > > [2] http://neil.franklin.ch/Projects/VirtexTools/#usenet > > > > I am thinking only to include support for Xilinx and > > Altera in the initial tool. > > I am focussing on one single architecture, for which I have at least > some docu (XAPP138 + XAPP151 + JBits 2.8). The Virtex(-E)/Spartan-II(E) > series. Older will vanish too quickly form the market. Newer the XAPPs > are lacking and JBits may also be, given what the newer features > direction in JBits 2.x look like. Altera I have never seen anything > comparable in docs (but not really looked either). > > > > This should capture well > > over 80% of the market. > > Above will fit what I want to do with it, clone historical computers > and perhaps one day escape from the "industry standard" crap PCs. > > > > Since this will be all open > > source other FPGA vendors can add code to support > > their FPGA architectures as they wish. > > Only after they see large amounts of customers wandering off. That > seems unlikely to happen for a long time. > > At present their minds seem to be 100% poisoned with the "got to make > money from secret knowledge (a.k.a. intellectual property)" virus. > > > > Would you guys be willing to donate some $$$ to such a > > project if you are guaranteed that it will come through ? > > My donation is working part time (salary loss), so I have more time > for hobbys (far too many of them), including making VT. > > > > - Accept EDIF netlist > > I am starting with assembler like level, my own "vas" source or > lower down Xilinxes machine code level XDL. Possibly _way_ into > the future something graphical like FPGA Editor. It's just a suggestion. It must be a format that allows the tools to be used in an existing design flow. I might use Synplify (for example) to synthesize my design. This will generate verilog netlist or edif netlist. From there the P&R&Mapper must be able to take over ... > > - Accept a user constrain file > > - Do automatic place & route > > That is above my level. > > > > - Graphical Floorplaner/Editor > > At what level? EDIF or XDL? EDIT level requires hinting to the > mapper/placer. XDL level requires understanding M+P output and redoing > on each compile. Hmm, probably both, before and after Auto P&R. Before to allow for guiding of the P&R, may be on a higher abstract level, after to optimize cases where the auto P&R could not. > > - "bit-file" generator > > That is my centerpiece. Should be usable by others higher up tools. > Is intended as foundation (in house building sense of the word). > > > > - support for various down-load cables/options > > Should be in also, as required for an graphical display/debugger of > an running FPGA. So this looks like an excellent starting point. All we need is to throw lots of funding an man power at it and we should end up with an excellent tool ! Best Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA Tools ###### Mail-from: From neil@franklin.ch Sun Sep 7 14:14:48 2003 Return-Path: Received: (from neil@localhost) by franklin.ch (8.9.3/19991231-neil@franklin.ch) id OAA00321; Sun, 7 Sep 2003 14:14:48 +0200 Date: Sun, 7 Sep 2003 14:14:48 +0200 Message-Id: <200309071214.OAA00321@franklin.ch> From: Neil Franklin To: rudi@asics.ws CC: graham@seul.org In-reply-to: <1062908995.1560.85.camel@linux8k> (message from Rudolf Usselmann on 07 Sep 2003 11:29:55 +0700) Subject: Re: [oc] Free Place & Route (fwd) References: <200309062244.AAA02323@franklin.ch> <1062908995.1560.85.camel@linux8k> Rudolf Usselmann wrote: > > On Sun, 2003-09-07 at 05:44, Neil Franklin wrote: > > Graham Seaman wrote: > > ... > > In the words of Peter Alfke (of Xilinx), paraphrased: they do not like > > it, but they can and will not do anything to stop it (but also will > > not do anything to support it in any way either). > > I wonder why that is. They should be happy ?! Should, but aren't. Why this is so, is the question I have been asking my self for about 3 years. I have found/been offered multiple reasons, none really convincing. 1: The oldest speculation was, that bitstream secrecy makes it difficult/expensive to reverse engineer customer designs. Unlike PALs and CPLDs which are (EE)PROM based and have an "security" (readout disable) fuse, FPGAs are SRAM based and reloaded every time from external (EE)PROM, so the bitsream can be spied on. Since Virtex-II with its DES encryption this one is 100% moot. And as Virtex-II is not open, despite DES, it kills this argument. 2: Support costs. Xilinx claims if they document it, they will have to support people using the documents to make their own stuff. "it is difficult, we do not want to be dragged into support quagmire" or "clean up after them" is an offcial statement, in [1]. [1] http://neil.franklin.ch/Usenet/comp.arch.fpga/20011128_Is_there_a_full_open_source_synthesis_path_for_any_FPGA As the open source people tend to once write something and then all modifiy/extend (or fork) that, this does not seem convincing to me. But all vendors have shown an complete non-understanding of the open source community, so this may be what they really (miss-)believe. 3: It "hinders them in innovating", by forcing newer chips to stay binary compatible. The "" part is an statement on c.a.f by one of Xilinxes customers (and an absolute FPGA ace) in [2]. Of course this contradicts their stand, that customers allways want the best chip, and will buy it simply for more speed or size (with an 100% "got source" customer base this is likely for existing customers). [2] http://neil.franklin.ch/Usenet/comp.arch.fpga/20021008_Why_can_Xilinx_sw_be_as_good_as_Altera_s_sw IMHO an large enough group of "we want binary compatible" customers (most likely newly entering customers) to be noticed by the vendors, would simply split the FPGA market, one section like todays, no restrictions, and an second section like the i386 market. See the CPU i386 standard for "binary only" desktop PC market vs ARM/MIPS/PPC/etc for "got source" embedded market for comparison. As the vendor whose product seeds the "binary" market will be the strongest there (at no cost in other market), I would advise them to try and grab this market as before an other vendor does it. But they do not see this argument (yes, I have presented it on c.a.f). General tone: "FPGAs are not CPUs, our market is different". > > > ---------- Forwarded message ---------- > > > From: Rudolf Usselmann > > > Reply-To: cores@opencores.org > > > > Does not seem to have an reply mechanism on the Web archive. So I am > > normally replying this and Cc:-ing to Rudolf Usselmann. Perhaps you > > could forward this to the list? > > If you like to post to the list just send an email to > cores@opencores.org and it should go to the list. I do not like posting to mailing lists which I myself are not on. I prefer it to come from an person who is on the list. > > > - Accept EDIF netlist > > > > I am starting with assembler like level, my own "vas" source or > > lower down Xilinxes machine code level XDL. Possibly _way_ into > > the future something graphical like FPGA Editor. > > It's just a suggestion. It must be a format that allows the > tools to be used in an existing design flow. I might use > Synplify (for example) to synthesize my design. This will > generate verilog netlist or edif netlist. From there the > P&R&Mapper must be able to take over ... I suppose the best solution to this, is for me to offer something like "vas" or XDL, and then someone else, who understands compiler technology to make the "next up" stage EDIF->what I offer. Then an third "level" would be VHDL/Verilog/etc -> EDIF, giving 3 compile stages. Problem is, that mapping/placing is something beyond my abilities. I am very good at juggling bits, but not at complex abstract algorithms. So best I can do is offer an robust interface to my stuff, that others can build on. I agree that EDIF must be in the toolchain somewhere, because it is the industry standard. > > > - support for various down-load cables/options > > > > Should be in also, as required for an graphical display/debugger of > > an running FPGA. > > So this looks like an excellent starting point. All we > need is to throw lots of funding an man power at it and > we should end up with an excellent tool ! Particularly the manpower bit, and not to forget talented enough manpower. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith - hardware runs the world, software controls the hardware code generates the software, have you coded today?