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VirtexTools FPGA Programming and Debugging Tools Project

Project Basics
Project Status
Code Download
Auxillary documents
Usenet discussions
External Stuff (Links)

Project Basics

This project is aimed at creating open source and freeware toolset for programming and debugging of Xilinx Virtex family FPGAs. Initial targets are the original Virtex XCV00 and its bitstream compatible Spartan-II XC2S00 version. Later extension is possible/likely to Virtex-E XCV00E, Virtex-EM XCV00E and Spartan-IIE XC2S00E. There will be absolutely no support ever for XC4000/4000XL or their compatible Spartan/Spartan-XL (totally different architecture, outdated). Virtex-II and Virtex-IIpro (quite different) may one day in the far future find support, but that would be an sister project.

It is based on the information provided in the XAPP138 and XAPP151 application notes, that describe part of the bitstream format. Particularly they describe the file header and configuration frame formats, and the positions of the LUTs, FFs, BRAMs and IOB FFs. They also describe how to download configuration and read back chip status. In addition to that I will be using the JBits tools for "black box" reverse engineering of the configuration bitstream bit positions.

This project grow out of my PDP-10 Clone Microprocessor in FPGA project. Mainly from my frustration with the existing tool situation.

Intended tools are:

Intended usage of these tools (tool flow) is:

For more info on this project read the README file. For some questions people have asked or may ask read the FAQ list.

Addendum 2003.12.24: This project and PDP-10 canceled on 2003.12.24. After 1 month of forced break (HD crash, system rebuild) and 1.5 months since then of doing nothing on either this project or on PDP-10, I have come the the conclusion that I have lost all interest in both of them. Reasons are many:

Project Status

For the full details of done/doing/todo of the project best read the Logfile. A short excerpt from it is here:

Done are:

Milestone 1 (2002.09.22), aim for minimal usable functionality, read-in bitstream and test it using minimal command (vd). This was just preparatory for the 2nd milestone: Milestone 2 (2002.10.15), aim for my first intended use of this project, graphical renderings of FPGAs use for educational purposes (vv): Milestone 3, aim for completed read-in, and list/graphic output from it (this being just preparatory for the 4th milestone):

Doing is:

Addendum 2003.12.24: This project and PDP-10 canceled on 2003.12.24.

Todo are:

Milestone 3, aim for completed read-in, and list/graphic output from it (this being just preparatory for the 4th milestone): Milestone 4, aim for my second intended use of this project, loading programs into LUT-RAMs and BRAMs (vm) Milestone 5: Milestone 6: Milestone 7: Milestone 8:

Code Download

Current (= development, = may be broken): (now frozen by cancel, not broken): Milestone 2 (from 2002.10.15): Milestone 1 (from 2002.09.22): Example .bit file (XCV300) from my PDP-10 project, how it looks viewed by vv, and how it looks dumped by vd.

Auxillary documents

These are files I made while investigating various aspects of using FPGAs:

ASCII art of Virtex CLB PIPs
list of Virtex BRAM PIPs
estimated config bits sizes for some PALs and FPGAs

This is a lecture about hardware, self making, programmable logic and open source hardware, I held at the LUGcamp 2003 (in German): LUGcamp 2003 Vortrag Hardware

This is a file I made while searchig for still unused command line option:

options, what is being used, for what, and where

Usenet discussions

Various threads of comp.arch.fpga (subscribed 2000.09.23, unsubscribed 2003.12.23) that pertain to Virtex internals:

My comp.arch.fpga archive
Spartan II vs. Virtex [Spartan-II are bitstream compatible with Virtex, so can use JBits]
Re: virtex shape [Discussion of shape of Virtex chip and CLBs on it]
Amplify experience, was: FPGA Express strikes again! Xilinx response [The first "we want open tools" discussion I got into, mentioned NeoCAD reverse engineering Xilinx]
JBits [The thread I learned of this tool, the inspiration for VirtexTools]
Xilinx Configuration Bitstream [Discussion of bitstream problematic, got me started writing down ideas for VirtexTools project]
download bitstream to FPGA [Discussion of .bit file format, is more than just XAPP151]
Linux download bitstream [w/ source] [Tool source for Linux, how to access IO ports]
Is there a full open-source synthesis path for any FPGA? [Once againt he bitstream secrecy problem, my question if different for V2 (as that has got encryption) got ignored]
Why can Xilinx sw be as good as Altera's sw? [Grieving about vendors tools, turns to open source tools, and to patent effects on no compatible FPGA clones]
What's in a bitstream? [And once again bitstream secrecy]
FPGA implementation in (V)HDL [Looking for an open FPGA architecture for research, pointers to multiple of them, all SoG style, my critique of this style]
Regarding XC6216 [Looking for data sheet for the open XC6216, ends in Discussion how to get an open bitstream, I present idea of open source VHDL or EDIF SRAM-FPGA-in-ASIC or chip "laser printer"]

Not Usenet, but also the same problems being discussed:

Opencores.org Forum: Free Place & Route [Also discusses the lack of open source tools, closed bitstreams, this project gets referred to in an follow up]
Mail side discussion which sprang from above, in it I collect all the lame excuses from Xilinx

External Stuff (Links)

Various other peoples websites with usefull FPGA stuff:

Xilinx, obviously :-)
Xilinx JBits SDK
Xilinx Data Book
Virtex 2.5V FPGAs (XCV00)
Virtex-E 1.8V FPGAs (XCV00)
Virtex-E 1.8V Extended Memory FPGAs
Spartan-II Family FPGAs (XC2S00)
Spartan-IIE Family FPGAs (XC2S00E)
XAPP Application Notes
XAPP151, Virtex Series Configuration Architecture User Guide
FPGA Art Gallery, triggered the idea of doing VirtexView
Chip Shots Gallery, ideas for styling VirtexView output colouring
MPGA - Meta Programmable Gate Array (FPGA-in-FPGA design)
"Lab#5" contains an FPGA-in-FPGA design called SJSU Spartan S01
Opencores.org: Project: Embedded FPGA Core
Opencores.org: Project: CF Reconfigurable Computing Array

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This page is by Neil Franklin, last modification 2003.12.25