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; m32def.inc - memory sizes, IO register addresses and bit names for ATmega32
; author Neil Franklin, last modification 2008.10.12


; device name
.device ATmega32

; shipping fuses
; E1: 7:BODLVL=1, 6:BOD=1 (disable), 54:SUT=10, 3210:CKSEL=0001 (int RC@1Hz)
; 99: 7:OCDEN=1 (dis), 6:JTAGEN=0 (en), 5:SPIEN=0 (en), 4:CKOPT=1
;     3:EESAVE=1 (not preserve), 21:BOOTSZ=00, 0:BOOTRST=1 


; memory sizes and address ranges
; Flash
.equ MINROM = $0000 ; begin at 0
.equ MAXROM = $3FFF ; 0x3FFF/16k Word (= 32k Byte)
; Data (regs+IO+SRAM)
.equ MINREG = $0000 ; begin at 0
.equ MAXREG = $001F ; + 0x1F/32 Byte
.equ MINIO  = $0020 ; begin after regs
.equ MAXIO  = $005F ; + 0x3F/64 Byte
.equ MINRAM = $0060 ; begin after IO
.equ MAXRAM = $085F ; + 0x07FF/2k Byte
; EEPROM
.equ MINEE  = $0000 ; begin at 0
.equ MAXEE  = $03FF ; 1kByte


; interrupt vectors
; all vectors space for 2 instructions, for jmp instruction
.equ RESETaddr  = $0000 ; Reset Vector Address
.equ INT0addr   = $0002 ; External Interrupt 0 Vector Address
.equ INT1addr   = $0004 ; External Interrupt 1 Vector Address
.equ INT2addr   = $0006 ; External Interrupt 2 Vector Address
.equ T2CMPaddr  = $0008 ; Timer 2 Compare Match Interrupt Vector Address
.equ T2OVFaddr  = $000A ; Timer 2 Overflow Interrupt Vector Address
.equ T1CAPaddr  = $000C ; Timer 1 Capture Event Interrupt Vector Address
.equ T1CMPAaddr = $000E ; Timer 1 Compare Match A Interrupt Vector Address
.equ T1CMPBaddr = $0010 ; Timer 1 Compare Match B Interrupt Vector Address
.equ T1OVFaddr  = $0012 ; Timer 1 Overflow Interrupt Vector Address
.equ T0CMPaddr  = $0014 ; Timer 0 Compare Match Interrupt Vector Address
.equ T0OVFaddr  = $0016 ; Timer 0 Overflow Interrupt Vector Address
.equ SPIaddr    = $0018 ; SPI Transfer Complete Interrupt Vector Address
.equ URXCaddr   = $001A ; USART Rx Interrupt Vector Address
.equ UDREaddr   = $001C ; USART Data Register Empty Interrupt Vector Address
.equ UTXCaddr   = $001E ; USART Tx Interrupt Vector Address
.equ ADCaddr    = $0020 ; ADC Conversion Complete Interrupt Vector Address
.equ EERDYaddr  = $0022 ; EEPROM Ready Interrupt Vector Address
.equ ACMPaddr   = $0024 ; Analog Comparator Interrupt Vector Address
.equ TWIaddr    = $0026 ; TWI Interrupt Vector Address
.equ SPMaddr    = $0028 ; SPM Ready Interrupt Vector Address
; from here on normal usage, this is where .org starts
.equ MINCODE    = $002A ; begin of normal code


; IO registers, from register summary

; CPU
.equ SREG   = $3F ; status reg
.equ SPH    = $3E ; stack pointer H
.equ SPL    = $3D ; stack pointer L

; TIMER
.equ OCR0   = $3C ; output compare 0

; INT
.equ GICR   = $3B ; general interrupt control
  .equ INT1   = 7   ; ext int 1 enable
  .equ INT0   = 6   ; ext int 0 enable
  .equ INT2   = 5   ; ext int 2 enable
  ;             4   ; -
  ;             3   ; -
  ;             2   ; -
  .equ IVSEL  = 1   ; int vector select
  .equ IVCE   = 0   ; int vector change enable
.equ GIFR   = $3A ; general interrupt flag
  .equ INTF1  = 7   ; ext int 1 flag
  .equ INTF0  = 6   ; ext int 0 flag
  .equ INTF2  = 5   ; ext int 2 flag
  ;             4   ; -
  ;             3   ; -
  ;             2   ; -
  ;             1   ; -
  ;             0   ; -
.equ TIMSK  = $39 ; timer interrupt mask
  .equ OCIE2  = 7   ; Timer 2 output compare match enable
  .equ TOIE2  = 6   ; Timer 2 overflow enable
  .equ TICIE1 = 5   ; Timer 1 input capture enable
  .equ OCIE1A = 4   ; Timer 1 output compare match unit A enable
  .equ OCIE1B = 3   ; Timer 1 output compare match unit B enable
  .equ TOIE1  = 2   ; Timer 1 overflow enable
  .equ OCIE0  = 1   ; Timer 0 output compare match enable
  .equ TOIE0  = 0   ; Timer 0 overflow enable
.equ TIFR   = $38 ; timer interrupt flag
  .equ OCF2   = 7   ; Timer 2 output compare flag
  .equ TOV2   = 6   ; Timer 2 overflow flag
  .equ ICF1   = 5   ; Timer 1 input capture flag
  .equ OCF1A  = 4   ; Timer 1 output compare match unit A flag
  .equ OCF1B  = 3   ; Timer 1 output compare match unit B flag
  .equ TOV1   = 2   ; Timer 1 overflow flag
  .equ OCF0   = 1   ; Timer 0 output compare flag
  .equ TOV0   = 0   ; Timer 0 overflow flag

; CPU
.equ SPMCR  = $37 ; SPM control
  .equ SPMIE  = 7   ; interrupt enable
  .equ RWWSB  = 6   ; read-while-write section busy
  ;             5   ; -
  .equ RWWSRE = 4   ; read-while-write read enable
  .equ BLBSET = 3   ; boot lock bit set
  .equ PGWRT  = 2   ; page write
  .equ PGERS  = 1   ; page erase
  .equ SPMEM  = 0   ; enable

; TWI
.equ TWCR   = $36 ; TWI control
  .equ TWINT  = 7   ; interrupt flag
  .equ TWEA   = 6   ; enable acknowledge
  .equ TWSTA  = 5   ; start condition
  .equ TWSTO  = 4   ; stop condition
  .equ TWWC   = 3   ; write collision
  .equ TWEN   = 2   ; enable
  ;             1   ; -
  .equ TWIE   = 0   ; interrupt enable

; CPU
.equ MCUCR  = $35 ; MCU control
  .equ SE     = 7   ; sleep enable
  .equ SM2    = 6   ; sleep mode bit2
  .equ SM1    = 5   ; sleep mode bit1
  .equ SM0    = 4   ; sleep mode bit0
  .equ ISC11  = 3   ; int sense control 1 bit1
  .equ ISC10  = 2   ; int sense control 1 bit0
  .equ ISC01  = 1   ; int sense control 0 bit1
  .equ ISC00  = 0   ; int sense control 0 bit0
.equ MCUCSR = $34 ; MCU control and status
  .equ JTD    = 7   ; JTAG disable
  .equ ICS2   = 6   ; int sense control 2
  ;             5   ; -
  .equ JTRF   = 4   ; JTAG reset
  .equ WDRF   = 3   ; watchdog reset
  .equ BORF   = 2   ; brownout reset
  .equ EXTRF  = 1   ; externel reset
  .equ PORF   = 0   ; power on reset

; TIMER
.equ TCCR0  = $33 ; timer control 0
  .equ FOC0   = 7   ; force output compare
  .equ WGM00  = 6   ; waveform mode bit0
  .equ COM01  = 5   ; compare match output mode bit1
  .equ COM00  = 4   ; compare match output mode bit0
  .equ WGM01  = 3   ; waveform mode bit1
  .equ CS02   = 2   ; clock select bit 2
  .equ CS01   = 1   ; clock select bit 1
  .equ CS00   = 0   ; clock select bit 0
.equ TCNT0  = $32 ; timer count 0
.equ OSCCAL = $31 ; oscillator calibration
  .equ OCDR   = $31 ; JTAG debug register
.equ SFIOR  = $30 ; special function
  .equ ADTS2  = 7   ; ADC auto trigger source bit2
  .equ ADTS1  = 6   ; ADC auto trigger source bit1
  .equ ADTS0  = 5   ; ADC auto trigger source bit0
  ;             4   ; -
  .equ ACME   = 3   ; analog comp mux enable
  .equ PUD    = 2   ; pull up disable
  .equ PSR2   = 1   ; prescaler reset timer 2
  .equ PSR10  = 0   ; prescaler reset timer 0+1
.equ TCCR1A = $2F ; timer control 1 A
  .equ COM1A1 = 7   ; compare match output mode unit A bit1
  .equ COM1A0 = 6   ; compare match output mode unit A bit0
  .equ COM1B1 = 5   ; compare match output mode unit B bit1
  .equ COM1B0 = 4   ; compare match output mode unit B bit0
  .equ FOC1A  = 3   ; force output compare unit A
  .equ FOC1B  = 2   ; force output compare unit B
  .equ WGM11  = 1   ; waveform mode bit1
  .equ WGM10  = 0   ; waveform mode bit0
.equ TCCR1B = $2E ; timer control 1 B
  .equ ICNC1  = 7   ; input capture noise canceler
  .equ ICES1  = 6   ; input capture edge select
  ;             5   ; -
  .equ WGM13  = 4   ; waveform mode bit3
  .equ WGM12  = 3   ; waveform mode bit2
  .equ CS12   = 2   ; clock select bit 2
  .equ CS11   = 1   ; clock select bit 1
  .equ CS10   = 0   ; clock select bit 0
.equ TCNT1H = $2D ; timer count 1 H
.equ TCNT1L = $2C ; timer count 1 L
.equ OCR1AH = $2B ; output compare 1 unit A H
.equ OCR1AL = $2A ; output compare 1 unit A L
.equ OCR1BH = $29 ; output compare 1 unit B H
.equ OCR1BL = $28 ; output compare 1 unit B L
.equ ICR1H  = $27 ; input capture 1 H
.equ ICR1L  = $26 ; input capture 1 L
.equ TCCR2  = $25 ; timer control 2
  .equ FOC2   = 7   ; force output compare
  .equ WGM20  = 6   ; waveform mode bit0
  .equ COM21  = 5   ; compare match output mode bit1
  .equ COM20  = 4   ; compare match output mode bit0
  .equ WGM21  = 3   ; waveform mode bit1
  .equ CS22   = 2   ; clock select bit 2
  .equ CS21   = 1   ; clock select bit 1
  .equ CS20   = 0   ; clock select bit 0
.equ TCNT2  = $24 ; timer count 2
.equ OCR2   = $23 ; output compare 2
.equ ASSR   = $22 ; asynchronous operation
  ;             7   ; -
  ;             6   ; -
  ;             5   ; -
  ;             4   ; -
  .equ AS2    = 3   ; asynchronous timer 2
  .equ TCN2UN = 2   ; timer 2 update busy
  .equ OCR2UB = 1   ; output compare 2 update busy
  .equ TCR2SB = 0   ; timer 2 control reg update busy

; WDT
.equ WDTCR  = $21 ; watchdog timer control
  ;             7   ; -
  ;             6   ; -
  ;             5   ; -
  .equ WDTOE  = 4   ; turnoff enable
  .equ WDE    = 3   ; enable
  .equ WDP2   = 2   ; prescaler bit2
  .equ WDP1   = 1   ; prescaler bit1
  .equ WDP0   = 0   ; prescaler bit0

; USART
.equ UCSRC  = $20 ; USART control and status C
  .equ URSEL  = 7   ; register select
  .equ UMSEL  = 6   ; mode select
  .equ UPM1   = 5   ; parity mode bit1
  .equ UPM0   = 4   ; parity mode bit0
  .equ USBS   = 3   ; stop bit select
  .equ UCSZ1  = 2   ; character size bit1
  .equ UCSZ0  = 1   ; character size bit0
  .equ UCPOL  = 0   ; clock polarity
  .equ UBRRH  = $20 ; USART baudrate H

; EEPROM
.equ EEARH  = $1F ; EEPROM address H
.equ EEARL  = $1E ; EEPROM address L
.equ EEDR   = $1D ; EEPROM data
.equ EECR   = $1C ; EEPROM control
  ;             7   ; -
  ;             6   ; -
  ;             5   ; -
  ;             4   ; -
  .equ EERIE  = 3   ; ready interrupt enable
  .equ EEMWE  = 2   ; master write enable
  .equ EEWE   = 1   ; write enable
  .equ EERE   = 0   ; read enable

; PIO
.equ PORTA  = $1B ; port A data out
.equ DDRA   = $1A ; port A data direction
.equ PINA   = $19 ; port A read pins
  .equ PINA7  = 7
  .equ PINAD7 = PINA7
  .equ PINA6  = 6
  .equ PINAD6 = PINA6
  .equ PINA5  = 5
  .equ PINAD5 = PINA5
  .equ PINA4  = 4
  .equ PINAD4 = PINA4
  .equ PINA3  = 3
  .equ PINAD3 = PINA3
  .equ PINA2  = 2
  .equ PINAD2 = PINA2
  .equ PINA1  = 1
  .equ PINAD1 = PINA1
  .equ PINA0  = 0
  .equ PINAD0 = PINA0
.equ PORTB  = $18 ; port B data out
.equ DDRB   = $17 ; port B data direction
.equ PINB   = $16 ; port B read pins
  .equ PINB7  = 7
  .equ PINSCK = PINB7
  .equ PINB6  = 6
  .equ PINMISO = PINB6
  .equ PINB5  = 5
  .equ PINMOSI = PINB5
  .equ PINB4  = 4
  .equ PINSS  = PINB4
  .equ PINB3  = 3
  .equ PINAIN1 = PINB3
  .equ PINOC0 = PINB3
  .equ PINB2  = 2
  .equ PINAIN0 = PINB2
  .equ PININT2 = PINB2
  .equ PINB1  = 1
  .equ PINT1  = PINB1
  .equ PINB0  = 0
  .equ PINT0  = PINB0
  .equ PINXCK = PINB0
.equ PORTC  = $15 ; port C data out
.equ DDRC   = $14 ; port C data direction
.equ PINC   = $13 ; port C read pins
  .equ PINC7  = 7
  .equ PINTOSC1 = PINC7
  .equ PINC6  = 6
  .equ PINTOSC0 = PINC6
  .equ PINC5  = 5
  .equ PINTDI = PINC5
  .equ PINC4  = 4
  .equ PINTDO = PINC4
  .equ PINC3  = 3
  .equ PINTMS = PINC3
  .equ PINC2  = 2
  .equ PINTCK = PINC2
  .equ PINC1  = 1
  .equ PINSDA = PINC1
  .equ PINC0  = 0
  .equ PINSCL = PINC0
.equ PORTD  = $12 ; port D data out
.equ DDRD   = $11 ; port D data direction
.equ PIND   = $10 ; port D read pins
  .equ PIND7  = 7
  .equ PINOC2 = PIND7
  .equ PIND6  = 6
  .equ PINICP1 = PIND6
  .equ PIND5  = 5
  .equ PINOC1A = PIND5
  .equ PIND4  = 4
  .equ PINOC1B = PIND4
  .equ PIND3  = 3
  .equ PININT1 = PIND3
  .equ PIND2  = 2
  .equ PININT0 = PIND2
  .equ PIND1  = 1
  .equ PINTXD = PIND1
  .equ PIND0  = 0
  .equ PINRXD = PIND0

; SPI
.equ SPDR   = $0F ; SPI data
.equ SPSR   = $0E ; SPI status
  .equ SPIF   = 7   ; interrupt flag
  .equ WCOL   = 6   ; write collision
  ;             5   ; -
  ;             4   ; -
  ;             3   ; -
  ;             2   ; -
  ;             1   ; -
  .equ SPI2X  = 0   ; double speed
.equ SPCR   = $0D ; SPI control
  .equ SPIE   = 7   ; interrupt enable
  .equ SPE    = 6   ; enable
  .equ DORD   = 5   ; data order
  .equ MSTR   = 4   ; master/slave select
  .equ CPOL   = 3   ; clock polarity
  .equ CPHA   = 2   ; clock phase
  .equ SPR1   = 1   ; clock data rate bit1
  .equ SPR0   = 0   ; clock data rate bit0

; USART
.equ UDR    = $0C ; USART data
.equ UCSRA  = $0B ; USART control and status A
  .equ RXC    = 7   ; recieve complete
  .equ TXC    = 6   ; transmit complete
  .equ UDRE   = 5   ; data register empty
  .equ FE     = 4   ; frame error
  .equ DOR    = 3   ; data overrun
  .equ PE     = 2   ; parity error
  .equ U2X    = 1   ; double transmit speed
  .equ MPCM   = 0   ; multiprocessor mode
.equ UCSRB  = $0A ; USART control and status B
  .equ RXCIE  = 7   ; recieve complete int enable
  .equ TXCIE  = 6   ; transmit complete int enable
  .equ UDRIE  = 5   ; data register empty int enable
  .equ RXEN   = 4   ; reciever enable
  .equ TXEN   = 3   ; transciever enable
  .equ UCSZ2  = 2   ; character size bit2
  .equ RXB8   = 1   ; recieve data bit8
  .equ TCB8   = 0   ; transmit date bit8
.equ UBRRL  = $09 ; USART baudrate L

; ADC
.equ ACSR   = $08 ; analog comp control and status
  .equ ACD    = 7   ; disable
  .equ ACBG   = 6   ; bandgap select
  .equ ACO    = 5   ; output
  .equ ACI    = 4   ; interrupt flag
  .equ ACIE   = 3   ; interrupt enable
  .equ ACIC   = 2   ; input capture enable
  .equ ACIS1  = 1   ; interrupt mode bit1
  .equ ACIS0  = 0   ; interrupt mode bit0
.equ ADMUX  = $07 ; ADC mux selection
  .equ RERS1  = 7   ; reference sel bit1
  .equ RERS2  = 6   ; reference sel bit0
  .equ ADLAR  = 5   ; left adjust result
  .equ MUX4   = 4   ; channel and gain select bit4
  .equ MUX3   = 3   ; channel and gain select bit3
  .equ MUX2   = 2   ; channel and gain select bit2
  .equ MUX1   = 1   ; channel and gain select bit1
  .equ MUX0   = 0   ; channel and gain select bit0
.equ ADCSRA = $06 ; ADC control and status
  .equ ADEN   = 7   ; enable
  .equ ADSC   = 6   ; start conversion
  .equ ADATE  = 5   ; auto trigger enable
  .equ ADIF   = 4   ; interrupt flag
  .equ ADIE   = 3   ; interrupt enable
  .equ ADPS2  = 2   ; prescaler select bit2
  .equ ADPS1  = 1   ; prescaler select bit1
  .equ ADPS0  = 0   ; prescaler select bit0
.equ ADCH   = $05 ; ADC data H
.equ ADCL   = $04 ; ADC data L

; TWI
.equ TWDR   = $03 ; TWI data
.equ TWAR   = $02 ; TWI (slave) address
.equ TWSR   = $01 ; TWI status
  .equ TWS7   = 7   ; status
  .equ TWS6   = 6   ; status
  .equ TWS5   = 5   ; status
  .equ TWS4   = 4   ; status
  .equ TWS3   = 3   ; status
  ;             2   ; -
  .equ TWPS1  = 1   ; prescaler bit1
  .equ TWPS0  = 0   ; prescaler bit0
.equ TWBR   = $00 ; TWI bitrate

.list