http://neil.franklin.ch/Projects/SoftVGA/Logfile - things done and to do author Neil Franklin, last modification see last entry near bottom later 198?.??.?? ??? met first time emulators, Z80+CP/M on 8088 PC, 10% speed in apps, fast in OS later 8080+MSODS on 68000 Atari ST, roughly same speed characteristics later 198?.??.?? ??? read about PALs in magazines, MMI 16R8/20R8, AMD 22V10 plans to do an CPU in an PAL, but even MMI 64R32 was too small, too few FFs did not know bitslice technique in those days, nor idea of external registers was too taken in from the idea of a single chip CPU, microprocessor 1990.01.?? ??? saw first time Xilinx chips in magazines, looked like a great thing but could not afford the $5000 development tools as just ex-student 1991.09.?? ??? saw Algotronix CAL1024 PC/AT card, but had just got new non-PC (NeXT) computer so I went a different career in programming, Unix, sysadmining digital electronics, particularly processors, staid an hobby interest 1992.??.?? ??? to 1993.??.?? ??? on NeXT computer used the SoftPC 8088+MSDOS emulator wrote an C64 emulator, CPU full speed, but graphics far too slow http://neil.franklin.ch/Projects/Soft64/ the Project names SoftVGA and SoftCPU are straight descendants of this 1997.12.17 Wed thread on PDP-10s Daniel A. Seagraves muses on emulating an 10 http://neil.franklin.ch/Usenet/alt.folklore.computers/19971208_Curious_about_10s G. Herrmannsfeldt mentions a FPGA project that turns out to be an -8 1999.07.02 Fri Communa/Lisard mentions putting Forth into hardware, simple enough for FPGAs http://neil.franklin.ch/Usenet/alt.folklore.computers/19990630_CPU_s_directly_executing_HLL_s Paul Wallich mentiones Alto only 1600 gates, would go in an FPGA 1999.07.07 Wed Jan Gray carries on speculations of implementing Xerox Alto in an FPGA http://neil.franklin.ch/Usenet/alt.folklore.computers/19990707_Alto_in_an_FPGA 2000.08.19 Sat D G Conroy announces PDP-8/X implemented in an XCS10 FPGA http://neil.franklin.ch/Usenet/alt.sys.pdp8/20000819_something_for_everyone_s_amusement Actual website is http://surfin.spies.com/~dgc/pdp8x/ Ben Franchuk mentiones above project http://neil.franklin.ch/Usenet/alt.folklore.computers/20000819_Naked_computers discussion that Blinkenlights are really neccessary my interest in doing an CPU myself with programmable logic rewoke 2000.10.05 Thu Discussion about open source tools, no back ends, secret bitstreams http://neil.franklin.ch/Usenet/comp.arch.fpga/20001002_Amplify_experience vendor tools only for WindowsNT/Solaris, ev also for HP-UX/AIX must use Win tools under Wine http://www.polybus.com/xilinx_on_linux.html frustration with programmable logic (at least FPGAs and CPLDs) starts here 2002.06.03 Mon went looking at microcontrollers for FPGA loading Zilog Z80/Z180 I know the instruction set, but no microcontrollers with it only Zilog microcontroller is Z8 which is different instr set, and mask ROM Z280/eZ80 webserver has all peripherals, but only mask ROM no flash Intel 8051 totally primitive, no space for bitstreams, best is 8751 EPROM external flash can not be addressed directly, only via special instr and uses up the few IO pins real fast, no left for FPGA, RS232, Floppy, IDE Motorola 68HC11 website ist unusable, can not even find data sheets Atmel AVR is a real processor, megaAVR large Flash versions up to 128kByte is actually an Harvard architecture RISC with 64k*16bit program space 2002.06.11 Tue after Mail from Harry Reed re-checked eZ80, has no mask ROM, no ROM at all eZ80 Webserver Developer's Kit has 1M Flash, but that is a multi-chip system I really do want an single chip solution, or I will prefer to use an SEEPROM 2002.07.10 Wed PDP-10 planned post milestone 3 changes done, now ready for new features but first I want to improve documentation there, for that I need VirtexView also I want to start education colleagues on using FPGAs, that also needs vv so now I am going to work on VirtexTools for a bit, until enough is running this turned out to be the beginning of the end for the PDP-10 project 2002.07.14 Sun went looking for Linux tools for programming microcontrollers found assemblers (ava, avra) and download tools (avrprog, uisp) for AVR one C compiler and simulator (sdcc and sdcc-usim) for 8051/AVR/Z80 simulator (gpsim, sumulpic), assemb (gputils, picasm) download (picp) for PIC of above I have looked at 8051 and AVR, so also went and looked at PIC PIC16Cxx are too small, PIC18Cxx large enough, but seems messy like 8051 2003.06.10 Tue yet annother discussion about bitstream format, reverse engineering costs http://neil.franklin.ch/Usenet/comp.arch.fpga/20030610_What_s_in_a_bitstream put in that I had 40d*5h = 200h for VirtexTools Milestones 1+2 estimate 1000h to bitstream, = 200d = 1 manyear, he lost interest then yet more frustration at FPGA bitstream secrecy and vendors situation the chips may be great, but the vendors and their policys prevent decent use 2003.10.04 Sat main PC HD crash, needs complete rebuild of system, no data loss (backup) 2003.12.22 Mon after 1 month rebuild, then 1.5 months doing nothing, PDP-10 or VirtexTools noticed that reason is total loss/lack of interest in both projects both only wanted for the other, PDP-10 to test tools, tools to make PDP-10 2003.12.23 Tue decided to give up both projects, get them off my mind gave up on PDP-10 and VirtexTools projects, as both only used for each other because frustrated with FPGA situation, and lost interest in hardware PDP-10 http://neil.franklin.ch/Projects/PDP-10/ http://neil.franklin.ch/Projects/VirtexTools/ that was the end of any hardware building projects at that time 2003.12.24 Wed updated Logfiles and Websites to reflect both projects being canceled now lots of time free, for other stuff and projects 2004.??.?? ??? looked at various small electronic projects and programming languages search for what I want to do, where my interests lay 2004.11.?? ??? started making notes for designing an own small computer is sufficient if it has only original historic speed, not todays only needs to be usable as an experiment, not productive without chips that will disappear looked into 3 technology variants pure transistors - lots of work and large http://neil.franklin.ch/Projects/Sketches/Transistor_Logic_Computer PALs/GALs - best programmable hardware that is open and multivendor http://neil.franklin.ch/Projects/Sketches/TTL_and_PAL_GAL_Computer microcontroller - compactest hardware possible, single chip http://neil.franklin.ch/Projects/Sketches/Microcontroller_CPU_Emu 2004.01.20 Tue surfed B.Kainka website, lots of small few-component electronics discoveries http://www.b-kainka.de/bastel0.htm 2004.05.28 Fri looked at building arcade style game controllers http://www.arcadecontrols.com/arcade.htm 2004.06.21 Mon went surfing by the colorforth website http://www.colorforth.com/ surfed multiple other Forth sites, http://www.theforthsource.com/ http://www.complang.tuwien.ac.at/projects/forth.html http://www.zetetics.com/bj/papers/moving1.htm reawaked interest in low level stuff 2004.06.23 Wed at LinuxTag 2004 accidently had booth just next to Forth guys there PC controlled metal xylophone, simple TTL decoders and phone relays reminded me how simple electronics projects can be fun, control stuff and also that Assembly and Forth are interesting, would like to do again also competing interest in perl, python and Lisp 2004.06.29 Tue went surfing Assembly oriented site http://cs.smith.edu/~thiebaut/ArtOfAssembly/artofasm.html reawaked interest in assembler stuff 2004.07.12 Mon surfing simple TTL self build CPU sites http://www.homebrewcpu.com/ http://www.venturalink.net/~jamesc/ttl/ and surfing Forth sites http://www.figuk.plus.com/byof.htm found out about Rickard Gunees microcontroller based video game, Atari joystick http://www.rickard.gunee.com/projects/ 16C84 20pin PIC 12MHz/3MIPS based b&w, using 1bit shift operation derived from Eric Smith design for generating b&w video http://www.rickard.gunee.com/projects/video/pic/howto.php 28pin Ubicom 42.95/53.1MHz SX28 based colour using 5bit R-2R DA converter http://www.rickard.gunee.com/projects/video/sx/howto.php dislike the complicated QAM modulation stuff, perhaps better RGB monitor? cool concept, modern microcontrollers are fast enough to generate MHz signals sparked basic interest in doing an video generator 2004.08.25 Wed looked at Paul Graham Lisp site, work on ARC modernising, seems to be stalled 2004.10.18 Mo looked at perl 6 development, but not much interest 2004.10.21 Thu re-visited Linux Assembly site, http://linuxassembly.org/ 2004.11.11 Sat found xgamestation, above Gunee colour idea, but with SX52 overclocked to 80MHz and external SRAM because SX52 only has 4k Flash and 8+16*16bytes SRAM and for some odd reason hardware sound chip instead of software http://www.xgamestation.com/view_product.php?id=12 2004.11.20 Sat found Jaakko Hyvätti simplified above PIC b&w pong video game 12F675 8pin PIC 16MHz/4MIPS based b&w, with paddles instead of joystick http://hyvatti.iki.fi/~jaakko/pic/pong/ 2004.12.14 Tue went looking at Lisp macros, http://www.lisperati.com/ 2004.12.31 Fri went looking at x86 Assembly http://www.jegerlehner.ch/intel/, http://www.sandpile.org/ 2005.03.05 Thu as Chemnitz Linux Tage saw that Xbox guys are now opening up WLAN APs after Lisp speech experimented with it, decided it is not what I want too strange and incomplete to use as is, too complex to implement my own also around same time at work lost interest in perl, and not much in python gave up on finding an ideal highlevel language, all worse even than C so more go for Assembly or Forth based projects, go for low level stuff 2005.04.30-05.01 Sat-Sun VCFe 6.0 with theme of making own interfaces to old computers Atari 800 guys showing USB interface, other speech on using 8051s rewoke interest in doing some hardware, latent above small video computer next year will be theme of building kits and own computers general interest in getting people back into hardware hacking 2005.05.05-08 Thu-Sun LUG-Camp 3 projects soldering on stuff, AVR model car, MSP340 ergometer and Linux Xbox hackers doing Linux on WLAN routers, speech on it and reference to Linux on USB NSLU2 disk servers http://www.nslu2-linux.org/ both are just generic 200MHz MIPS or 266MHz ARM with Flash and SDRAM decided I really want to get back into hardware, after giving up PDP-10 software VGA from microcontroller project looks great, with game(s) on it remaining interest in Python fits with Blender use for LUGS movie project but later project terminated, so that interest has dropped, so time free 2005.05.16 Mon from www.6502.org landed at Robert Greene microcontroller based VGA generator PIC 18LF252 4MHz/4MIPS later 10MHz/10MIPS for 124 pixel at 2instr/pixel http://webpages.charter.net/greener/electronics/video1/ PIC 18LF4220 (only address generator and ext SRAM as line-per-pixel LUT at 1inst/pixel 10MHz/MIPS gives him 251 pixels per line SRAM reload makes display snowing, as no tristate or blanker http://webpages.charter.net/greener/electronics/video2/ 2005.05.17 Tue (and following 3 weeks) started looking at microcontroller makers and products for results of this see the Controller_Selection file 2005.05.?? ??? at some time idea that with large (64k..256k or external Flash) controller could put in entire programming environment, get C64 like system usage write an minimal memory based, disk-less operating system something with Forth-like dictionary memory, but no data stack, direct Asm modules with something vocabularies-like, but module::symbol syntax and generally language with C/perl/python/etc syntax and constants would be revival of an old early-1980s C64 project, extended monitor prog with interactive assembler, with full labels, etc 2005.05.31 Tue Karel Kulhavy (Ronja) posts link to open source board w ARM9 I just looked at not usable for me, because cache timing irregular, but nice NSLU2 competitor mention I am interested in high speed hard realtime for signal generating spawns multiple discussions of self brew hardware projects, incl mechanics and about DIP/PGA/2.54mm vs SMD parts and wired/wrap vs print construction 2005.06.03 Fri at work mentioned that I am starting this project, so am now committed 2005.06.05 Sun started this Logfile, collected dates from webcache, agenda, maillist archives wrote Controller_Selection file detailing information collected so far dito wrote Controller_Specification file on what I am planning for and want started writing Video_Signals file detailing what signals are to be generated with an historical look back onto older video signals, how VGA came to be 2005.06.06 Mon finished Video_Signals for VGA, noticed 32/25 lower rate than I had thought corrected Controller_Specification 160/320 pixel from 8/16MHz to 6.35/12.7MHz 2005.06.08 Wed fetched full data sheets for AVR ATmega162, ATmega168 and ATmega1281 and ARM AT91SAM7S256, AT91RM3400 and AT91R40008, and both instruction sets read a few of them ATmega162, AT91SAM7S256, AT91RM3400 (part), AVR instr set while on walk thinking about presenting hardware stuff at LUGS or LUG-Camp first do already intended "behind the compiler" about assembler&co then "programming IO using parallel port", leading then to microcontroller HW access, real time, replacable, smaller, cheaper, less power, less heat decided to first show IO with multiple interfaces on parport for this possibly separate subproject parallel port, with IO modules possibly use above parport project modules on uC suggests an uC board with 2 parport connectors needs 2*(8+4+5=17)pins (8 are GND), so ideal fit for ATmega162 4*8+3 6*8-port chips 3 parports with 1pin unused, 4*8-port 2 par with 1pin unused 2005.06.09 Thu found http://www.mikrocontroller.net/ Forum, lots of AVR vs i51 vs PIC stuff and also FAQs compiled from these (all in german) 2005.06.10 Fri from above site went to article on circuit building techniques http://www.geofex.com/Article_Folders/protostyles/proto_styles.htm his "perfboard plus" technique with solder-through wire is what I intend he also calls it "PCB minus", as good, slow for mass prod, but flexible 2005.06.12 Sun simplest AVR programmer board, parport to 6/10pin ISP (SCK/MOSI/MISO/RESET) powered from controller end, so no problems with missing parport power seems that 6pin official AVR standard, smaller, nothing missing, old 10pin simple STK200 design with just 4 tristate gates, using 2*2 of an 244 http://rumil.de/hardware/avrisp.html 2005.06.13 Mon reworked Controller_Specification, merged Requirements and Rating into one avoided so duplicate data, renamed file to System_Requirements also moved programmer board stuff into Logfile, not an IO module 2005.06.15 Wed updated thougths on specification and on controller selection detailed read of Ubicom data sheets, indir autoinc addr can access near all RAM but it still is a very small device, 4kx12 Flash and 262 SRAM size of 8048 or 89LV-style 8051 or ATtiny, so only if all other fails looking up details at Atmel noticed also new 164/324/644 40pin family w 20MHz 2005.06.16 Thu System_Requirements interfaces added IO pin counts, suggests switch to DIP28 20MHz available earlier, and smaller and so more impressive change selection on pin count, DIP28 enough, smaller, showy, 20MHz earlier tidy up stuff on MHz numbers and instr/pixel and requires MIPS now nice table 40..720 pixel and 1..5 instr/pixel, 1.57..141.60MIPS 2005.06.23 Thu discussion with Hans Franke about this project, he mentions Apple ][ colour gen and actually has an book detailing it on him at the time (on an bike tour!) read that, is simple hi-freq shift register, colour by pulse distribution Hires40 7.159MHz 280pix/line 2clocks/pix, 00,00,.. black 11,11,.. white 01,01,.. gray (at 280pix/line), drop/set bits green/violet or orange/blue Hires80 14.318MHz 4clocks/pix, 4->12colours by 01+C producing DAC for shades 2005.06.24 Fri discussion with Hans, showed him minimal TV 2pin 2 R circuit and detailed minimal VGA (1|3)+2pin and 1|3 R, but better 3*2+2pin and 2*3R to conserve pins poss (2*)joystick as 5|10 input par-ser shift register but IMHO better use larger more pins controller, actually less stuff discussed background+virtual sprite line object list algorithms with variable pixel vs decision times, background just block w full logic vs precompiled pixel line, and more work to compile each line Hans also mentioned ZX-81 circuit (direct instruction codes to video) but that is impossible in controllers, because no prog mem data bus access detailled reread of Apple ][ colour gen stuff, (2|4)*3.5795MHz pixel stepping reread Rickard Gunee colour gen algorithms, hi res intens, low res colour name idea, instead of SoftVGA use VGA+VCS->VGS, better but not yet good 2005.06.28 Tue asked at work ELL what they use as controllers, straight Siemens licensed 8051 so too slow for me, recommended looking at Analog Devices high speed 8051 went reloaded Atmel high speed 8051, still only 2|4k Flash 256 SRAM 20pin 2005.06.29 Wed Video_Signals added more line timing, traceback, overscan details because TV/CGA with overscan and VGA without, 2* horiz but only 25/14* pixels while on walk thinking along line of Greene style uC as timer/addrgen style dev for lower speed few-bits/pixel + shift reg + lookup table based video separate display and draw proc, draw proc direct 6502 or other old 8bit or even like ZX-80/81 style video, display direct by 6502 Controller_Selection 4MHz 6502 and 8/10MHz Z80 added ZX-80/81 style output as it is possible to use an traditional processor, if instr->bits decoder 2005.07.04 Mon decided to drop any 6502/Z80 + SRAM + Flash + TTL style designs are more work, use more space, and lack the elegance of just one chip decided that it is still open whether I will do VGA or PAL TV output so project needs a new name, SoftVideo or better, such as MicroGame split all parport stuff out of this project into separate Parport project removed all VGA and Video references from stuff transfered to that 2005.07.06 Wed while on walk went through options, multiple possible devices: uC: pure software onto VGA, pure software onto TV, shift register onto TV historic processor: shift reg + LUT onto VGA, shift register onto TV looks loke above is about row of increasing complexity, TV worse than VGA 2005.??.?? ??? rest 1/2 and 2006.??.?? ??? and 2007.??.?? ??? first 1/3 near 2 year hiatus, nothing much done, all projects dormant on and off quite a bit of surfing 8051 and other uC stuff, with video in mind also drew an 3x5 pixel font, for fitting in 4x8 character cells http://neil.franklin.ch/Info_Texts/Font_3x5_Matrix and quite a bit of musing on processor architectures resulted notes for own 8bit design, 8080 derived, with best of others added and in depth reading about Charles Moors newer Forth CPUs resulted notes for own similar design, but with more registers, for copy loop 2006.05.01 Mon at VCFe 7.0 saw Replica-1 Apple 1 redesign, 65C02 + 32k SRAM + 32k EEPROM uses AVR+shiftreg+2FFs for B&W TV terminal, instead of orig 1/2 board logic 2007.04.28-29 Sat-Sun at VCFe 8.0 saw Dennis Kuschels MyCPU in operation similar to my PALs/GALs idea, but using EPROM/EEPROM/Flash and 374 Registers he gets an near-6502 from it http://www.cc86.org/~dkuschel/ at VCFe 8.0 saw an Galaxija, ex-Yugoslavia Z80+TTL near ZX-80/81 clone uses similar video RAM reading by processor 1-access/4-cycle instructions reawoke interest in doing an small VGA Video system for gaming also theme of next VCFe will be gaming computers and consoles, fits 2007.05.04 Fri after VCFe 8.0 started discussion with organiser Hans Franke about VCFe 9.0 project to do an workshop that builds an small computer to fit in to the announced theme of gaming computers small system either xgamestation (Ubicom TV/PAL) or own uC or ZX-80/81-like I would prefer VGA as output, and better processor, 8051 or Z80 8051 with external SRAM+TTL/PAL or Z80 with Flash+SRAM+TTL/PAL+rest ideally all of it inside one microcontroller, no external logic larger system for homecomputer revival, 65816, eZ80 or 80186/188 external 8/16M or 1M RAM, and 1/8 or 0.5M Flash, separate video mem entire IO based on USB Host (key,mouse,"disk",sound,video) but also USB device so that can peek on protocols, hack tool Hans dislikes 8051 strongly because data memory mess, and Z80 quite a bit but accepts eZ80 (mainly because 16->24bit extension good, 65816 broken) surprisingly likes 8086/88 because segments usable like 370 adressing 2007.05.18 Fri at LUG-Camp Venty has AVR based geekclock with hin, made at CCC workshop so yet annother 2 Linux people into using AVR chips, seem to be the standard decide AVR is proprietary, but so are extended 8051, and normal 8051 too slow so AVR is back into list of acceptable parts, enough SRAM intern, and speed so this makes an only-1-chip uC system again interesting, 28pin or 40pin? discussion with Venty, 40pin fits better to size given by connectors 2007.05.31 Thu did an analysis of colours generatable with different small size DACs http://neil.franklin.ch/Info_Texts/DAC_Resolution_Colours.html really do want full 3*2bit DACs, only emergency 4bit RGBI or RGBL, or 3bit 3*3bit with cut down to 8bit gives more reds, but not neccessary updated here all entries in 2006/2007, and Controller_Selection list 2007.10.?? ??? to 2007.11.?? ??? tried to get the LT-ACS I bought af VCFe to work, analysed wiring for connector may need to disassemble EPROMs, and may in future want to make EEPROMs so made an EPROM/EEPROM/Flash reader + EEPROM/Flash writer (only 5V prog) connects to PC parallel port, just 2 274s for addr, direct data and control first actual hardware made/wired since over 10 years (made none for PDP-10) but never made the software for it, did not need to do EPROM read and most likely will stay that way, as SoftCPU better ROM per AVR RAM load LT-ACS wiring understood, made adaptor, but DC/DC converter broken, no use 2008.04.26 Sat at VCFe 9.0 saw Dennis Kuschels MyCPU expanded to an full system including RS232 terminal or VGA+PS/2, storage, ported Commodore Basic discussion with Dennis about my ideas for SoftCPU, MyCPU as one candidate at VCFe 9.0 saw AVR ATmega644 ChipBasic, manages 30char/line on SCART RGB TV http://www.jcwolfram.de/projekte/avr/chipbasic32/main.php that recindled VGA generator interest, reawakening of dormant video project but I want 40/30=4/3=+33.3% as many chars in 25/40=5/8=-37.5% of the time he has 6pixel/char, but I can put up with 4pixel/char, -33.3% clocks/char at VCFe 9.0 looked around for old style keyboards, ideally TTY bitpaired none there, only various more or less idiosyncratic home computer layouts took an old dead C64, know that layout, and it was cheapest because dead 2008.05.0x ??? after VCFe massive action of writing down ideas for projects centered around project mail-discussed for a while with VCFe organiser for an universal 8bit bus + swappable CPUs + mult IO cards based system included microcontroller based minimal VGA card, aim 40char wide display that then became the beginning of implementing this project included also microcontroller based microcoded/emulated CPUs for any historic (incl disappeared) or own (never existed) designs should be possible to run at equivalent about 1-2MHz 8bit memory accesses that after a while became the start of this project SoftCPU precise timing calculations 40char*4pixel/char=160pixel, @ 3clk/pixel 18.9MHZ can do this with an standard 18.432MHz 10*RS232baseline quarz gives 2.48% underclocked VGA monitor at an 15.2% overclocked 16MHz AVR decided to go for an separate generic AVR board and plug-on VGA adapter use an with-analog without-ext-databus pinout DIP40 type AVR largest available here in this pinout is ATmega32, get some of these can also be used for other experiments, such as PS/2, Atari Joy/Paddle, etc even for an floppy controller, or as an dedicated small game system VGA adapter on port C, PC7..0 VHRRGGBB, blue 03, green 0C, red 30, h 40, v 80 updated 3x5 pixel font to 3x6 (3x7 underlines), better fit for 4x8 char cells http://neil.franklin.ch/Info_Textst board with 4 8bit/10pin port connectors and 8bit/10pin to VGA HD15 adaptor with 3 2bit R DACs on it 2008.05.0x ??? downloaded AVR programmer and assembler software got parts for an STK-200 compatible programmer and separate AVRisp compatible 3-wire RS232 debug interface and generic ATmega32 development board with 4 8bit/10pin port connectors and 8bit/10pin to VGA HD15 adaptor with 3 2bit R DACs on it soldered all of these together, finished somewhere in 2008.06.0x 2008.06.16 Wed made photo of hardware produced up to now http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1193.JPG updated here all entries in 2008, and todo, and put photo here 2008.07.22 Tue compiled and installed avrdude (loader) and avra (assembler) software just before going on holiday, indended to there read docs and start coding never got around to doing that, also camping laptop power/charging limits 2008.09.11-14 Thu-Sun before and at www.XzentriX.de multiple discussions with Hans Franke about features/interfaces/etc for universal bus+cards based system large selection of card ideas, will only implement a few my main interest is towards all AVR microcoded ones, CPU and IOs 2008.09.12 Fri at www.XzentriX.de used avrdude to program 4 ATmega8 for other participant avrdude -v -c pony-stk200 -p m8 -t avrdude -v -c pony-stk200 -p m8 -U flash:w:SDrive.hex avrdude -v -c pony-stk200 -p m8 -U eeprom:w:SDrive.eep and after also connected and looked into my ATmega32, OK, hardware works avrdude -v -c pony-stk200 -p m32 -t read through avra Example program, to get syntax and initialisation details while there noticed a few amateur built FPGA systems, 1 C-One, 2 1-chip-MSX also one person there started FPGA based oscyloscope vector display was also complaining about tools, long compile times, still >1h for small also announced intentions for making SoftVGA system out of my board 2008.09.13 Sat at www.XzentriX.de read further avra Docs generated m32def.inc based on only given tn15def.inc improved format, bit names direct after their register is defined wrote TxD LED blink test program, see if assembly is working avra -fI -o blink.hex -l blink.list blink.asm avrdude -v -c pony-stk200 -p m32 -U flash:w:blink_test.hex assembles, loads and runs, but factor 15 slower than expected suspect that 18.432MHz/15 ist near 1MHz, is using internal RC osc fuses are set at defaults lfuse E1 and hfuse 99 E1: 7:BODLVL=1, 6:BOD=1 (disable), 54:SUT=10, 3210:CKSEL=0001 (int RC@1MHz) 99: 7:OCDEN=1 (dis), 6:JTAGEN=0 (en), 5:SPIEN=0 (en), 4:CKOPT=1 3:EESAVE=1 (not preserve), 21:BOOTSZ=00, 0:BOOTRST=1 for fast external quarz osc and max stable startup need lfuse=FF 7:BODLVL=1, 6:BOD=1 (disable), 54:SUT=11, 3210:CKSEL=1111 (ext resonator) datasheet suggestes also hfuse=D9 to disable JTAG to avoid static current set fuses, reassembled, loaded, now works as intended 2008.09.18 Thu wrote static VGA output test program, format loop puls+blank+content+blank 12+25+400+13 lines of 30+60+480+30 clocks (= 40+80+640+40 25.18MHz Pixels) avra -fI -o vga_static.hex -l vga_static.list vga_static.asm avrdude -v -c pony-stk200 -p m32 -U flash:w:vga_static.hex in first test sync, line pattern and pixel pattern are 100% right colours black/white/blue/yellow are correct, green/cyan/red/magenta wrong http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1848.JPG suspect AVR board wring, retry with PORTA instead of PORTC, same suspect VGA adapter, is red<->green bit0 small high-ohm short, removed, works http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1849.JPG 2008.09.19 Fri add second test pattern with all 64 colours in it, in bottom screen half http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1851.JPG 2008.09.20 Sat go through notes on how to generate text patterns, threaded jump chain 3+1 pixel wide font as chars*lines/char routines of each 4 out instructions copied/merged many signal/timing/font/generator/etc ideas and info into project docs, as file Generating_VGA_Text most of this is stuff that had been collected in VCFe bus+cards PC project better move it here, generic AVR software VGA, not specific to that project 2008.09.21 Sun continue in updating docs, making propper website, project structure for this Makefile, README, Photos/, INSTALL, FAQ, index.html.en and .de added ../Makefile symlinks to the 2 existing program directories ran make tar to generate an archive file, only code/docs, without pictures showd Photos to Adi, resulting discussion about Pong on it, needs Atari Paddles search for potentiometer resistance value, various claims in range 220k..1M 2008.09.22 Mon copied/merged PS/2 and VCS Joystick+Paddles stuff from VCFe project into here into project docs, files PS2_Keyboard_and_Mouse and VCS_Joystick_and_Paddles search indicates that VCS paddles seem to have 1M potentiometers in them while at it documented pinout correctly, and added pinouts to VGA description 2008.09.26 Fri wrote static VGA text program, vga_text_static.asm first test failled to give an picture, code tidy up replaced 49*8line hack with proper 25*8line, with intermediate empty lines correct computation of SRAM video buffer address, 0..(n-1), not n..1 now get picture, but horizontal timing problems, and only 25*6line picture also 0123 shifting by 1 char is also reversed, same n..1 vs 0..(n-1) http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1855.JPG 0 has lines 0 1 [2345] [2345] 6, 1 has lines 0 1 2 [345] 6 2 has lines 0 1 2 4 6, 3 has lines 0 1 2 [45] 6, missing lines are 3 5 7 2008.09.27 Sat fix above control flow and timing bugs, was in abort pseudo-char 07 computed amount of needed nops for space 1 too little, corrected, works http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1856.JPG dislike loop for drawing lines of an row not in frame control loop archived current as vga_text_static/version_1_row_based/* reworked, also only one time draw code, not unrolled, and all 16 lines drawn having 2 nested loops gives an irregular timing of first line http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1857.JPG dislike (re-)compute in-line frame buffer row SRAM address and line offset archived current as vga_text_static/version_2_recompute/* reworked with both generated in frame control loop, now timing right http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1858.JPG massively dislike complicated error prone frame timing, loop init compensating archived current as vga_text_static/version_3_complex_loops/* tried 30 rows, looks ok, but flicker effect of 70Hz->60Hz is clearly visible (and to think that we one used and liked PAL 50Hz TV displays ...) tried 5line (5/8=0.625 height) instead of 6line (6/8=0.75 height) as nearer to todays 7/12=0.5833 height or 8/12=0.667 height) looks more pleasant, but lacks home computer feeling, some even 7/8=0.875 decided that I also prefer blank intermediate lines over double scan but make sure that both variants are always possible, user choice tried white or cyan or light blue instead of yellow text, less aggressive 2008.09.29 Mon did an larger code tidy up, systematic commends, cycles time in {} archived current as vga_text_static/version_4_tidied_up/* switched from pulse-blank-draw-blank to draw-blank-pulse-blank timing for the larger after-pulse blank time to spare, makes calling easier and with enough time switched to each loop in own subroutine together with an 4+"pre"+n*600-"spare" time computing scheme for line subs gives an horizontal timing error at begin of picture, is not in line timing must be time error switching between vsync blank and draw, found one error made BLLINE display its 480 clock "draw" section as medium intensity orange shows mirror image of resync effect at botton, and comb effect at edges http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1863.JPG turned out to be side effect of draw/blank instead of doublescan, time diff 2008.09.30 Tue factored out the 2 linepair codes, and nop-corrected BLLINE no 8pre case added linepair mode switch, use 1(default) 2nd blank, 0(jumpered) doublescan want PINn6 (next to GND on 10pin headers), use PINB6, SPI, will remain free while testing broke PINB6, as is SPI, progr now fails, return always 0x53 would have been better to have used PIND6, changed code put in new ATmega32, same result, not broken, also exchanged adaper LS367 still same non functioning, checked wiring, no break, no short tried both old chips, works now again, nothing broken, was it wire shorted? mode switching still not works, tried disabling port setup, now always double before always 2nd blank, port setting dep, was using PORTD instead of PIND add per-row changable colour code in LUT registers to frame buffer 2008.10.01 Wed code tidy up, put chars line segment code comments into CHLINE, reworked them also put all abort pseudo-char stuff there, inline, direct before CHEND and improved description of code conversions, indexing, code layouts moved abort pseudo-char to char code, 0xBF, place of non-draw ASCII DEL/127 while at it rearranged drawn characters "0123" to ASCII 0x30..33 and ASCII->code processing for interleaved codes, ASCII/2, non-hole font utilise per-row changing colours, vary red compoment from cyan to white http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1865.JPG extracted raw font data from vga_text_font.inc to vga_text_font.fon added chars 0x20..0x2F and 0x34..0x3F from previously defined font http://neil.franklin.ch/Info_Texts/Font_3x6u7_Matrix 2008.10.03 Fri wrote font compiler for expanding vga_text_font.fon to larger vga_text_font.inc fixed some non-optimal glyphs (+ 4 7 F), some bad but not fixable (# $ & *) added characters 0x40..0x5F, for old style 64chat ASCII, save load time fixed more non-optimal glyphs (K N), some bad but not fixable (M N V W) http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1866.JPG factored out ASCII to charcode conversion, and added ASCII range tests can now draw non 2^n amounts of chars, and shift by 2 or 3 to right without complex algorithm changes or any trouble added characters 0x60..0x7E, as apparently no large difference in load time http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1868.JPG fixed some more glyphs (, . ; :), so that comma and semicolon below text and , consistent in design with ' and `, 2+1 lines with pixels and dot and colon less confusable with underline and equals, now near optimal archived current as vga_text_static/version_5_full_font/* 2008.10.08 Wed Makefile added automatic font (re-)compilation, file dependency rules while at it modified genfont to produce output, to see when it gets used define frame buffer with .dseg and .byte, so later string buffer possible support for strings, with .dw .db "" const, and .byte 2 2 BUFLEN "accumulator" STINIT for lengths setup and STLDI to load constant routine to write string buffer into frame buffer, FBWSTR text does not appear, force stuff into string buffer, output works eliminate lpm instr and use ldi it also works, despite no Z+ happening! but with lpm (for Z+) and after overwriting values it fails again swapped direction of pop/push ZH and ZL, no effect noticed missing call/ret word to lpm byte addr conv, fixed, no effect now re-applied new swapped direction of pop/push ZH and ZL, works split frame buffer init (colours/blank/abort/end) from demo (fgcolour/data) while at it moved DDR stuff to port setup, and PIND6 stuff to fb init frame buffer init no columns loop, use STLDI and string constant but FBWCHAR seems to crash randomly, perhaps on random memory content because no markers yet, so for init use more robust dumb writing routine frame buffer demo use more robust X/Y based drawing, not XH:XL autoincrement nor does not draw at all, most likely frame markers overwritten register usage conflicts, added named registers XYROW and XYCOL, still fail chopped XYCOL to max 31, draws again, shows 2 rows (13,19) drawing wrong chars ghijk (27to31) and klmnopq (25to31) are 12 rows up and 4 cols right http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1869.JPG addresses exactly 12*43-4=512 too small, at addr would be 768 and 1024 most likely also at 256 and 512, but overwritten by later is fault of using add and then subi -1 flags for these are incompatible 2008.10.10 Fri FBUF+2 -> FBUF+FBCOLOURS, in case more or less colour bytes later now that screen content is separate from frame setup, moved to after drawing renamed to FRDEMO to DEMO and renamed LOOP to DISPLAY more varied demo screen contents using positioned strings and colours 3 row ASCII + 6 row rainbow + 3 row announce + 7 row RGB + 2 row site info http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1870.JPG special pre-0x10 codes for inverse video, colour change, underline, etc line begin 6 clocks time, good for loading 3 additional colours changed colour setting stiff to set one at a time, as 5 do not fit in AH:AL added colour loading to drawing, corrected timings, for +6 clocks draw end unneccessary call+return, converted to jmp, further 8 clocks freed added colour exchanges for invert on and off, differ in out register after inverse only background, after uninverse blank, was all ori ZL,0x00 moved code for specials line segments into second .inc file, for auto-gen added colour exchanges for underline on and off, differ in out register added colour exchanges for alternate colours 1 2 and 3, same for on and off better demo for colour switch, explanative texts, 2/3 and 1/3 and pastel http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1871.JPG 2008.10.12 Sun started conversion to interrupt based threading, new dir vga_threaded/* updated Makefile and index.html.en, Makefile fixed a missing things at begin of new coding section, tidy up code, better methods split generic AVR register naming from ATmega32 specific model definitions while at it reorganised my register usage conventions and register naming convert all code to use the new conventions, less collisions, less push/pop WAIT T use T0, change all ldi TL, before calls to WAIT STINIT and STLDI proper use of TH:TL for 16bit counts, A0 for copy RETRINIT use the 4 G0..G3 variables for sync bit patterns, for TL use T0 FBW* switch to T0/T1 for parameters, change in XY* and DEMO FBWSTR YH:YL use ZH:ZH throwaway, no push/pop needed FBINIT use C0/C1 for looping, named by .equ to FBCOL/FBROW FBW* usage AL/AH->T0/T1, as no T0/T1 with C0/C1 collision any more XY* use C0/C1 for looping, named by .equ to XYCOL/XYROW, for TL use T0 CHLINE use the 4 4 S0..S3 and I2..I3 for colour patterns, will later be ISR parameter TH use T1, not TL or T0 because that used in calls to WAIT pass throug in CHPAIR, computed in ROWDRAW ROW* use C0/C1 for looping, named by .equ to FBLINE/RBROW avra fails to make an .equ (or .def) to an register name defined by .def MH:ML can not be used for TH:TL because no immediate, so use ZH:ZL now STLDI collision ZH:ZL and TH:TL usage, and AH:AL non-pushed, tidy up copy Z+ to T0 to X+, count by AH:AL as MH:HL no immed, fit check MH:ML push/pop AH:AL, as its usage is unavoidable, AH:AL allows using sbiw check up also on FBWSTR (and implicit XYWSTR), there different usage, is OK first run blank monitor, bug hunt, found some T0/T1 register collisions gave up on idea of separate P0/P1 names for parameters, increases bug chances still crashed, use TxD debug IF LED to hunt down until where program gets is in DEMO, is in XYWSTR, is in FBWSTR, is endless loop FBWLOOP overjump FBWLOOP, then get picture, stable, lines/timing ok, chars all "." but colours wrong, fg lightblue, bg last set colour, XYWCOLOUR indexing back to FBWLOOP, notices still 2 byte row begin, change to adiw reason was counter TH:TL switched from MH:ML zu ZH:HL, register collision changed all string stuff to STR*, no lds/sts, all accesses via ls/st X+ needy only buffer address label, same also string handling in FBWSTR while at it STLDI ijmp at end, instead of push;push;ret, faster hardware description posts and values converted to .equ lines, symbolic names replace PORTC usage with VGASPORT and VGADPORT, may be different ports because of this also separate NONE for sync and BLANK for DACs changes genfont to use VGADPORT instead of PORTC, and run it archived current as vga_threaded/version_1_resources_renamed/* 2008.10.13 Mon split auxillary into debug and timing, timing just before vertical retrace all drawing stuff together, timing and retrace just before character lines while testing noticed mode not reverting after letting go sometimes even flackering when wire touched, missing pullup was yesterdays port renaming, pullup needs MODPORT and not MODPIN while at that noticed that pin testing still PORTD, missed, corrected that 2008.10.14 Tue completed {pre} comments, always everything preparing next line to be drawn possibly switch back to drawing hsync pulse first, so empty lines return fast thus giving more time for background, to modify frame buffer contents what timing is better, and by how much vert retrace a few times lots of time, or hor retrace often a little time ver retrace gives bulk (450-400)lines*(30+480+60-irq)clocks per frame for irq=20|30|40|50 gives 50*(570-(20|30|40|50))=27500|27000|26500|26000 of 18342000/70=262000 clocks, ca 10%, ca 3-10 times Z80/6502 but no clocks free while large 400/450*1/70s frame draw, irregular timing disconveniences the system sending data to the display allows {pre} calculations of line setup while in hor retrace hor retrace gives distributed 450lines*(60-irq)clocks per frame for irq=20|30|40|50 gives 450*(40|30|20|10)=18000|13500|9000|4500 of 18342000/70=262000 clocks, ca 6.8|5.1|3.4|1.7%, 1-5 times Z80/6502 offers regular amount of clocks free every 31.5us, (10..40)/600th of AVR so still a lot of power (and enough), even in worst case but {pre} calculations may need to go into hor pulse after last line so stay with todays draw-then-horizontal-pulse strategy all lines waiting as long as draw line setup costs, pre-setup in prev line this requires prev line to prepare next line setup, yet annother call better no hierarchical calls and loops at all, pure jmp based state machine each line end computes continuation, store before reti, then irq ijmp this approach may also allow us to utilise both ver and hor retrace time if we can get timer to make 2 continue interrupts, before draw and pulse corrected 18.342MHZ in .db to 18.432MHz, after seeing number in AVR RS232 table 2008.10.15 Wed filled up unused specials char 0x0F with 3nop, no code hole which can crash while at it added 16 2x2 block graphics patterns in font chars 0x10..0x1F allows primitive low-res 80x50pixel block "bitmap" graphics split out DEMO repeated code for the 2 colour bands, calculate the ALT colours use 2x2pixel subgraphics in DEMO, draw an SoftVGA logo, 16 chars wide, 6 high reduce ASCII art to 23chars (because 1 char wide separator) found STRLDI bug when non div by 2 length, in this case code skip filler 0x00 http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1873.JPG 2008.10.22 Wed sync pulses without 4 registers, reduce register count for drawing/interrupt and more important no all-bit writes, sbi/cbi, allow random non-DAC port pins in BLLINE, VPLINE and CHLINE sbi+cbi VGAHPORT pulse in BLLINE (and CHLINE) cbi and VPLINE sbi VGAVPORT state all inside H-Sync pulse, after retrace blank, no timing change outside these renamed S0..S3 to G4..G7, so all of these can be fast globals or specials (re-)use G0..3 for drawing colour bit patterns, not I* while at it, no ISREG for I3, collision danger just as bad as P0/P1 for T0/T1 same with AH:AL for DH:DL, only as AH:AL, also TH:TL for ZH:ZL, only ZH:ZL slight font improvements, for characters # $ { and }, all using underline space and also right-alligned text VGA in logo, slight space between Soft and VGA archived current as vga_threaded/version_2_sbi_cbi_sync/* 2008.10.29 Wed drawing no loop-call-loop-call-draw, instead call-less pure-jmp state machine end of each line switch to next line type, while in horizontal retrace timing blank for old line, pulse for select, retrace for new line prepare move vertical pulse set/clear bit into "draw"/wait, not in horizontal pulse this makes all horiz pulses identical, code for this only once also simplifies adding switch/ijmp stuff later wait and jump to HPULSE is short, fits direct into abort pseudo-character so no CHEND any more, no jumping to that archived current as vga_threaded/version_3_common_hpulse/* CHPAIR split, no-call CH2NDLINE switch, and then PAIRDRAW just call-wait-jmp the later for dropping with all other *DRAW from call-loop-call stuff no YH:YL and to XH:XL copying, only XH:XL and after-use corrections FRDRAW directly set XH:XL, no increment YH:YL (or XH:XL) there either ROWDRAW no multiple movw, after-call sbiw for next time, same as PAIRDRAW noticed that 2nd blank with BLLINE needs XH:XL increment simulation rename T1 into SEGOFF, use I1 global (must be immediate, for ldi/subi/andi) all setting 0x00 and "incrementing" 0x10 in CHINIT and CHLINE, where used CHLINE2 before BLLINE also increment, like for XH:XL CHLINE2 also undo first lines increment, for the second line same archived current as vga_threaded/version_4_tidy_line_addr_segm/* while doing SoftVGA for a while musings on multi-microcontroller homecomputer one microcontroller each for CPU, VGA, key+mouse+joysticks+paddles and facultative then sound, Serial-Flash or floppy all with uCs allows direct serial interface/bus from CPU uC to all IO uCs as side effect of this losing interest in VCFe parallel bus+cards project modular design, VGA at end, key+mouse at beginning CPU in between, in "pipeline", sound after CPU as "filter" joysticks/paddles before CPU as "inserter" and then S-Flash or Floppy beside CPU as "transactor" prefer one such an board over multiple swappable CPU boards and parallel bus requiring on each IO card an parallel bus interface to AVRs and have no interest in minimal parallel-only hex keypad and 7-seg system better VGA full-screen 25*8byte hex+ASCII memory editor, Apple 1 style while SoftVGA is nearing multithreading, thinking about how to test it ideally RS232 ASCII terminal, input from keyboard, need 2nd AVR PS/2->RS232 could then place 3rd AVR in between, as general purpose CPU emulator or even better, for tests/demo just put SoftCPU on same AVR as keyboard even ATmega168 could offer an SoftCPU 8k-of-16k Flash and 0.5k-of-1k SRAM enough for even full monitor or line assembler, or an small Basic/Forth ATmega1284P can give 8k-or-15k-of-16k SRAM and 64k-or-3*32k-of-128k Flash for even more SRAM then make dedicated board with external SRAM with internal ROM from Flash or Flash copied to read-only ext SRAM or even only bootloader in internal ROM, and rest from SPI Flash "module" looks like it is time to start up an official SoftCPU project made SoftCPU project directory, moved various uC microcode stuff into there moved CPU designs from VCFe project into SoftCPU as SoftCPU/CPU_Designs/* moved older CPU sketches to SoftCPU/CPU_Designs/Older_Sketches/* moved older uC CPU Emu sketch to SoftCPU/Microcontroller_CPU_Emulator started SoftCPU Logfile, collected dates from sketches, agenda, logfiles 2008.10.30 Thu continued adding info to above SoftCPU project, expanding Logfile went through PDP-10 and VirtexTools Logfiles plus various other ommisions, and some corrections moved CPU design stuff from VCFe bus+cards PC project microcoded CPU to there as file SoftCPU/Microcoded_CPUs also some prehistory stuff added to this (SoftVGA) Logfile 2008.11.05 Wed designed details of the new state machine based control logic 2008.11.06 Thu abort character again only out BLANK and jmp CHEND, no repeats, no space limit needed for entire FB address, line switch/count setting and continuation test replace hierarchical calls-loop-call-draw stuff with call-less state machine ijmp *LINE after HPULSE, to ZH:ZL set to continuation before jmp HPULSE leaves 60-out(1)-ijmp(2)=57 cycles of time for continuation wait+prepare BLLINE and VBLINE line count use C0 n..1, with BLSTATE and VBSTATE to set up 2 different BLLINEs, for before and after VBLINE, different continuations and different caller and so different *STATE entry timing rename systematic to VRBB*/VRP*/VRTB* with each *STATE and *LINE while at it vertical retrace pulse sbi/cbi in state setup, only once CHSTATE XH:XL = FBUF, ROW = FBROWS..1, SEGMENT = 0x00..0x70, LINE = 0x00|0xFF CHLINE in main drawing no segment modify, and CHLINE2 no un-modify only modify after drawing, in CHEND stuff, if on second line CHLINE2 do not use BLLINE, because yet annother different continuation just fix up address count, then wait, no out BLANK, normal jmp CHEND rename systematic to CH2LINE, or better integrate it into CHLINE 2 tests "first line" and "double scan", true overjump, else blank CHLINE/CHEND flip LINE, if LINE==0x00 increment SEGMENT, range SEGMENT if SEGMENT==0x00 decrement row and poss VRBB state, else XH:XL-=FBROWLEN DISPLAY entry point can use any *STATE, use VRBBSTATE as first test gave crash, because double use of ZH:ZL as state and for unthreading for present ZH:ZL state only used for HPULSE "return", do it different archived broken current as vga_threaded/version_5_ijmp_state_machine/* change to call HPULSE and ret, no switching in there, not timer either while at it better clocks documentation in HPULSE calls and state switches now got an picture again, no crash, but badly distorted mess http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1876.JPG playing with 2nd blank vs double scan shows it to be an "every 4 lines" actually may be only drawing half amount of lines, monitor stretching them with first 1 segment from 1 row, rest 7 segments from next row with double scan only first line of first segment from first row is row stepping triggering on 2nd line of 1st segment, because still seg=0x00 reworked entire CHEND next-line/next-segment/next-row/next-state code now all lines are correctly here, just HPULSE timing bug waive at top CHSTATE seems to be correct, VRTBLINE 1 nop too few, now quite a bit better but still slight waive at top, switch to states with "pre" timing and put all filling in the caller, in the old state gives simpler numbers, and filler after actions, less chance for errors CHLINE blank case same mossing nop as VRTBLINE, fixed, now more waive was all vertical retrace, 55 loop, 4+(15*3+3)=53 instead of =52, add a nop archived current as vga_threaded/version_6_call_state_machine/* updated Generating_VGA_Text timer stuff, most likely only while blank lines HR-blank used and too short, H-pulse too short, HL-blank used partially so first strategy is to use "draw"/wait time of blank lines if no 2nd line blank this gives large 400/450 * 1/70s "hole"/"freeze" but that may be acceptable, still updates every 1/70s, every frame read interrupt handling/timing documentation details in chapter "AVR CPU Core" the last section "Interrupt Response Time" begin INTcall min 4clk (+ presently executing instr) + vector ijmp (3clk) + in+push SREG (3clk) + push regs (n*2clk), then resume drawing code end set continuation + pop regs (n*2clk) + pop+out SREG (3clk) + reti (4clk) requires at least ?+n*2+3+4 + backgr + ?+4+3+2*n+3 = 17+4*4+?+?+backgr time so no chance to return to background while 30+30+60 clock H-pulse stuff so do background only in blank lines, long 450..500 clocks started reading timer documentation details, what are differences T0 T1 and T2 T1 appart from being 16bit, also has 2 outputcompare+waveformgen and also hat inputcompare, from analog mux+comparator, needed for paddles so avoid using T1, only 8bit T0 or T2, but they have prescalers, /8 is OK T2 has async operation, and own oscillator, so avoid using T2, so use T0 2008.11.13 Thu VCFe organiser after 2 months absence appears again in chat showed him project, long discussion of how code works, AVR details in particular from him not knowing AVR code Flash word-addressed thought only used half space, suggested faster algo with double mem need feature request "2nd blank" selectable colour, an moment not, but backgr col request commenting improvements, in particular how un-tokeniser works these are neccessary, code it not easy to understand he noticed that inverse and underline on/off are identical, need only one that I have on/off is remnant of original idea, "current" colour, not swap while explaing stuff, and doing calculations, noticed in listfile near full of 8char/1kistr/2kbyte code used already 0x37A of 0x400, 7/8 used can free 3 of the 8 chars reserved for specials, then 7/11 used suggestion of font instead of 112*8*(10+6) arrangement use 112*(8*10+48) would give 112*(48-1)=5264 (slightly over 5k = 5120) instr usable space auto-spread code into these, with inserted rjmp in laat fo 64 instr can be used for all not timing critical stuff, maybe rjmp trouble would require +0x0A step instead of +0x10, end test 0x50 not 0x00, fix 2008.11.14 Fri dismantled the old C64, for keyboard, for making C64 matrix to PS/2 converter so I can take rest of it to colleage for spares, when there in 2 days from keyfronts seen how extensive their graphics were, 64patterns + 64inverse but a lot of this line graph stuff, requires 8pixel per char width to work VCFe organiser again, he continued working on other untokenising ideas basic segment by routines stays, but as only 16 segment patterns no using of 128-16-1=111char * each 8 segments + 128wod/256bytes = 32k instead only 16 segments, packed in only 256word/512byte (8bit index!) and then 256char * 8segmentindexes * 8bit = 2kbyte/1kword + above the only problem with his method is that it needs am single LPM instr which requires 3clocks, so patterns ()..().. and ..()..() one edge "moved" suggests optimising same-pattern pixel widths for different chars also suggests using full 8bit for colour DACS of VGA output ar alternatively 2 left over ones for effects, such as blinking, dislike 2008.11.15 Sat commenting improvements, better explanations vga_text_font.fon comments p-A (pseudo-ASCII) replaced with block graphics and ASCII added to chars, and aa= gone, and all hh=/ll=/cc= debug stuff was all of no use to font designers, only confusing insider info end of file .org and include stuff also no aa= and hh=/ll=/cc= debug stuff and consequent .equ naming of first/last char code ranges in FBWCHAR use the new FIRSTPSEUDO and ABORTPSEUDO, not IVON and DEL vga_text_specials.inc removed duplicate code on/off for inverse and underline also removed unused char, only 5, 3 char codes more code space for system while at it also reordered least important first, in case space crunch later noticed both on/off needed, because "blanking" from BACK vs FORE so reintroduced them both, so only 1 unused char space saved COL1,COL2,COL3 -> ALT1,ALT2,ALT3, collide with LUT register names change them to LUT*, fixed also in genfont and vga_text_specials.inc hardware description added VGA HD-15 pinout and more DAC description documented here and in Generating_VGA_Text resistance value computations abort pseudochar replaced series of 13 nop line with .dw 13 words of 0 same also after font chars and special chars .dw 6 words of 0 .dw fails to work with multiple words, use string .db "012345678901" in FB* no blank end const 0xBF and 0xFF, give names, at .equ explain values systematically use naming code (chars) vs token (in framebuffer) unthreader better description of aa=0xaa, hh=0xhh, ll=0xll, cc=0xcc stuff describe aa -> hh,ll -> cc - in videoram - cc -> hh,ll -> ijmp at VCFe organisers request made photo of schematic sketches http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1878.JPG are most likely totally useless in that state, but better than nothing draw stuff duplicate .def-s for C0/A0/C1 DRLINE/DRSEGM/DRROW like for G1..G7 named constants VR*LINES for 12/13/25 lines separate FBROWS and CHROWS for later 30 and 25|30 2008.11.16 Sun got from an colleage an 8bit DIP-switch, to make an general 8bit switch adaptor sorted out parts, sawn circuit board, do soldering tomorrow when daylight while there found out he has Atari Paddles, looked inside, are marked 1Mohm wired for left turn max resistance, right turn least resistance but forgot to check up which button pin (1,2) fits to which pot pin (5,9) OTOH noticed that no external "1/2" "A/B" or "L/R" markings on paddles this has to be got from placing them according to how the wires run or simply observing on-screen behaviour and swapping them rework register usage and naming convention, in light of experiences get rid of A0/A1 as never used, and rename AH:AL to DH:DL as no A* any more gives additional T2, as no A* rename C0/C1 to S0/S1 and additional S2 get rid of all A2/A3/T2/T3/I2/I3, as never used entire R2..R15 as V*, just 14byte fast reg variables, work in 16 immediate switchable row count 25/30, defined 2 sets of constants for line/row counts/timings for both VGA text/400@70Hz and graphics/480@60Hz control pin D7, naming SIZ*, "generic" MOD* for existing D6 changed to LN2* CHSTAT sbis/ldi/sbis/ldi for 2 different loop counts, corrected {pre} als all VR*STAT the same switch, even if only slight effect there demo added line 26 annother blank separator, 27-30 only the default dots archived current as vga_threaded/version_7_tidy_variables_comments/* 2008.11.17 Mon soldered together an generic 8bit port to DIP-switch adapter can now switch 2nd-blank/double-scan and 25/30 rows, space for 6 other things 2008.11.20 Thu transfered/collected all 2nd AVR board and 28pin ATmega168 stuff to SoftCPU change drawing variables use those for interrupts, as called by timer int drawing WAIT spinloop T0->I0, and all the many calls to it DRLINE -> VBLINE and CHLINE, DRSEGM and DRROW -> CHSEGM and CHROW place VBLINE/CHLINE in V0, CHROM in V1, CHSEGM in I1 because subi/andi for V0 and V1 need to load constants via I0, only I1 can be direct CHLINE collision variable name and label, label to CHDRLINE, also CHDRSTATE 2008.11.21 Fri read up details in timer T0 documentation TCCR0 control register no force output compare, FOC0(7)=0 no waveform mode, WGM01(3):WGM00(6), but CTC0=WGM01(3), so WGM01:WGM00=10 need clear timer on compare match (CTC) mode no compare match output, COM01(5):COM00(4)=00 clock select int, prescaler 8, and timer start, CS02(2):CS01(1):CS00(0)=010 all of this gives TCCR0=0x0A to set and start timer TCNT0 timer and OCR0 output compare registers 600/8=75 clocks, TCNT0 runs = 0..74, for "MAX" OCR0=74, before TCNT0=0 how far we are after timer interrupt, read TCNT0, for int delay sync TIFR interrupt flags register OCF0(1) flag 1=match, interrupt auto-acknowledge, auto-cleared on exec but to kill multi-hsync-pulse later interrupts while drawing, OCF0=1 TIMSK interrupt mask register enable OCIE0(1)=1, no need clear, no recursive int, kill OCF0 before reti int vector 11, address 0x0014, Timer/Counter0 Compare Match 2008.11.26 Wed split IO bus/slot/card/device stuff from Microcoded_CPUs to Microcoded_IO_Cards added many details of signalling, multidevice cards, SPI S-Flash, flashing decided that 8bit for 256 colours may be worth it, but 3/3/2 division is bad causes R+G (0..7)/7 vs B (0..3)/3, no clean gray levels, murky but would work and be better if all R+G+B 3bit DACs, goes with G+B common LSB extended Generating_VGA_Text with DAC values for 3*3bit, with common G0 and B0 gives 256of512 instead of 64 colours, at cost of +3 DAC resistors and +2 pins and can worst case fallback to todays 64 colours, but offers more and updated analysis of colours generateble with different small size DACs http://neil.franklin.ch/Info_Texts/DAC_Resolution_Colours.html 3*3bit with merged G+B LSB to 8bit gives also 8 grays including better values for "half" (3/7 or 4/7), worth extra 3 Rs so final production non-prototype-board based system will have 3*3bit with V+H single bits on other port (most likely B or D) decided Flash-saving segments only once is good, with separate font index data as it only uses 8*256 bytes font indexes + 256 instr segment routines accept LPM 3-clock and resulting ()..().. 2nd/3rd pixel scew this affects " # % & 0 4 6 8 9 @ A B D G H K M N O P Q R U V W X Y ^ a b d e g h k n o p q r u v w x y that is 1/4 of digits and punctuation, and 1/2 of letters, no blockgraph but today also improved idea, use LD 2-clock, font in RAM, gives softfonts this collides with RAM size limit, may need ATmega644 for 4k RAM, accept ATmega32 no chance anyway near 256char font, but softfonts really worth it 2008.11.28 Fri got from colleage an electronics magazine microcontroller special edition has article about I2C/TWI, read that, triggered thinking on bus interface biggest problem low 400kbit/s data rate, way below 1MHz 8bit parallel bus AVR SPI and USART in sync mode can do fosc/2, gives ca 10Mbit/s, 25 times 2008.11.29 Sat while at Dornbirn LinuxDay detailed read of SPI and USART documentation for communications from/with an 2nd AVR board, for input data/commands USART sync mode is as fast as SPI, both reciever limited same >(2*2clk)/bit as USART better semantics, and choice of geograph or bus addr, use that 2008.12.03 Wed switched all special chars colour swaps to tripple-XOR algorithm, free TEMP reg for USART variants solved handshaking problem, ext INT parallel to RxD allows sender to use TxD->RxD for data and reciever TxD->RxD for startbit same 2 lines opposite when sending in other direction, no extra lines continued with rest of USART documentation and I2C/TWI, will stay with USART decided most likely separate PS/2 and Atari Joystick/Paddle cards allows making PS/2 card before designing Atari card, and simpler timing same advantage also in separating Video and Sound generation and allows independant reflashing, Atari even in-system from system CPU + Video + PS/2 relative fixed, Sound + Atari + Comms + Store variable 2008.12.05 Fri softfonts only space for 96chars, but 16bit indexing may need too much time need to go for 64char (no full ASCII) or 128 (uses too much space) computed max frame buffer size if in ATmega32 2k RAM 1k used for 128char font only loose 8col or 4row or 4col+2row, use the later of these, gives 36x23 gets more chars than current, and optional reuse of 7 colour change specials 2008.12.08 Mon tidied up split of jobs between here and SoftCPU project here maximally an single PS/2 keyboard testwise rest only after 2nd AVR proto board, for SoftCPU, then in there added first set of thoughts for protocol for accessing SoftVGA from ext CPUs in particularly cursor control with simple dumb terminal single 0..31 bytes but also sophisticated techniques possible, single byte 128..255, no escape 2008.12.10 Wed reorganised SoftVGA and SoftCPU directory structure all design texts as Projects//Design/* while at it shortended SoftCPU/CPU_Designs/* to SoftCPU/CPUs/* and SoftCPU/CPU_Designs/Old_Sketches/* to SoftCPU/CPUs/Sketches/* and corrected all symlinks from Projects/Sketches/* to here fixed index.html and one link in Projects/Sketches pointing here updated serial bus and S-Flash timing, and 20-or-24MHz (16-or-20MHz chips) here testing input only from output-only RS232 from PC or an RS232 keyboard PC can't do per-byte handshaking, limit speed by using low bitrate can safely process 1char/frame, max 60char/s, use 300bit/s, OK for typing with that even basic PS/2 to ASCII will be in SoftCPU project, no PS/2 here moved all PS/2 keyboard/mouse (and Atari joysticks/paddles) to SoftCPU are after all now all of them only relevant for IO cards in that system as no use in SoftVGA, updated a few details in those files while at it SoftCPU can do handshaking, then speed limit by that, use max bit rate hardware added variant ATmega168 for converting Commodore 64 keyboard to PS/2 and running experimental version of key matrix to ASCII direct on that no generating PS/2 (use hardware later for that) and so no PS/2 to ASCII and even possible experimental version of entire SoftCPU with monitor on that sorted out strategy/steps for implementing/testing drawing sprites and cursor 2008.12.17 Wed sorted out pinout usage for 2nd AVR, 28pin proto vs missuse C64 keyboard custom what sort of interfaces to use for what, wiring schemes, proto adaptors SoftVGA on ATmega32 proto using sync US(A)RT requires PD->PB0 flyover wire vs key/SoftCPU on ATmega168 requires (fast?) quarz for async U(S)ART timing is given if using ATmega168 proto, but not if less work missuse C64toPS/2 looked at 2 possible hardware variants 2nd proto board 28pin AVR with ATmega168 on it, existing 24MHz quarz input sync serial with PS/2 make/break, output async serial with ASCII one of these with USART hardware, other in software, which for which? ports PB 2other+4SPI+2clk at (bottom or) right side PC 6analog+1reset at right (or top) side, with AVCC and AREF 5V jumpers PD 3USART+2int+3other at left side port for 2-AVR operation, use custom AVR-to-AVR link cable wiring just 1 full 8bit port with 10pin IDC cable 2power+8data, best PD* SoftVGA requires its USART for input, as timing irregular and breaks XCK not part of ATmega32 PD*, is PB0, requires an flyover wire, bad this board has quarz, can do async mode, so no need for sync async is also same mode as used for RS232 from PC via debug adaptor U(S)ART with twisted comms wires, from 2nd/SoftCPU TxD to 1st/SoftVGA RxD and fitting also 1st/SoftVGA TxD to 2nd/SoftCPU RxD, bidir or handshake and consequently also other data twist in pairs, symmetric, incl INTs port for PS/2 interface, no PD, no USART, bitbang fast enough, use any pins and then USART remains free for communication with SoftVGA, better there but all INTs are also on PD*, can missuse ICP on PB0, use PB* ev use an ATmega32 proto compatible PS/2 adaptor problem that requires US(A)RT sync mode, ATmega32 XCK PB0, flyover, bad so better ignore ATmega32 proto compatible, adaptor only for here missuse 28pin custom wired AVR, for converting C64 keyboard to PS/2 input is parallel C64 keyboard matrix, output is sync serial with PS/2 while missuse output is async serial with ASCII requires doing matrix scanning, but OTOH no PS/2 setup/processing needed port for 8 keyboard in, PB 8other, no SPI, intern clk (sync PS/2 no quarz) SPI for programming works automatically, when no keys pressed, no pullups alternat wiring, if using async for ASCII output, requires quarz PB 6other+2clk, 6 keyboard in, 2 clk, use 2 PD for 2 missing, better port for 6 keyboard out, PC 6other+1reset, use 2 PD for other 2 missing port for 1 RESTART, 1 PD INT pin port for 2 PS/2, PD 2US(A)RT(unidir)+1int+5other (1int+2|4other used) wiring for 2-AVR operation, missuse PS/2 cable, just minimal 2power+2data keyboard can use sync mode US(A)RT for PS/2, for that wire TxD+XCK requires data from CPU with software sync, seldom, fast enough also requires async bidir to/from CPU with software async, unfriendly altern PD 2U(S)ART(bidir)+1int+5other (1int+2|4other used), wire TxD+RxD allow hardware async bidir for 5V 3wire RS232 over PS/2 cable/connector but must use software sync PS/2 both dir, use any pins, fast and simple altern either 2US(A)RT(unidir) or 2U(S)ART(bidir), tristate wrong one most flexible, no parts cost, as (just) enough pins available use this ATmega32 proto board PS/2 interface, RxD PD0 and XCK PB0 not on same port either for sync mode requires 2power+RxD+(XCK-flyover-wire), blocks PB* or for async mode use 2power+RxD+any-PD*-best-TxD, no flyover wire this is way better, and compatible with RS232 from PC via debug adaptor but async requires keyboard quarz, low speed existing 4.9152 is enough or fast existing 24 for also running SoftCPU on here, or socketable updated notes on byte codes for controlling video output, terminal features make sure that cursor keys and cursor control are compatible 2008.12.19 Fri after 4 weeks at last entire afternood+evening time, no distraction update understanding/details entry for timer programming at 2008.11.21 Fri update/refresh design for handling interrupts, add missing stuff modify text generator to run from timer interrupt, freeing time for background run drawing from an timer interrupt, threaded as foreground replace the long 55of60 + 480clock wait with background processing code there always ZH:ZL=high:low(*CONT), jmp BACKGR, *CONT: ... continue/resume timepoint before 30clk horizontal right blank this allows time for line count/stateswitch/prepareation int vectors added VEC* label names to all, VECT0CMP: jmp T0CMPINT drawing after WAIT stuff for background "call" to reti and "return" from int BACKGR .. reti, T0CMPINT .. ijmp save/restore ZH:ZL for continuation addr, movw 2 dedicated regs sbi TIFR,OCF0(1) to prevent draw line 2nd interrupt screwing timing push/pop non dedicated registers SR in ISR only sideeffect/used/forget for anything, push/use/pop via I0 ZH:ZL in ISR only load/used/forget for contin and unthread, push/use/pop XH:XL in ISR while entire CHDRSTATE, framebuffer addr incr, must survive push/restore/use/save/pop, save/restore XH:XL, movw dedicated 2 regs DISPLAY simulate ISR int call, setup timer, start drawing cli clear interrupt flag, as interrupt does, same push stuff set up timer TCNT0=0, OCR0=74, TCCR0=0x0A, TIMSK OCIE0(1)=1 run into first line state as if doing stateswitch, to set up drawing use background, set continuation ZH:ZL ldi/ldi, BACKGR jmp done so in all 3 VR*STATE cases, will only jitter rescan jmp DISPLAY -> call, then ENDLESS: rjmp ENDLESS, nop before rjmp for safety assemble fails on sbi for TIRF and TIMSK registers, use ldi/out this also answers question of handling TIFR, out data byte is strobes despite large changes, and timer never used before, it works first time test shows that nop before rjmp ENDLESS is not neccessary use background also in CHDRSTATE, at long last jitter is visible jitter needs compensating for, in ISR synchronise with timer timer sync is only possible to clk/8 because 8bit T0 with /8 prescaler presently 15 + 0..3 clks after TCNT=0, 3 times variable delay +1 clk at TCNT0=0 + 15 + 0..3 clocks, TCNT0=1|2, if 1 delay +1 with TCNT0 is IO addr > 31, so must use in+cmp+branch, no skip possible branch has 1|2 clocks, for fallthrough|jump, jump next instr = delay +1 clk runs correctly, int response + pushes just right timing for 3|4 clock need 2|3 times compensating test with 3 clock instr, background rjmp{2}->jmp{3}, this misshits so add 2 nop-2, now clearly visible, can test 2 times compens, works test with 4 clock instr, background jmp->rjmp, before it call{4} JITTER with only ret{4}, immed visible, fails, and 3clk case now also is timing calculation wrong, forgot jmp{3} from vector to routine moved call DEMO to after call DISPLAY, no visible effect switch to endlessly calling DEMO in loop after call DISPLAY archived current as vga_threaded/version_8_timer_interrupt/* various small improvements line 2 2nd blank mode, option switch for colour background instead of blank FBINIT no FBCOL/FBROW .def variables for S0/S1, add push/pop as they are S* same also XY* and DEMO routines no XYCOL/XYROW .def variables for S0/S1 various of these add missing row/col parameter comments DEMO also add push/pop as they are S*, DEMO ASCII/separ/logo no push/pop DERGB use push/pop instead of S2 (and missing push/pop) FBWSTRING no row wraparound, just abort, eliminate frame end check FBINIT no frame end token write, no FBENDVALUE, FBSIZE no FBFREND side effect of all this is that all of 0x00..0xFF can become valid colours good for when switching to 8bit VGADPORT and sync bits on separate port move XY* framebuffer stuff after drawing, just before demo, easy modify both after XYWSTR add XYWLINE, with included inc S0, as allways used after it DESEPAR changed to also use XYWLINE, XYWCHAR not used any more, leave it 2008.12.23 Tue more small improvements text usage "mode" for size/mode/colour switches tidy up, use "control" endless loop in demo, after building up screen, not in main prog, there jmp modular demo, XYWLINE -> DELINE, split into DE_X ASCII DEASC_3X32 only chars, no 2* 3X4 blanks at front and end for ends not dots full DECLEAR for clear screen, FBROWS times DEBLANK DEBLANK non-colouring 40char space, DEBLACK set colour and jmp DEBLANK graphics DEWAVE_6X23 + DESEPAR_6X1 + DELOGO_6x16 = DEGRAPH_6X40 and for colouring before them DERAIN_6X40, with automatic S0 resetting same also DEMULT_7X40, with before colouring DERGB_7X40 announce message DEANN_3X40, same DEWEB_2X40 all drawing of initial screen in DESCREEN, DEMO only call that and loop later in DEMO loop call all dynamic/animated stuff DECLEAR too specialised, and only 3 lines need it, all 30 is wasted time make DEASC_3X40, 3 clears, and S1 offset stuff, calls DEASC_3X32 2008.12.24 Wed more small improvements save space, where possible 2word jmp/call -> 1word rjmp/rcall in particular all the new call|rcall instr in modular DE* but also all the call|rcall to HPULSE and WAIT in drawing code shrunk from 0x03F3 to 0x0372, = 0x81 = 129instr = 1/9th of code space normalise all comments to begin on column 26 (of 1-80) of source file archived current as vga_threaded/version_9_tidy_demo_call_comments/* for animations background needs synchronisation with drawing, spinloops CHROW runs 25..1, is left as 0, so wait until that hitting 0 but requires first wait while 0, until non-0, works only in 2nd blank mode therefore VB*STATE 3 different values, -1|-2|-3, there var name VBSTATE VBWAIT routine to do the waiting, 2 waits, while -1 and then until -1 while adding this saw 2 commenting errors, outdated CHLINE for label -> CHDRLINE, as CHLINE is now for variable drawing sequence is still visible before blank, changed around and move BACKGROUND,T0CMOINT,DISPLAY after HPULSE, as called later result of this DISPLAY can directly run without rjmp into VRBBSTATE in DEMO ENDLESS: loop insert VBWAIT at beginning first animation, rotate an line background through all 64 colours make FBWCOLOUR counterpart FBRCOLOUR, same also for XYRCOLOUR DEMO in endless loop, FRWAIT loop to decrement frames counter, 3/4s, 52frames DEROTBG_1X40 to rotate red component of one row from DEROTBG_3X40 call for 3 announce rows, use switch 4 to start and stop second animation, horizontally scroll an _@_/ andalusian video snail DESNAIL_1x40 to scroll, in black row above announce use switch 3 to appear+scroll and disappear the snail timing is inflexible, use an 8bit counter/timer variable, 0..255 then in each demo select at what values to do next step DEROTBG_3X40 every 64th (ca 1s), DESNAIL_40_1x4 every 16th (ca 1/4s) third animation, bouncing 3x3 ball in 6x6 field, chop off of ASCII waves DEBOUNCE_7x6 use 1X6 for 2nd DESEPAR_1X6, rest 6X6 for bounce field compute ball position from frame counter, divide by 8, drop right 3 bits take next 3 bits, 8 positions, convert to pseudo-sine 0,1,2,3,3,2,1,0,... with column phase shifted by 1/8th relative to row, sort of lissajou ball drawn with mixed ASCII art + block graphics, in each field half alle 3 current animations, as far as statically visible, video http://neil.franklin.ch/Projects/SoftVGA/Photos/MVI_1890.AVI changed ball in blockgraphics half to also be hollow, looks better 2008.12.30 Tue move animation 2 (snail) to blank row above web address, for better balance change bounce pattern to 2nd type lissajous, hor 16 and ver 8 frames while at it remove push/pop of T0, use T1, for 7-T[01] use T2 T0/T1 diff exposed bug, fix, use column/T1 for ball type, not row/T0 renamed DEBOUNCE_7x6 to DEBOUNCE_6X40, right way round and full size test if cursor display with every 2nd frame is usable, or flickers too much DECURSOR_3X40, overlay by consecutive frames off/on/off/on/... blinking roughly at 3/4Hz, switch every 22 frames, go for 32, not 16 frames 0..15 off and 16..31 (half) on, move through first 8 chars flicker is visible but not problematic, but char and cursor only half bright half bright side effect solves cursor on #$,;_gjpqy{} problem, adds up full alternative without flicker, just blink the character under the cursor because cursor in announce, move colour rotate to ASCII display running out of Flash, of 0x0480 non-font used 0x466, switch to space saving for that start with indirect unthreading, end of this development leg final video for vga_threaded, all 4 effects, final 3 anims and cursor http://neil.franklin.ch/Projects/SoftVGA/Photos/MVI_1891.AVI started conversion to table indirect font jumping, new dir vga_indirect/* switched .current, updated Makefile and index.html.en 2008.12.31 Wed worked out details of what must be changed for new drawing method and sorted into what row they are to be done in order code in file more systematically first all hardware: model, fuses, pinout, wiring then all registers .def: standard usage/naming, specific globals makes it easier tu insert/remove one, without searching all code then all SRAM .dseg: frame buffer, then string (use 40), then snail demo pos makes it easier to see how much used, without searching all code than all Flash .cseg: int vectors, then all the allocted code then unused, then all the special .org code for computed ijump usage added comment declaring where the unused space in flash is in the source code char codes/token distributions/usage are data formats place these after pinouts and before registers and SRAM in particular .equ for FIRSTPSEUDO ABORTPSEUDO ABORTTOKEN rename CH[TG]ROWS to CHDR[TG]ROWS, consistent size with VB*[TG]ROWS clear CHLINE with eor instead of ldi+mov, save 1 instr + 1 reg + 1pre clock before CHDRLINE also CHDRSEGM and before that CHDRROW, as tripple loop will become relevant when later need to reload CHSEGM to 0x3C00 BACKGROUND and T0CMPINT and DISPLAY add pop/push YH:YL, for later use all 3 without register storing for continuation, as only temp for indir ijmp systematic register usage is YH:YL for stable stuff, XH:XL for temps so switch framebuffer pointer to YH:YL, and later use XH:XL for indirect crash, undo edit, OK, repeat edit, crash, undo edit, OK *LINE/etc initial values for VGA timing also up at top, in data usage at same time also vertical blanking state constants with them archived current as vga_indirect/version_1_tidy_reorder_rename/* 2009.01.01 Thu makefile added ..tar, does (cd ..; make tar), make tar while in work directory avr_registers.inc name R2..R15 as fast variables, F0..F13 for specific projects rename then from R15 downwards, F0 longest unused STRINIT YH:YL -> ZH:ZL, as those are temporary, else would need push/pop BACKGROUND/T0CMPINT/DISPLAY push *H:*L, pop *L:*H, so H at higher address 2009.01.02 Fri systematic register usage is YH:YL for stable stuff, XH:XL for temps so switch framebuffer pointer to YH:YL, and later use XH:XL for indirect try again edit, crash, disable 2nd blank backgrounding, now broken picture http://neil.franklin.ch/Projects/SoftVGA/Photos/IMG_1894.JPG in particularly drawing while in vertical retrace, total screwed up VSYNC? possibly false colour values with bit6/7?, st X+ with X destroyed? where? but switching from X+ to Y+ should actually reduce chance of this noticed that YH:YL not used anywhere else, same also save regs, broken chip? remove push/pop, crash, remove movw save/restore, crash, how to test this? looked at partially drawn picture, incl announce, fails on inv/ulin/colours is there any usage of YH:YL there, no, but in code ,X+ not changed to ,Y+ disable DEMULT_7X40, only usage of them, now stable picture, that was cause archived current as new state of vga_indirect/version_1_tidy_reorder_rename/* filenames vga_threaded.* changed to vga_indirect.*, Makefile corrected switch to Flash space saving table indirect font jumping with font tables in Flash, full 256char in only 8*256=2kByte|1kWord code segments each only once, only 8bit indexing time, so max 256word|512byte .orig 32k-2k-512=0x4000-0x0400-0x100=0x3B00, indexes .orig 0x3C00 design new table indirect unthreading method this requires 3-cycle LPM, can fit most segments, if drop redundant outs spread this among rest of the 4 out instr, wherever lpm fits best still hits on all-outs-needed ()..().. and ..()..() combinations draw with middle .. 1 clk wider and middle () 1 clock narrower possibly shifted duplicates of all begin/end pixel on 2/3 pixel but both lpm and ijmp will only work with ZH:ZL, no XH:XL or YH:YL requires switching ZH, more time, not enough time in 4*2 clocks so need to go to 4clock/pixel anyway, 30char/line, so 4*3 for unthread no lpm display irregularite, but also more code, no space for variants switch everything to 30char/line, only FBUF line length, rest follows all 16 segments with labels for low(), SEGM0000 to SEGM1111 plus specials abort, fore<->back on/off (use 8 or 7sp+1), fore<->alt labels SEGMABRT, SEGM0FXB, SEGM1BXF, SEGM0FX1, SEGM0FX2, SEGM0FX3 CHDRLINE enter unthread totally new, again derived from in-char unthreading CHDRSEGM loop CHSEGM select segment index table start .orig 0x3C(00)word = 0x78(00)byte, in CHEND +1 AND, loop reload FBWCHAR no token mangling, as no token picking apart, pure low(