TTL and PAL/GAL Computer
author Neil Franklin, last modification 2012.05.09


Technology

Computer based on standard TTL chips instead of self made transistor modules
  ICs save a lot of time of drudge work of filling boards with components
  ICs allow a lot more logic than self made transistor modules
  ICs save space and power, and are faster on top of all that
  in particular if large MSI TTLs are used, such as 181 and its friends
possibly reinforced with PAL/GAL chips for more effective design
  allow replacing multiple SSI TTLs, all chips up to MSI density
    in particular also all PAL/GAL contain registers, saves 273/374s
or even just standard (E)EPROM chips, same chips as for firmware
  as logic tables for ALU, today large 2Mx8bit w 21 addr lines allow 21 inputs
    limit will actually be max 8 outputs, need 2 for 8bit+carry+otherflags
  and also as microcode sequencer to drive all of system
    and as such shows old historical design/implementation techniques
  same chips as also used for firmware, same programmer, no PAL/GAL programmer
  aim for 3-board design, sequencer + datapath + IO path/timing
    allow multiple switchable designs with only partial multiple builds
    just swap the sequencer board, and firmware module on datapath board
  but then still require 273/374s, which then gives then TTL+(E)EPROM design
    and these most likely required anyway for databus to addressbus, 8008-style
possibly reinforced with SRAM chips for register files, even if large waste
  as old TTL SRAMs may be difficult to get, and many 273/374s use lots of room
in any case only use standard multivendor chips, TTL, (E)EPROM, SRAM, PAL/GAL


Possible Systems

Intel 4004 would be small and trivial, 8008/8080-like/8051-like also
PDP-8 is easy/trivial, PDP-11 or 16bit RISC or T212 are possible
with extra cost even 32bit RISC or T414 style system, actually usable
  or go and reimplement the MIT Lisp Machines, at roughly fitting technology
  or any other similar time workstation, such as Xerox Alto
even a Cray1 clone if enough space/cost are allowed (was 6/10 volume RAM,
  other 4/10: all regs 8bit/chip, logic 2-gate chips, lots of power/cooling)


Parts Selection

for maximal speed use modern F or A TTLs, or better go for HCT, ACT, FACT CMOS
  or even use LV 3.3V parts (save power and are even faster)
alternatively ignore speed and go for minimal part count
  implement bitserial data path, shift registers or bit-addressed SRAMs
use DIP parts, not SOIC or PLCC, so will fit hole raster boards and wire wrap
  no need to go treating PCBs with acid, and no need for photo layout prints
    also go for old fashioned look, like an traditional 1970s system, ev wrap
  but this may limit to max 33MHz, wrap is massive trouble at 100MHz
    OTOH even 10MHz ist most likely fast enough for an small system


Technoloy Level Selection

technology/chiptype levels depending on what chips are to be allowed
  technology standards of early/mid/late-1970s minis and workstations
only one type of gate, such as 2*4|5NAND, same as Cray1 still used
only single gates (2|3|4(|5)|8(|11)-input NAND/NOR/AND/OR and NOT)
  with bus as full muxes, or using OC, or allow tristates
all SSI TTLs allowed incl FFs, possibly limit to 14pin for optical effect
  else 240/244/245 20pin 8*common-control-tristate bus interface is still SSI
all 14pin TTLs allowed, no matter how complex internally
  this adds the use of complete XOR chips (4*2XOR is already MSI)
all DIP300 wide (up to 20pins) TTLs allowed, 20pin mainly tristate and FFs
  possibly limit to no highly complex stuff (no 20pin ALUs, even with regs)
all TTLs without any exeption, aggressive use of all MSI 74xxx, ALUs
  but only use individual TTL parts as far as supply looks safe for future
    particularly problem with specialised function higher integrated MSI 74xxx
    not used much these days since computers made of microprocs and progr logic
all TTLs plus minimal PAL/GALs wherever they are large enough advantage
  in particular random logic where no MSI TTLs available, save lots of space
    also replace missing TTLs, where they have faded/will fade from production
  entire instruction decoder in PAL/GALs, not slow NOT+NAND+NAND in many TTLs
  for barrel shifter single PAL/GAL usable like MIT Lispm 512x4bit PROMs
  but this will require programming PALs/GALs, more work per chip
    possibly just small set of function-independant "standard" designs
replace all TTLs with PAL/GALs, inclusive existing ones, even just registers
  only 2 or 3 chip types (16V8 and 20V8, possibly 22V10), less parts buy/stock
  for single register normal 74S273/374 8bit, or missuse 20pin PAL/GAL for this
    also accumulator can be directly PAL/GAL register of ALU carry stage
      saves chips/space/power and reduces propagation time
    or altern design bitslice, all regs+muxes+ALUfunct in 1 PAL/GAL per n bits
      only minimal carry stuff in horizontal PAL/GALs, get fastest propagation
  also GALs are even available in 3.3V fitting with ZBT SRAMs and SD-RAM DIMMs
    and so reducing power consumption, power supply size
  also GALs are faster than fastest 74Sxx, far faster than 74x74 or 74xxx
    3.3V are down to 3.5ns (allow 33..66MHz design, 1970s ECL speed Cray1-like)
      even 5V are down to 5ns (allow 20..50MHz design, 486-like, so usable)
      30MHz 32bit is faster than 386-16 on which Linux was originally developed
    this would allow about system speed of late-1990s old FPGA soft CPUs
      so no need for large programmable chips, nor their closed software tools
  but this will require programming PALs/GALs, more work per chip
    possibly just larger set of function-independant "standard" designs
    basically build an own logic family, based on 20 (and poss 24) pin chips
    even for 74181-like ALU better 2 levels of GALs (function+carry)
or even use (E)EPROM or Flash chips
  in particular if PAL/GALs not powerfull enough (for 74181?)
    or even entirely, instead of PAL/GALs, same chips+tools as for firmware
  but this has then far highter (more than *10) propagation delays
    OTOH far simpler to program, convert formulas to bit tables
only use (E)EPROM or Flash chips
  in this case no PAL/GAL chips, no PAL/GAL programmer needed
definitely no larger programmable chips, CPLDs or FPGAs
  because no open source tools and are single manufacturer parts
  even if they were OK to use, hardly any DIP parts (old CPLDs), PLCC or worse


Memory

for memory 8bit wide 62xxx (32|128|512kx8) SRAM chips, compact, simple to use
for register sets either multiple 273/374 or PAL/GALs or above SRAMs
  SRAMs are slow (but still 2 times faster as 74x170 were), and no dual port
    but save on space, only one set for many registers, switchable reg banks
  TTL/PAL/GALs use lots more space, either one set per 8bit register
    or use 20V8|22V10 as 3port 6|8 1bit regs (6|8out data, 2 out read muxes)
    but are 5|5|10 times faster than 74x170 were, and offer multiport
  this problem suggests making 1-acc machine, ev stack machine with implied TOS
    all the rest of data in main memory, which in SRAM will be fast enough
no ROMs, use self-booting disk controller design or front pannel
  or use PC BIOS ROMs for this, f p code, even though far too larger space
  or use PC BIOS ROMs, full firmware operating system, no boot


IO Disk

for disk space standard IDE parts, so full speed and space
  alternatively use CF or SD cards, space more realistic, speed varies


IO Video

in processor also DMA address register, special microcode mode similar to AVR
  also CLUT register(s), copy these to external 734, with RGB DACs behind
    basically the same signal generation method as in SoftVGA PIO
  add to this external pixel/frame timing, at least H-sync
    microcode branches on/after begin H-puls, waits for end H-sync, draws


IO Other

standard normal PIO-style with out 273/374 and in 240/244/245