SoG based Open FPGA Specification(s) author Neil Franklin, last modification 2004.01.11 4x4=16bit 1 2bit 4:1 InMux + 1 active + 4 neighbor NOT->NAND + 1 inv + 4* 2bit 4:1 OutMux minimal size, only NAND(/AND), no Mux possible, no Latch or FF possible 4x4=16bit 2 2* 2bit 4:1 InMux + 4bit/2LUT + 4* 2bit 4:1 OutMux minimal size, all 16 functions, no Mux possible, no Latch or FF possible 4x4=16bit 3 2* 2bit 4:1 InMux + 4bit 74181-S0..S3-functions + 4* 2bit 4:1 OutMux minimal size, all 16 functions, no Mux possible, no Latch or FF possible 4x4=16bit 4 2* 2bit 4:1 InMux + 2* Inverters + 2bit 4:1 Mux 0/1/-I2/F + 4* 2bit 4:1 OutMux basically CAL1024 18bit without global clock or F.out bits minimal size, Latch logic possible "F" in Mux, not all 16 functions, no Mux 4x4=16bit 5 2* 2bit 4:1 InMux + 2* Inverters + 2bit 4:1 Mux 0/1/-I2/FF + 4* 2bit 4:1 OutMux as above, but instead of F for Latch, 11 is F.out pattern minimal size, FF poss with 11 in "Mux" losing logic, not all 16 funct, no Mux 4x4=16bit 6 3* 2bit 4:1 InMux + 2* Inverters + 4* 2bit 4:1 OutMux minimal size, 14 (2 dup) functions, Mux possible, no Latch or FF possible basically XC6200 function generators in CAL1032 surroundings 5x5=25bit 1 2* 2bit 4:1 InMux + 5bit 74181-S0..S3+M-func + 4* 2bit 4:1 OutMux + 8bit FFctrl all 16 functions, arithmetic direc, elaborate FF add to logic poss, no Mux poss poss use some of the 8bit FF ctrl for Mux separate add to logic 5x5=25bit 2 3* 2bit 4:1 InMux + 2* Inverters + 4* 2bit 4:1 OutMux + 9bit FF ctrl 14 (2 dup) functions, Mux possible, elaborate FF in addition to logic possible 5x5=25bit 3 3* 2bit 4:1 InMux + 8bit/3LUT + 4* 2bit 4:1 OutMux + 3bit FF ctrl 3bit FF: 000 non 001 latch, 01c D-FF (c clock inv), 1rc D-FF (r reset polarity) all 256 functions (arithmetic anydir), simple FF in addition to logic possible poss FF ctrl can select 3->2LUT downgrade, 4->7bits elaborate FF reducing logic 5x5=25bit 4 no InMuxes, 16bit/4LUT + 4* 2bit 4:1 OutMux + 1bit FF ctrl all 65636 functions, but seldom 4 inputs providable, so often not usable FF poss but needs separate circuit, allows "skewed" reduced 4->3LUT logic 8x8=64bit 1 no InMuxes, 4* 16bit/4LUTs, OutMuxes, single stage logic all 65636 functions, 4 of them, no Latch or FF poss, far most bits can run all data, control, carry, clock at exact same speed but as all bits are one 4 4x4 SRAMs with common Muxing, not massively large --- Up to here only 4 neighbor routing (n* 2bit 4:1 InMux + 4* 2bit 4:1 OutMux) This has turned out to be not enough, so cells need to be degraded to non-logic All newer commercial SoGs (and no hobby/open one so far!) have more routing 4x4=16bit 1 4bit 16:1 InMux + 4 neighbor NOT->NAND + 4* 2bit 4:1 OutMux minimal size, only NAND, no Mux possible, no Latch or FF possible lot more input can take from lot further away than neighbors 5x5=25bit 1 2* 4bit 16:1 InMux + 5bit 74181-S0..S3+M-func + 4* 2bit 4:1 OutMux + 4bit FFctr all 16 functions, arithmetic direc, elaborate FF add to logic poss, no Mux poss poss use some of the 8bit FF ctrl for Mux separate add to logic lot more input can take from lot further away than neighbors 5x5=25bit 2 3* 3bit 8:1 InMux + 2* Inverters + 4* 2bit 4:1 OutMux + 6bit FF ctrl Mux possible, simple FF in add to logic poss, 14 (2 dup) functions more input can take from further away than neighbors 5x5=25bit 3 3* 2bit 4:1 InMux + 2* Inverters + 4* 3bit 8:1 OutMux + 5bit FF ctrl Mux possible, simple FF in add to logic poss, 14 (2 dup) functions more output can give from further away than neighbors 5x5=25bit 4 2* 5bit 32:1 InMux + 5bit 74181-S0..S3+M-func + 4* 2bit 4:1 OutMux all 16 functions, arithmetic direc, no Latch or FF possible, no Mux poss 32:1 = 4 dir * last 8 outputs star, OutMuxes in Routing (self + 3 dir pass) no need to lose logic for routing, allows 1bit/Mux logic hand placing 5x5=25bit 5 2* 5bit 32:1 InMux + 2* Inv + 2bit 4:1 Mux 0/1/-I2/F + 3bit FF + 4* 2bit OutMux all 16 functions, no Mux possible, simple FF in addition to logic possible 32:1 = 4 dir * last 8 outputs star, OutMuxes in Routing (self + 3 dir pass) no need to lose logic for routing, allows 1bit/Mux logic hand placing 5x5=25bit 6 3* 5bit 32:1 InMux + 2* Inverters + 4* 2bit OutMux in Routing 14 (2 dup) functions, Mux possible, no Latch or FF possible 32:1 = 4 dir * last 8 outputs star, OutMuxes in Routing (self + 3 dir pass) no need to lose logic for routing, allows 1bit/Mux logic hand placing 6x6=36bit 1 3* 5bit 32:1 InMux + 2* Inverters + 11bit FF and other + 4* 2bit OutMux in Rout 14 (2 dup) functions, Mux possible, elaborate FF add to logic poss 32:1 = 4 dir * last 8 outputs star, OutMuxes in Routing (self + 3 dir pass) no need to lose logic for routing, allows 1bit/Mux logic hand placing 6x6=36bit 2 3* 5bit 32:1 InMux + 2* Inverters + 7bit FF and other + 4* 3bit OutMux in Rout 14 (2 dup) functions, Mux possible, elaborate FF add to logic poss 32:1 = 4 dir * last 8 outputs star, OutMuxes in Routing (self + 3 dir pass) no need to lose logic for routing, allows 1bit/Mux logic hand placing 6x6=36bit 3 no InMuxes, 16bit/4LUT + 4* 3bit 8:1 OutMux + 8bit FF ctrl all 65636 functions, elaborate FF in addition to logic poss, large more output can give from further away than neighbors 6x6=36bit 4 no InMuxes, 16bit/4LUT + 4* 4bit 16:1 OutMux + 4bit FF ctrl all 65636 functions, simple FF in addit to logic poss, lots of output, large poss FF ctrl can sel 16->8 OutMux downgrade, 4->8bits elaborate FF reduc OutMux lot more output can give from lot further away than neighbors 6x6=36bit 5 no InMuxes, 16bit/4LUT + 4* 5bit 32:1 OutMux all 65636 functions, no Latch or FF possible, large lots of output, large poss FF ctrl can sel 16->8 OutMux downgrade, 4->8bits elaborate FF reduc OutMux large lot more output can give from large lot further away than neighbors --- 7x7=49bit 1 4* 5bit 32:1 InMux + 16bit/4LUT + 5bit FFctrl + 4* 2bit OutMux in Routing all 65636 functions, simple FF in addit to logic poss, largest 32:1 = 4 dir * last 8 outputs star, OutMuxes in Routing (self + 3 dir pass) no need to lose logic for routing, allows 1bit/Mux logic hand placing with routing+LUT+FF this is near full LUT FPGA, just missing carry or RAMs 8x8=64bit 1 same as above, just 15bit more for carry or RAMs, full LUT based FPGA