Minimalist Computer Architecture, Narrowed down Data, still enough Adresses author Neil Franklin, last modification 2009.10.08 to use for an Basic Calculator or Programmable Calculator type Machine simple enough to implement in 1960s with individual transistors max volume cabinet of drawers, ideal volume HP9100 electr typewriter size look at existing architectures for hints how to do it start at Whirlwind, universal narrow system, basic design, von neumann 16bit data, mem, alu, acc, instr 5+11bit opcode+addr, 2kWord cycles instr, no indirect, data TX-0, reduce opcode bits, to test TX-2 36bit 64kWord memory 18bit data, mem, alu, acc, instr 2+16bit opcode+addr, 64kWord cycles instr, no indirect, direct PDP-1 and PDP-4, add indirect mode 18bit data, mem, alu, acc, instr PDP-1 5+1+12bit opcode+indir+addr, 4kWord PDP-4 4+1+13bit opcode+indir+addr, 8kWord cycles instr, ev indir, (ev proinc?), data LINC, split addr width, 2+bit/4*mem variant of very limited L-1 12bit data, mem, alu, acc, instr 2+10bit opcode+addr, 1kWord and 2+5+1+4 opcode+opcode+indir+addr, 16Word "zero page", indir 1kWord cycles instr, ev "zero page" indir, data CDC160, expanded indirect, autoincrement adressing, immediate addr/const 12bit data, mem, alu, acc, instr 4+2+6bit opcode+indir+const/addr, 64Word "zero page", indir 4kWord cycles instr, ev "zero page" indir, ev "zero page" preinc, ev data PDP-8, larger page size, split as zero and current page 12bit data, mem, alu, acc, instr 3+1+1+7bit opcode+indir+curr+addr, 128+128Word "zero+curr page", indir 4kWord cycles instr, ev "zero/curr page" indir, ev "zero/curr page" preinc, data 8008/8080, only reg indir, doubled indirect width, immed addr/const, 8080 stack 8bit data, mem, alu, acc, instr 2+3+3bit opcode+opcode/addr+addr, (6+1+1)Byte "registers" indir 8008 16kByte (drop 2 bits) and 8080 64kByte and RST-only 2+3+3bit opcode+addr+opcode 8 short-call points cycles instr, 8080 ev addr16.1 and addr16.2, ev const or data Z80, PC relative addr, else as 8080 6800/6809/6502, pure 8bit opcode+indir, all const+addr+rel immed, zero page enough space add ROM, is cheaper, address half RAM half ROM, each still 32k in ROM device microcode, simpler and cheaper IO and storage devices in ROM machine code monitor, uses IO devices, save cost of cons front pannel in ROM FP (use FP acc), other libraries, saves RAM and uses runtime linking save even more RAM if short RST style calls to libraries in ROM FP pseudoinstr interpreter (use FP acc and 2nd op addr) only one call neded, then FP instr like sweet16, 2+4+2bit opc+addr/4+opc possibly even FP driven looping constructs, call outs to machine code in ROM line assembler user interface, ev disassembler, save programming time no handling of external binaries, only text, reduce cost storage device in ROM HLL interpreter, save more programming time, escapable to machine code this ends up with typical late1970/early80s Basic microcomputer design from here on harward, separate code/data memories and address spaces no code from RAM, only from ROM, loses escapability to machine code only if fixed function or interpreter ROM based device no writing to ROM, so call/return addresses on stack, in RAM or separate 8051, only reg indir, doubled ROM address width, immed addr/const, PC rel addr 8bit data, mem, alu, acc, instr 1+3+1+3bit opcode+opcode+indir+addr, 8Byte "registers" indir RAM 256byte and ROM 64kByte ROM cycles instr, ev ROM+addr8 or ROMaddr11.2 or (ROMaddr16.1 and ROMaddr16.2) or RAMaddr8, ev const RAM cycles ev indir, data 8048, only reg indir, reduced one-and-half ROM indirect width, immed addr/const 8bit data, mem, adder, acc, instr 1+3+1+3bit opcode+opcode+indir+addr, 8Byte "registers" indir RAM 256byte and ROM 4kByte ROM cycles instr, ev ROMaddr12.2, ev const RAM cycles ev indir, data PIC, different ROM/RAM data width, only mem 0 indir 8bit data, mem, alu, acc, PIC165x 12bit instr, PIC 168x 14bit instr 3+9/11bit opcode+addr, 512Word/2kWord ROM 3+1/3+8bit opcode+opcode+const 3+4+5/7bit opcode+opcode+addr, 32/128byte RAM, indir 16+8*16 / 32+4*80+16 ROM cycles instr RAM cycles ev indir, data 4004/4040, 4bit data memory, for BCD, only reg indir, immed addr/const 4bit data, mem, alu, acc, 8bit instr 4+4bit opcode+opcode/const/addr, 16Byte "registers" indir RAM 2reg 256nibble and ROM 4kByte ROM cycles instr, ev ROMaddr12.2, ev const RAM cycles 1st instr indir, 2nd instr data HP9100, 56*(2+4)bit FP data memory 4bit data, alu, acc, 56*(2+4)bit mem, 64bit instr 6+58bit opcode+rest, (7+16)*14nibble, indir unknown, cycles unknown HP9800 bit serial, 16bit, for BCD 1bit alu, 16bit data, acc, instr 4+12bit opcode+rest, indir unknown, cycles unknown HP35/45/65, bit serial, wide memory, for BCD, only reg indir 1bit alu, 14*4bit data, acc, mem, 10bit instr 2+8bit opcode+address, 16pages*256Word ROM, rest unknown resulting architecture 1bit small (e)prom alu, bitserial, high clock 4|6|8bit memory, depends on memory phases, cpu clock, and shiftreg size n*1|2*memory=4|6|8|12bit user program token for interpreter n*1|2*memory=4|6|8|12bit machine code instruction, full von neumann 2|3*memory=8|12|16|18bit exponent of floating point 2|3|4|5*memory=8|12|16|18|20bit addresses, memory word or full word? possibly 1/2*float=24|32bit integer "halfword" to save space 40|48|56|64bit floating point "fullword", 3/4 mantissa, 1/4 exponent