Simple 8Bit Accumulator+Registers Computer
author Neil Franklin, last modification 2006.05.09

somewhat Intel 8008/8080/8085 like
  but with accumulator separate from regs, full 8 8bit regs (like 8048/8051)
    OTOH lacking direct register->register transfers
  and multiple register pair indirect operations for memory access
    including with auto-increment operation for faster (like 6809)
  replace 2+3+3bit format instructions with more hex friendly 4+4bit format

8 instructions ADD/ADC/SUB/SBC/AND/ORA/XOR/LDA, op(A,data)->A
  ADD/ADC/SUB/SBC with carry chain active, AND/ORA/XOR/LDA without
    ADD/SUB no carry-in, ADC/SBC with carry-in, rest doesn't matter (no carry)
    all set M(minus) and Z(zero) flags, ADD/ADC/SUB/SBC also C(carry) flag
    LDA treated as special case of ALU op, data, no A, no need for ALU/load Mux
  with 8 register PH PL (pointer) RH RL (readp2) WH WL (writep2) SH SL (stackp)
       8 memory   (P) (P++) (R) (R++) (nn) (I++)[=#n] (S++)[=POP] IO(n)[=IN]
         P++/R++ stuff is compacter and faster than additional INC/DEC rp instr
           and no opcode space used up for separate  INC/DEC rp
           and no flags modified, just like if special  INC/DEC rp
         P++/R++ all use same 16bit addressbus+1 increment method as I++ uses
           this may be ALU load from reg out bus or data bus + carry 1
         (nn) stuff is compacter and faster than first loading 2 addr registers
           and no instruction space used up for separate  LD[PRW] #nn
             but  LD[PRW] #nn  would also be good for loop begin loading
             dito  LDP ([PRW])  or even  LD[PRW] ([PRW])  for pointer chasing
             dito  ADP [PRW]  and  ADP #nn  could be usefull for indexing
           uses an TH + TL temp register pair for 2 address bytes from memory
         (I++)[=#n] stuff is next instr byte, faster+compact than (nn) + const
         IO(n)[=IN] has an automatic 1-cycle interrupt lock-out for
           LDA #n, op IO(n), *locked*, STA IO(n)  for interrupt-safe IO
  format 1  op<0..7>  reg/mem<0..1> reg-sel/mem-mode<0..7>

1 instruction STO, A->data
  separate from load, even though usually logically grouped with LDA
    but is totally different operation, no changing of A, rather of reg or mem
    just tristate gate to get A out bus to data bus, or A second output port
  with same 8 register
       same 8 memory, but
         (R) (R++) replaced by (W) (W++) second write
           for op(1[],2[])->3[] triple array stuff, as P++/R++ already 2 reads
         (S++)[=POP] replaced by (--SP)[=PUSH]
           the --SP needs an decrementer, before address being output
             can be done with ALU in invert operand and carry clear mode
         IO(n)[=IN] replaced by IO(n)[=OUT]
         (I++)[=#n] is nearly senseless, but can be used (1 write mult read)
           but this technique fails when code resides in ROM, not changable
           possibly reuse this opcode for IO device select, as DS(n)
  format 0 0 0 1  reg/mem<0..1> reg-sel/mem-mode<0..7>

4 instructions SHL/ROL/SHR/ROR, op(data)->data
  SH* incl output into carry, RO* same but with also in from C (=SH*C, 9bit)
    arithmetic SH* (keep MSB) and 8bit RO* (out direkt to in) must be emulated
    SHL/ROL by using ALU ADD/ADC(data,data), SHR/ROR by mux in ALU carry XOR
    all set all 3 flags M(minus), Z(zero) and C(carry)
  with 8 same registers and memory modes, but
    nearly senseless memory (I++)[=#n] replaced by A
      this replaces need for  STA r, shift r, LDA r  or  STA r, ADD/ADC r
    for all memory modes use an TD temporary register, not TH + TL as in-use
  format 0 1 carry<0..1> dir<0..1>  reg/mem<0..1> reg-sel/mem-mode<0..7>

1 set of 16 program control instructions
  JMP #nn->I, CALL I->(--S) #nn->I, RET (S++)->I
  NOP, HALT, DI/EI
  possibly PUSHF/POPF or interrupt auto-push and RETI auto-pop flags
  possibly RST/SWI/BRK/INT/SystemCall 1byte CALL
  format 0 0 0 0  ????,  if too few missuse a few senseless DJNZ (rp++) opcodes

1 instruction BR[N][ZMC], condit (I+n)->I or nn->I
  with 16 conditions, N(not, invert) xor ( M(minus) or Z(zero) or C(carry) )
    condition 1000 gives unconditional BR (or JMP), 0000 gives 2/3-byte NOP
    possibly save opcodes with only 8 conditons: N 0/M/Z/C or N M/Z/MZ/C
      extreme case save even more, only 2: C/NC, no zero or minus detect/flags
  format 0 0 1 0  invert<0..1> cond-flags<0..7>

1 instruction DBNZ, (data-1)->data, zero condit (I+n)->I or nn->I
  with 8 same registers and memory modes as shift/rotate group
    DJNZ (rp++)  are completely senseless, possibly reuse for other stuff
    also  DJNZ #n  is nearly senseless, but most likey not worth reusing
  is compacter and faster than separate  DEC/INC reg  instr and then  BR Z
    and like with ++ no flags modified, just like if special  INC/DEC reg
  or possibly IBNZ, if simpler to do, but only 1 of these 2 forms
    increment may be easier on ALU (add) and on test (carry instead of zero)
    but needs loop counter loading with 0-count, runs -count .. -1
  format 0 0 1 1  reg/mem<0..1> reg-sel/mem-mo<0..7>