8Bit 16Register Computer - 16bit 2Address Instruction Set author Neil Franklin, last modification 2009.02.04 design features registers+ALU 8bit data 2-address system without dedicated accumulator/temporary 2-operand both on 16 regs and direkt on memory 16 modes, like in PDP-11 not only reg+mem/reg as in 8086, not only reg+reg as in AVR 16 8bit registers also usable as 8 2*8bit register pairs no special 16bit ops for load/add address arithmetic decrement-and-jump, like Z80 and 8048/8051 DJNZ, save separate DEC time in particular fast block copy, together with auto-postincrement memory 16bit address 16bit programm counter all branches (conditional) w 8bit offset, like 6800/6802 6809 6502 and fitting also jump (uncondit) variant w 8bit offset, like 6809 8086 only register based addressing, full 2*8bit full 2*8bit stack pointer, not 8bit part-of-memory stack stack pointer one of general purpose registers, for more flexible PUSH/POP 3 2*8bit address register pairs to prevent slow memory-indirect addressing, unlike 6800/6802 or 6502 but can double as normal data registers, not only-16bit like 6809 mult reg-pair indirect memory accesses, like in 8048/8051 and 6809 but with full 16bit addresses unlike 8048/8051, and regpairs unlike 6809 address registers with autoincrement, save separate INX/DEX time like in 6809 registers, and in Z80 LD[ID]/CP[ID], but no LD[ID]R/CP[ID]R stack and 1 address register pair 16bit index addressing no 16bit address manipulation ops, must use dual MOV or ADD/ADC this is acceptable as most common case INX/DEX is by autoincrement IO space 16bit address separate IO space, to not cut off small stuff from large memory Instructions 16bit opcodes, usually word alligned hex friendly 4+4+4+4bit format instr, not n*(2+3+3)bit or even worse format op+destreg/op+const/op+sourcereg/const/op usage of fields result is a mixture of AVR and my 8bit_Accu8Reg_8bit_1Addr intended to be the best features of both of these systems together is also somewhat PDP-11 derived, reduced to 8bit, non-orthogonal addressing from 8bit_Accu8Reg_8bit_1Addr instruction/operation selection combined memory access and arithmetic registers and addressing registers+modes (but 16+16, not 8+8) flags set for status and control from 6800/6802 via 6809 (and also from 8086/8088) 4bit/16combinations as conditions for branch instructions from AVR 8bit constant in 16bit word, effective on 16 registers 2-address system (but with only above 16 registers, not 32) only part of registers usable as 4 address register pairs naming of X and Y and Z for address register pairs interrupt request as flag (not just interrupt enable) from PDP-11 2-address instructons with 2 full any register/memory mode operands registers 8bit R0..R7 general purpose registers 8+8bit R8..R15 address+stackpointer register-pairs X=R8+9 Y=R10+11 Z=R12+13 S=R14+15, also usable as general purpose registers alternatively R0..R15 usable as address+stack register-pairs 16bit P program counter, dedicated, not in arithmetic 8bit F flags status flags are: 7:Minus 6:Overflow 1:Zero 0:Carry changed when Arith/Shift all MOZC, Logic/Load only MZ control flags are: 5:ProcReset 4:ProcHalt 3:IntReqest 2:IntEnable setting IntEnable has an automatic 1-cycle delay, allows using PPF or ORF #$04; *locked*; RTS; *unlocked* for return from interrupt setting ProcHalt halts the processor until interrupt or reset is applied memory 64k*8bit general purpose program and data memory 64k*8bit separate IO space, only immediate addressing instructions oo o o dddd cccc cccc register+8bitconstant instructions oo o o = operation: 0000..0011 used for 2-address register/memory instructions 0100 used for NOP/JMP/BRA jump and conditional branches instructions 0101 used for DBN decrement branch nonzero instructions space for 10 operations with 0110..1111 opcodes MOV, AND/IOR/XOR, ADD/ADC, CMP/CPC no SUB/SBC (use ADD/ADC negval) (also MOV 0 = CLR, MOV -1 = SET, XOR -1 = INV, ADD 1 = INC, ADD -1 = DEC) dddd = dest+s1: register R0..R15 for destination (and first source) all of these only work on registers, not on memory cccc cccc = source2 const: 8bit constant/immediate second source 00 s d dddd oooo ssss 2-address register/memory instructions s = source2 type: 0=reg/1=mem for second source d = dest+s1 type: 0=reg/1=mem for destination and first source dddd = dest+s1: register R0..R15 or memory mode ssss = source2: register R0..R15 or memory mode where for memory modes dddd and ssss are format rrmm (regpair+mode) X/X++/--X/??, Y/Y++/--Y/??, Z/Z++/--Z/??, S/S++/--S/?? the ?? are special cases, [nn]/IO[nn]/[Z+nn]/[S+nn] alternatively memory dddd and ssss are format rrrm (regpair+mode) allows all regpairs R0+1, R2+3, .., R14+15, but only Rn/Rn++ or --Rn/Rn++ with Rn/Rn++ need special case stack dddd/writing/pushing S/--S or even 5|4 regpairs Rn/Rn++ and 2|3 regpairs and stack Rn/--Rn with --Rn/Rn++ need special case stack dddd/writing/modding --S/S or even 6|5 regpairs --Rn/Rn++ and 1|2 regpairs and stack --Rn/Rn with 1 regpair (R0+1) replaced by the 2 special cases [nn]/IO[nn] oooo operation: space for 15 operations with 0001..1111 opcodes (0000 1-address) MOV, AND/IOR/XOR, ADD/ADC/SUB/SBC, CMP/CPC, TST ev multibitRO*/SH*, ev XCG (semaphores!), ev MUL/MAC (also ADD self = SHL, ADC self = ROL, XOR self = CLR) 00 o d dddd 0000 oooo 1-address register/memory instructions d = dest+s type: 0=reg/1=mem for destination (and only source) dddd = dest+s: register R0..R15 or memory mode where for memory modes dddd are as above 2-address o oooo operation: space for 31 operations with 0.0001..1.1111 opcodes (0.0000 0-address) SET, INV/NEG, ABS, INC/DEC SHR/ROR/SAR (right), ev RRL/RRR (register 8bit no carry) computed JPC/JSC (also JPC [S++] = RTS) 00 0 o oooo 0000 0000 0-address instructions o oooo operation: space for 32 operations with 0.0000..1.1111 opcodes PSF/PPF flags with 2nd word nn=[P++] 16bit immediate: JPL [P+nn], JPA [nn], JSR [P+nn], JSA [nn], SYS/DLL mod/lib PSM/PPM multiple regs (immed pattern), MVF/ANF/ORF/XRF flags 01 0 0 fffv aaaa aaaa NOP/JMP/BRA jump and conditional branches instructions fff = condition flag: 1/ZorC/MxorO/Zor(MxorO)/Carry/Zero/Overflow/Minus fff=000(1) and val=0 does nothing, is NOP fff=000(1) and val=1 gives unconditional JMP fff<>000 and val=any gives 14 BRA variants v = condition value: 0/1 aaaa aaaa offset: +128..-128 for adding to P, possibly in words if alligned 01 0 1 dddd aaaa aaaa DBN decrement branch nonzero instructions dddd = dest+s: register R0..R15 (direct only, no memory modes) aaaa aaaa offset: +128..-128 for adding to P, possibly in words if alligned