Simple 32Bit RISC Computer
author Neil Franklin, last modification 2000.08.24

Memory Space

4096M Addresses = 1024MWords*4Bytes*8Bits, last 1/16 IO space
  (ev. single go to bit addressing)


Register Set

0..13	general purpose, 13 recommended Stack Pointer
14	Jump And Link Pointer
15	Instruction Pointer (Load=Jump)


Instruction Set

	OAAADDDDEEEEFFFFGGLRRRRRUUUISSSS
O=1	 MWPTTTT	WW
I=1				    CCCC
L=1			   CCCCCCCCCCCCC

	O			Op Class 0=ALU Reg direct/1=Memory Reg indirekt
	 AAA			ALU Operation FFFF AAA SSSS/CC... to DDDD
				  0=OR/1=XOR/2=AND/3=MOV
				  4=ADD/5=SUB/6=TST/7=CMP
	    DDDD		Destination Register 0..15
				  0..D general, E Link/JAL, F Instr/JMP
		EEEE		Execute Conditionally on Reg EEEE
		    FFFF	First Source Register 0..15
	    		GG	Granularity SIMD 0=4*8/1=2*16/2=1*32/3=invalid
			WW	Width Memory Acc 0=Byte/1=Word/2=Long/3=invalid
			  L	Second Source 0=Register/1=long Constant
			   RRRRR	    Rotate before writing to DDDD
				UUU	    unused (deposit/extract?)
				   I	    Scnd Source Type 0=Reg/1=Constant
				    SSSS    Scnd Source Register 0..15
				    CCCC    Scnd Source Const -7..0..7, -8 n W
			   CCCCCCCCCCCCC    Scnd Source Const -4096..0..4095
	 M			Mem Operation 0=Load DDD/1=Store DDD
	  W			Writeback FFFF + SSSS/Const to FFFF
	   P			Pre/Post-add above before/after Mem Access
	    TTTT		Transfer Register 0..15
		EEEEFFFFGGLRRRRRUUUISSSS    rest as for ALU ADD, for address


Virtual Memory Management (Tables in RAM, 2 level, with ATC)

8(U0D+U0I+U1D+U1I+U2D+U2I+SD+SI)Fields*
  1024Segments*1024Pages->1048576Pages * 4kBytes
Table Format: 1024Entries*4Bytes
  bits as: 31..12 pg, 11..4 U2 wx / U1 rwx / U0 rwx, 3..1 mod/acc/pres, 0 cache


Suggested Memory Layout

00000000..EFFFFFFF 3840MBytes Data/Prog/OS RAM
Fs000000..FsFFFFFF 16Slots*16Chips*1MB I/O [s=SlotID=0..F, F=firstCPU]
Fsb00000..FsFFFFFF   Driver ROMs [s=SlotID, b=Begin=F|E|C|8 for 1|2|4|8MB]


Periphery chips

 s000000...s0FFFFF   BIC Control Registers
   00000.....0FFFF     General (def X pin groups, Intr Prio, DMA Prio)
   1x000.....1xFFF     X pin Private Registers [x=Xpin=0..F]
 s100000...s1FFFFF   CPU Control Registers
   00000.....0FFFF     General (Intr Ctrl, Halt, Clk Div/Mul, InstrSet)
   10000.....1FFFF     MMU (on/off, S/U Mode, mapping, ATC ctrl)
   20000.....2FFFF     Cache L0I, L0D, L1, L2 (on/off, lines, flush)
 s200000...s2FFFFF   MEMC Registers (timing, address decoding, refresh)
 s300000...s3FFFFF   FPU (Floating Point Unit) Registers
   00000.....0FFFF     Control Registers
   10000.....1FFFF     Data Registers
   20000.....2FFFF     Command Pseudo-Registers
 sc00000...scFFFFF   IOTC (In/Out/Timer/Counter) Registers [c=Chip=0..F]
   00000.....0FFFF     General (def X pin groups, Intr Prio, DMA Prio)
   1x000.....1xFFF     X pin Private Registers [x=Xpin=0..F]
 sc00000...scFFFFF   DDC (Disk Drive Controller) Registers
 sc00000...scFFFFF   NIC (Network Interface Controller) Registers
 sc00000...scFFFFF   VDG (Video Display Generator) Registers
   00000.....0FFFF     Frame Timing Registers
   10000.....1FFFF     Line Data Format Registers
   20000.....2FFFF     CLUT Registers
 sc00000...scFFFFF   BLIT (BLock Image Transfer) Registers
 sc00000...scFFFFF   SSG (Sound Signal Generator) Registers
 sc00000...scFFFFF   WTG (Wave Table Generator) Registers


Pinout (general)

Pins	IO Function
2	<  VCC+GND
32	<> AD0..31
1	<  -AddrLatch
1	<  Read/-Write
1	<  -ChipSelect
n	<> Functions (-MemWait, I/O, -DMAReq/Ack, -IntrReq, -Reset, Clock)
--	-----
37+n	Total


Pinout Processor (f = full external L2 cache, r = reduced only internal caches)

Pins f	Pins r	IO Function
4	4	<  VCC+GND
32	32	<> AD0..31
1	1	 > -AddrLatch
1	1	 > Read/-Write
1	1	<  -ChipSelect (Control Registers)
1	1	 > -MemAccess
1	1	<  -MemWait
1	1	<  -BusReq
1	1	 > -BusAck
1	1	<  -IntrReq (=JAL-S iiiiiiii, Sysmode)
16	-	<> CID00..07+10..17
2	-	 > -CICS0..1
2	-	 > -CDCS0..1
1	-	 > CRead/-Write
1	1	<  -Reset (=JMP FFFFFFF0, Sysmode, MMU off)
3	3	<> Clock (XTAL 14.31818MHz in, PLL Cap out, PLL Cap in)
--	--	-----
68	43	Total


Pinout BIC Chip

Pins	IO Function
2	<  VCC+GND
32	<> AD0..31
1	<  -AddrLatch
1	<  Read/-Write
4	<  SlotID (no -ChipSelect as BIC is address decoder!)
1	 > -MemWait (for I/O access, never for BIC itsself)
1	<> -BusReq
1	<  -BusAck
1	 > -IntrReq
1	 > -ROMSelect
16	<> -X0..15 (X = -ChipSelect, -MemWait, -DMAReq/Ack, -IntrReq, or IO)
1	<  -Reset
1	<  Clock
--	-----
63	Total


Pinout MEMC Chip

Pins	IO Function
2	<  VCC+GND
32	<> AD0..31
1	<  -AddrLatch
1	<  Read/-Write
1	<  -ChipSelect (Control Registers, not Memory as MEMC is addr decoder)
1	 > -MemWait (for DRAM access time and Refresh delay)
15	 > MA2/9..8/15 (allows 128 word static column), MA16/17..30/31
1	 > -RAS
4	 > -CAS0..3
1	<  -Reset
1	<  Clock
--	-----
60	Total


Bus boards and computer cases Slot arangements

n CPU 1 Chassis 4 6 8 10 12 16
n CPU 2 Chassis 2*4 2*6 2*8