32Bit 32Register Computer - 32bit 3Address Instruction Set
author Neil Franklin, last modification 2011.02.03

design features
  this is an "best of" of mainly SPARC + quite a bit MIPS + some ARM
    with 256register alternative variant + some MMIX or F-CPU
  index from 201101 on, as completely new design, from 16bit l/s, new idea then


MIPS|SPARC-like PC separate from general purpose registers
  no ARM-like R15 as PC, or even worse flags integrated into PC bit31..26

MIPS-like 32reg, no ARM-like 16reg, no SPARC-like regwindows
  unlikely MIPS|SPARC-like R0=const0, use Const=0 for this
  no MIPS|SPARC-like delay slots, hide these with branch target cache
  no ARM-like bit31..28 every instruction conditional
  alternatively MMIX/F-CPU-like 256reg, at cost of constant field size
    or possibly in between as 64reg or 128reg, compromise variants
  alternatively more register bits, but 2 of them used for memory mode
    then code these as 00=direct/01=indirect/10=ind-postincr/11=ind-predecr
    this drops load/store RISC approach, for 32bit getting just 3-addr CISC

SPARC-like 2bit bit31..30 op1, used here for reg/const/largeconst/call formats

SPARC-like "11" for JSR/CALL + 30bit address, only instruction of this class
  into 30bit PC, instr longword alligned, 0-shifted 2bit left for 32bit addr
  SPARC|MIPS-like JSR/CALL as JAL, for maximal leaf node optimisation
    MIPS-like link into R31 (or alternatively into R255, or R127, or R63)

SPARC-like "00"/"01"/"10" for rest + semi-MIPS-like 6bit bit29..24 op2 field
  + MIPS-like 5bit bit23..19 Rd + semi-MIPS-like bit18..0 varying
  the 6bit op2 allows each 64 in all 3 classes, 3*64 most likely far too many
    or only 3*32 op2 with 5bit bit29..25 + 5bit bit24..20 Rd + bit19..0 varying
    or even 3*16 op2 with 4bit bit29..26 + 5bit bit25..21 Rd + bit20..0 varying
      this would allow MIPS-like 6bit op1+op2 + 2*5bit reg + 16bit Const
        that would allow merging 16bit LDHI, but 3*16 may be too few opcodes
  alternatively 256reg with 8bit bit23..16 Rd + bit15..0 varying
    or 128reg with 7bit bit23..17 Rd + bit16..0 varying
    or 64reg with 6bit bit 23..18 Rd + bit17..0 varying

semi-SPRAC-like "00" and "01", both general, but SPARC "i" modebit in bit30
  here called the "c" bit for constant, as not word immediately after instr
    term immediate is reserved for [PC++], if it is even present here
    constant used in Arithmetic/Logic for constant and also in LD/ST for offset
  offers switch between 3addr/3reg and 2addr/2reg+const instructions
    use the Rd = Rs1 <op> Rs2 [ev-shifted] and Rd = Rs1 <op> Const
      with the same set of 64 operations, bit30 is only Rs2/Const select
      could be used for 32 full Arithmetic/Logic set + 8 LD/ST pre/post no/wrb
  for bit30/const = 1: 5bit bit18..14 Rs1 + 14bit bit13..0 Const
    Const is sign extended to 32bit, gives range of 8192..+8191
      use with LDHI of minimally 18bit for loading 32bit constants
    alternatively ARM-like 5bit bit13..9 position + 9bit bit8..0 constant
      no LDHI instruction, but then requires 4 instructions for 32bit
  for bit30/const = 0: 5bit bit18..14 Rs1 + 5bit bit13..9 Rs2
    with 10bit bit9..0 remaining for ARM-like embedded auto-shifting Rs2
      4bit bit9..7 shift op4, bit6 "sc" shift const mode
        for bit6/sc = 1: bit5 unused + 5bit bit4..0 const shift amount
        for bit6/sc = 0: bit5 shiftdir + 5bit bit4..0 Rsa3 shift amount
  alternatively 256reg with 8bit bit15..8 Rs1 + 8bit bit7..0 Rs2 or Const
    in this variant no ARM-like embedded auto-shifting of Rs2
      nor any ARM-like shifted variant of Const instead of LDHI
        and LDHI requires 24bit, too large, must use 2 minimally 12bit LDHIs
    or 128reg with 7bit bit16..10 Rs1 + 10bit bit9..0 Rs2 or Const
      this allows ARM-like 2bit bit9..8 position + 8bit bit7..0 constant
    or 64reg with 6bit bit17..12 Rs1 + 12bit bit11..0 Rs2 or Const
      this allows ARM-like 4bit bit11..8 position + 8bit bit7..0 constant

SPARC-like "10", for LDHI and JMP/BRA, or anything needing an wider Const
  allows 19bit bit18..0 Const, for Arith/Logic/LDHI const or LD/ST/JMP offset
  offers all the 1addr/1reg+const (and also 0-addr/0reg+const) instructions
    LDHI load Rd, JMP ignore Rd, NOP ignore Rd+Const, BRA decide on reading Rd
  possibly BRA not with flags, but semi-MIPS-like BRZ|BRN with register
    but requires compare instruction for <,<=,>=,> stuff (=,<> are SUB|XOR)
      full set would work with SUB and then AND with hex 80000000
  alternatively 256reg with 16bit bit15..0 Const
    or 128reg with 17bit bit16..0 Const
    or 64reg with 18bit bit17..0 Const