16Bit Stack+nRegister Computer - 1+3*5bit 0Address Instruction Set
author Neil Franklin, last modification 2008.10.30


design features

stacks+specialregisters+ALU 16bit data
  0-address system without adressable registers
  data stack for evaluation and call parameters / return values
    hardware stack in CPU, not in memory, wraparound, hidden stack pointer
  return stack separate from this, with push>R and R>pop
    hardware stack in CPU, not in memory, wraparound, hidden stack pointer
  not a pure stack architecture, special purpse registers
    this avoids the typical performance killing stack top thrashing
    1 16bit count register for DJNZ style loops, with >C and C>
      decrement-and-jump, like Z80 and 8048/8051 DJNZ, save separate DEC
        in particular fast block copy, together with auto-postincrement
memory 16bit address
  16bit programm counter, instructions must be alligned to every second address
    all branches (conditional) w 5bit offset, and fitting jump (uncond) variant
  no full 16bit direct/absolute addressing, use 5bit/16bit address on stack
  2 16bit address registers, with >S and S> and >D and D>
    mult reg indirect memory accesses, to prevent slow memory-indirect addr
      and also prevent pure-stack architectures stack thrashing
    address registers with autoincrement, save separate INC/DEC time
      possibly always/only with autoincr, as non-inc addr not used any more
  1 16bit locals base register, addresses with 5bit offset
    unless TOR used for this, gives automatic push, new from malloc
IO space 5bit address
  separate IO space, to not cut off small stuff from large memory
instructions 5bit opcodes
  in 16bit wordwide instr, as highly packed bundle of 1+5+5+5bit or 5+5+5+1bit
    "3 instructions and a bit", 3.2 instructions/bundle
result somewhat similar to Charles Moore Forth stack processors
  but with various register processor things where those are better


registers and stacks

n*16bit ? data stack, implemented with separate TOS register
n*16bit R return stack, possibly implemented with separate TOR
16bit S and D source and destination address registers
16bit C loop counter register (or better use TOR for this)
16bit L locals base/frame pointer (unless TOR used for this, or none)
16bit PC programm counter
1bit F flag(s), are/is 0:C(carry), changed when Arith/Shift op


memory

64k*16bit general purpose program and data memory, word addressed/accessed
  gives 128kByte memory without separate 64k+64k code and data address space
  alternatively 32k*2*8bit memory, byte addressed, possibly auto-ByteSWAP
32*16bit separate IO space, only 5bit constant addressing


instructions

16bit bundles
  0aaaaabbbbbccccc = NOP (rest are 3 5bit instr aaaaa bbbbb and ccccc)
    5bit instr each: 00000 = NOP, 00001..11111 31 other 5bit instructions
  1aaaaaaaaaaaaaaa = CALL (rest is 15bit address for in PC bit15..1)
                          (allows 32kWord/64kByte program memory)
  or possibly reversed as cccccbbbbbaaaaa0 and aaaaaaaaaaaaaaa1
    has advantage of no 1bit shift of Ireg14..0 to PC15..1 needed

5bit instructions
  stack
    DUP DROP SWAP
  arithmetic
    + +carry  (- use NOT + 1 +, -carry use NOT +carry 1 +,
               =CMP use -, <CMP use - 0x8000 AND)
  shift
    /2 /2carry  (*2 use DUP +. *2carry use DUP +carry)
  logic
    NAND XOR  (NOT use DUP NAND, AND use NAND NOT,
               OR use NOT SWAP NOT NAND)
  register
    >S S> >D D> >C C> >L L>  (counter possibly use TOR for DBN(5), no >C C>)
                             (locals possibly also use TOR, no >L L>)
  stack
    >R R>
  const
    LIT(5) L+OFF(5)  (LIT(16) and L+OFF(16) are CALLs with const16 after,
                      LIT(16) contains S> R> >S S@W++ S> >R >S RET)
  memory
    S@++ D!++ BYTE-ROT  (@ use S> S@++, ! use D> D!++,
                         @B use S@++ 0 BYTE-ROT SWAP DROP,
                         !B use ...)
  in/out
    IO@(5) IO!(5)
  control
    NOP HLT INT  (CLI use 0 INT, STI use 1 INT)
  program
    RET JMP(5) BRZ(5) DBN(5) TIMES (CALL is not a 5bit instr)
                                   (JMP|BRZ|DBN(16) are CALL plus const16)