Simple 16Bit RISC Computer author Neil Franklin, last modification 2000.08.24 Memory Space 64k Addresses = 32kWords*2Bytes*8Bits, last 1/16 IO space Register Set 0..5 general purpose, 5 recommended Stack Pointer 6 Jump And Link Pointer 7 Instruction Pointer (Load=Jump) Instruction Set OAAARDDDEFFFISSS O=1 MWPWTTT R=1 D I=1 CCC O Op Class 0=ALU Reg direct/1=Memory Reg indirekt AAA ALU Operation FFF AAA SSS/CCC to DDD 0=OR/1=XOR/2=AND/3=MOV 4=ADD/5=SUB/6=TST/7=CMP R Rotate before writing to DDD, Direction D below DDD Destination Register 0..7 0..5 general, 6 Link/JAL, 7 Instr/JMP E Execute Conditionally on Reg0 = 0 FFF First Source Register 0..7 I Second Source Type 0=Register/1=Constant SSS Second Source Register 0..7 D Direction Rotation Right/Left CCC Second Source Constant -3..0..3, -4 next Word M Mem Operation 0=Load DDD/1=Store DDD W Writeback FFF + SSS/Const to FFF P Pre/Post-add above before/after Mem Access W Width Memory Access 0=Byte/1=Word TTT Transfer Register 0..7 EFFFISSS rest as for ALU ADD, for address Virtual Memory Management (Table in CPU) 2(D+I)or4(UD+UI+SD+DI)Fields*16Pages->256Pages * 4kBytes Table Format: 16Entries*11Bits, bits as: 15..13 rwx, 12..8 software use, 7..0 pageno Virtual Memory Management (Table in RAM, with ATC) 2(D+I)or4(UD+UI+SD+DI)Fields*256Pages->4096Pages * 256Bytes Table Format: 256Entries*2Bytes bits as: 15..4 pageno, 3..1 rwx, 0 cache enable Suggested Memory Layout (Large, 2*64k) b0000..b7FFF 32kBytes Data/Prog/OS RAM (b = both D(=0) or I(=1)) b8000..bBFFF 16kBytes Data/Prog/OS RAM or Prog/OS ROM bC000..bEFFF 12kBytes Data/Prog/OS RAM or Prog/OS ROM 0Fs00..0FsFF 16Slots*8Chips*32Bytes I/O [s=SlotID=0..F, F=CPU] 1Fs00..1FsFF 16Slots*256Bytes Driver ROMs [s=SlotID=0..F, F=CPU] Suggested Memory Layout (Small, 4k) bi000..bi3FF 1kBytes Data RAM (b = both D(=0) or I(=1), i = ignore = 0..F) bi400..bi7FF 1k=32Chips*32Bytes I/O bi800..biFFF 2kBytes Prog/OS/Driver ROM Periphery chips F00....F1F CPU Control Registers 00.....07 General (Intr Ctrl, CPU Halt, Clk Div) 08.....0F Cache (on/off, lines, flush) F20....F3F MEMC Registers 20.....27 General (timing, address decoding, refresh) 28.....2F DMA Address generation (3 or 4 channels) 30.....37 MMU (on/off, S/U mode, mapping, ATC ctrl) F40....F5F Interrupt Handler selection s00....s1F IOTC (In/Out/Timer/Counter) Registers s00....s1F DDC (Disk Drive Controller) Registers s00....s1F NIC (Network Interface Controller) Registers s00....s1F VDG (Video Display Generator) Registers 00.....07 Frame Timing Registers 08.....0F Line Data Format Registers 10.....17 CLUT Registers s00....s1F CPG (Cell Pattern Generator) 00.....07 Control Registers 08.....0F Cell Pattern DRAM (64|256|1024Chars*8Lines*8Bits) s00....s1F ODG (Oscilloscope Display Generator) Registers Pinout (general) Pins IO Function 2 < VCC+GND 16 <> AD0..15 1 > -AddrLatch 1 < Read/-Write 1 < -ChipSelect n <> Functions (-MemWait, I/O, -DMAReq/Ack, -IntrReq, -Reset, Clock) -- ----- 22+n Total Pinout Processor (n = normal version, e = MMU extended version) Pins n Pins e IO Function 2 2 < VCC+GND 16 16 <> AD0..15 1 4 > A16..19 (n: A16=Instr/-Data) 1 1 > -AddrLatch 1 1 > Read/-Write 1 1 < -ChipSel (Control Registers) 1 1 > -MemAccess 1 1 < -MemWait 1 1 < -BusReq 1 1 > -BusAck 1 1 < -IntrReq (=JAL-S 1FFE0) 1 1 < -Reset (=JMP 1FFF0) 1 1 < Clock (XTAL 14.31818MHz) -- -- ----- 29 32 Total Pinout MEMC Chip (n = normal version, e = MMU extended version) Pins n Pins e IO Function 2 2 < VCC+GND 16 16 <> AD0..15 - 4 < A16..19 1 1 < -AddrLatch 1 1 < Read/-Write 1 1 < -ChipSelect (Control Regs, not Memory, MEMC is addr decoder) 1 1 > -MemWait (for DRAM access time and Refresh delay) 8 10 > MA0/4..3/7 (allow 16 word static column), MA8/9..14/15|18/19 1 1 > -RAS 4 4 > -CAS0..3 1 1 < -Reset 1 1 < Clock -- -- ----- 37 43 Total Bus boards and computer cases Slot arangements 1 CPU = 1 Chassis 4 6 8 10 12 16 2 CPU = 2 Chassis 8(5+3) 10(7+3) 10(6+4) 12(7+5) 16(8+8) 3 CPU = 3 Chassis 10(6+2+2) 10(4+3+3) 12(6+3+3) 16 (8+4+4)