16Bit 16Register Computer - 16bit 2Address Instruction Set author Neil Franklin, last modification 2009.02.04 design features registers+ALU 16bit data 2-address system without dedicated accumulator/temporary 2-operand direct on 16 regs and regindirekt on memory, like in PDP-11 not only reg+mem/reg as in 8086, not only reg+reg as in AVR operations only full 16bit, saves 8/16bit switch instruction bits/space 8bit (only use for packed chars) handled by 8bit rotating decrement-and-jump, like Z80 and 8048/8051 DJNZ, save separate DEC time in particular fast block copy, together with auto-postincrement strictly also possible design for 32bit (or even 64bit) computer memory 16bit address, word addressed 16bit programm counter all branches (conditional) w 8bit offset, like 6800/6802 6809 6502 and fitting also jump (uncondit) variant w 8bit offset, like 6809 8086 only register based addressing, full 16bit full 16bit stack pointer, not 8bit part-of-memory stack stack pointer one of general purpose registers, for more flexible PUSH/POP 3 16bit address register pairs to prevent slow memory-indirect addressing, unlike 6800/6802 or 6502 but can double as normal data registers, not only-16bit like 6809 mult registers indirect memory accesses, like in 8048/8051 and 6809 but with full 16bit addresses unlike 8048/8051, like in 6809 address registers with autoincrement/decrement, save separate INX/DEX time like in 6809 registers, and in Z80 LD[ID]/CP[ID], but no LD[ID]R/CP[ID]R stack and 1 address register 16bit index addressing IO space 16bit address separate IO space, to not cut off small stuff from large memory Instructions 16bit opcodes, must be word alligned, no bit addresses if 32bit (or even 64bit) computer, then word as instruction bundle requires "byte" addressbits extension of program counter jump simply sets these to 0, can only jump to begin of an bundle undecided how to handle these when call/return, mult calls in one bundle in 32bit possibly require call always be 2*16bit and 32bit alligned in 64bit unlikely require call always be 64bit alligned hex friendly 4+4+4+4bit format instr, not n*(2+3+3)bit or even worse format op+destreg/op+const/op+sourcereg/const/op usage of fields result 8bit_16Reg_16bit_2Addr expanded to pure 16bit, no 8086/8088 w(width) bit no rearranging of opcodes for gaining space for the w(width) selection bit just adding 16bit Immediate mode for 16bit constants (only 8bit in instr) registers 16bit R0..R11 general purpose registers 16bit R12..R15 address+stackpointer registers X=R12 Y=R13 Z=R14 S=R15, also usable as general purpose registers alternatively R8..R15 usable as address+stackpointer registers 16bit P program counter, dedicated, not in arithmetic 8bit F flags status flags are: 7:Minus 6:Overflow 1:Zero 0:Carry changed when Arith/Shift all MOZC, Logic/Load only MZ control flags are: 5:ProcReset 4:ProcHalt 3:IntReqest 2:IntEnable setting IntEnable has an automatic 1-cycle delay, allows using PPF or ORF #$04; *locked*; RTS; *unlocked* for return from interrupt setting ProcHalt halts the processor until interrupt or reset is applied memory 64k*16bit general purpose program and data memory, word addressed alternatively 32k*2*8bit memory, byte addressed, possibly auto-ByteSWAP or 4G*32bit, word addressed, if 32bit computer alternatively 1G*4*8bit memory, byte addressed, possibly auto-ByteROT 64k*16bit separate IO space, only immediate addressing instructions oo o o dddd cccc cccc 16bitregister+8bitconstant instructions oo o o = operation: 0000..0011 used for 2-address instructions 0100 used for NOP/JMP/BRA jump and conditional branches instructions 0101 used for DBN decrement branch nonzero instructions space for 10 operations with 0110..1111 opcodes MOV, AND/IOR/XOR, ADD/ADC, CMP/CPC no SUB/SBC (use ADD/ADC negval) ev LDHI for building 8+8=16bitconst (also MOV 0 = CLR, MOV -1 = SET, XOR -1 = INV, ADD 1 = INC, ADD -1 = DEC) dddd = dest+s1: register R0..R15 for destination (and first source) all of these only work on registers, not on memory cccc cccc = source2 const: 8bit constant/immediate second source no 16bit const, upper 8 bits from aux upper register, loadable with LDHI or LDHI high 8bit to any register, then AND/OR low 8bit, then 2-address or for this use 1-address format with 2nd word 16bit immediate 00 s d dddd oooo ssss 2-address instructions s = source2 type: 0=reg/1=mem for second source d = dest+s1 type: 0=reg/1=mem for destination and first source dddd = dest+s1: register R0..R15 or memory mode ssss = source2: register R0..R15 or memory mode where for memory modes dddd and ssss are format rrmm (reg+mode) X/X++/--X/??, Y/Y++/--Y/??, Z/Z++/--Z/??, S/S++/--S/?? the ?? are special cases, [nn]/IO[nn]/[Z+nn]/[S+nn] alternatively memory dddd and ssss are format rrrm (reg+mode) allows more registers R8..15, but only Rn/Rn++ or --Rn/Rn++ with Rn/Rn++ need special case stack dddd/writing/pushing S/--S or even 5|4 regs Rn/Rn++ and 2|3 regs and stack Rn/--Rn with --Rn/Rn++ need special case stack dddd/writing/modding --S/S or even 6|5 regs --Rn/Rn++ and 1|2 regs and stack --Rn/Rn with 1 register (R8) replaced by the 2 special cases [nn]/IO[nn] oooo = operation: space for 15 operations with 0001..1111 opcodes (0000 1-address) MOV, AND/IOR/XOR, ADD/ADC/SUB/SBC, CMP/CPC, TST ev multibitRO*/SH*, ev 2-reg byteROT, ev XCG (semaphores!), ev MUL/MAC (also ADD self = SHL, ADC self = ROL, XOR self = CLR) 00 o d dddd 0000 oooo 1-address instructions d = dest+s type: 0=reg/1=mem for destination (and only source) dddd = dest+s: register R0..R15 or memory mode where for memory modes dddd are as above 2-address o oooo operation: space for 31 operations with 0.0001..1.1111 opcodes (0.0000 1-address) SET, INV/NEG, SEX/ABS, INC/DEC SHR/ROR/SAR (right), ev RRL/RRR (register 16bit no carry) ByteSWAP/ByteLOW/ByteHIGH computed JPC/JSC (also JPC [S++] = RTS) with 2nd word nn=[P++] immediate for 16bitregister+16bitconstant: any of 2-address instructions, but with immediate as source2 00 0 o oooo 0000 0000 0-address instructions o oooo operation: space for 32 operations with 0.0000..1.1111 opcodes PSF/PPF flags with 2nd word nn=[P++] 16bit immediate: JPL [P+nn], JPA [nn], JSR [P+nn], JSA [nn], SYS/DLL mod/lib PSM/PPM multiple regs (immed pattern), MVF/ANF/ORF/XRF flags 01 0 0 fffv aaaa aaaa NOP/JMP/BRA jump and conditional branches instructions fff = condition flag: 1/ZorC/MxorO/Zor(MxorO)/Carry/Zero/Overflow/Minus fff=000(1) and val=0 does nothing, is NOP fff=000(1) and val=1 gives unconditional JMP fff<>000 and val=any gives 14 BRA variants v = condition value: 0/1 aaaa aaaa offset: +128..-128 for adding to P, in words as always alligned 01 0 1 dddd aaaa aaaa DBN decrement branch nonzero instructions dddd = dest+s: register R0..R15 (direct only, no memory modes) aaaa aaaa offset: +128..-128 for adding to P, in words as always alligned