http://neil.franklin.ch/Projects/PDP-10/Logfile - things done and to do author Neil Franklin, last modification see last entry near bottom 1981.11.xx my first use of a computer, Z80 microprocessor based, Pascal and Assembler http://neil.franklin.ch/Computers/index.html http://neil.franklin.ch/Projects/index.html mid to late 198x.xx.xx designed data path for an 32bit Forth CPU using 74LSxx(x) TTL logic failled at control circuits due to not knowing enough about logic design did not even know about finite state machines in those days later 198x.xx.xx read about PALs in magazines, MMI 16R8/20R8, AMD 22V10 plans to do an CPU in an PAL, but even MMI 64R32 was too small, too few FFs did not know bitslice technique in those days, nor idea of external registers was too taken in from the idea of a single chip CPU, microprocessor later 198x.xx.xx recieved Jargon File on floppy, read about TMRC/MIT-AI hacker culture read about PDP-1, PDP-6 and PDP-10, impact in hackers, ITS development 1990.01.xx saw first time Xilinx chips in magazines, looked like a great thing but could not afford the $5000 development tools as just ex-student 1991.09.xx saw Algotronix CAL1024 PC/AT card, but had just got new non-PC (NeXT) computer so I went a different career in programming, Unix, sysadmining digital electronics, particularly processors, staid an hobby interest mid 199x.xx.xx one session on Usenet at local university, discovered alt.folklore.computers 1997.11.xx got onto Usenet from my home Internet connection 1997.12.10 Wed subscribed to alt.folklore.computers, as 2nd newsgroup, oldest still going 1997.12.17 Wed thread on PDP-10s Daniel A. Seagraves muses on emulating an 10 http://neil.franklin.ch/Usenet/alt.folklore.computers/19971208_Curious_about_10s G. Herrmannsfeldt mentions a FPGA project that turns out to be an -8 also has a discussion about DECtape file system format and claim that someone still has an KA-10/KI-10 TOPS-10 that fits one DECtape 1999.07.02 Fri Communa/Lisard mentions putting Forth into hardware, simple enough for FPGAs http://neil.franklin.ch/Usenet/alt.folklore.computers/19990630_CPU_s_directly_executing_HLL_s Paul Wallich mentiones Alto only 1600 gates, would go in an FPGA 1999.07.07 Wed Jan Gray carries on speculations of implementing Xerox Alto in an FPGA http://neil.franklin.ch/Usenet/alt.folklore.computers/19990707_Alto_in_an_FPGA 1999.09.20 Mon downloaded PDP-8 and PDP-10 instruction descriptions from http://www.cs.uiowa.edu/~jones/pdp8/man/ http://www.inwap.com/pdp10/opcodes.html http://www.inwap.com/pdp10/hbaker/pdp-10/pdp-10.html 2000.xx.xx sketched out instruction set, MMU, pinouts, bus structure and periphery ARM/MIPS-ish 16bit and 32bit load-store style RISC processors and computers http://neil.franklin.ch/Projects/16bit_RISC_Computer http://neil.franklin.ch/Projects/32bit_RISC_Computer later added an 16bit PDP-4/7/9/15 style system http://neil.franklin.ch/Projects/16bit_Accu_Computer 2000.07.29 Sat LUGS grill party discussion with U Schuetz about old systems he mentions an unused rack sized PDP-11 available at ex Job (PMODWRC) says he will make contact from me with ex Boss 2000.08.08 Tue Mail from H Roth about "PDP-11", turns out to be 2 PDP-8/A leads to me doing search for info on 8s 2000.08.12 Sat as part of above I subscribe to alt.sys.pdp8 and also .pdp10 and .pdp11 2000.08.19 Sat D G Conroy announces PDP-8/X implemented in an XCS10 FPGA http://neil.franklin.ch/Usenet/alt.sys.pdp8/20000819_something_for_everyone_s_amusement Actual website is http://surfin.spies.com/~dgc/pdp8x/ Ben Franchuk mentiones above project http://neil.franklin.ch/Usenet/alt.folklore.computers/20000819_Naked_computers discussion that Blinkenlights are really neccessary my interest in doing an CPU myself with programmable logic rewoke 2000.08.21 Mon J Gray pointer to www.fpgcpu.org, many pages on techniques http://neil.franklin.ch/Usenet/alt.sys.pdp8/20000820_pdp8x_fpga_code_and_front_panels stuff on his XR16 CPU and SoC designs http://www.fpgacpu.org/xsoc/index.html 2000.08.23 Wed visit to H Roth, PDP-8/A are octal console type, like PDP-11/34 no binary front panel, no historic value for front panel, not what I want but via Usenet found homes for both of them http://neil.franklin.ch/Usenet/alt.sys.pdp8/20000920_Want_new_home_2_PDP8_A_2_Calcomp_836_1_Centronics_6085 2000.08.26 Sat - 2000.09.08 Fri Autumn holiday, offline, did thinking on programmable logic recalling PAL details of AND arrays, fixed ORs, macrocells remember Xilinx called many times 5L2 PAL, sketched ideas how this could work failled to come up with solution for routing signals past an logic element had never heard of PIPs, dominating FPGA chips, with CLBs embedded in them 2000.09.09 Sat looked at boards used by J Gray for XR16 XS40-010E+ (XC4010E) http://www.xess.com/prod018.html also XSV (XCV50-800) http://www.xess.com/prod014.html start looking at CPLD and FPGA vendor data sheets 2000.09.09 Xilinx, 2000.09.13 Altera, 2000.09.27 Atmel, 2000.10.22 Cypress Lucent too complicated, Gatefield&Quicklogic no data sheets Actel&Lattice websites fail (A wants JavaScript&Flash, L tons of my data) 2000.09.17 Sun shape and size of the CLBs and BRAMs http://neil.franklin.ch/Usenet/comp.arch.fpga/20000917_virtex_shape 2000.09.20 Wed visit gEDA (GPL Electronic Design Automation) web site 2000.09.21 Thu T Sailer mail about how to get into FPGA programming they at ee.ethz.ch use Synopsys on Xilinx, suggests Spartan-II or Virtex claims that TQFP is hand solderable, if I want to make own board 2000.09.23 Sat subscribe to comp.arch.fpga 2000.09.27 Wed visit Optimagic, for boards list 2000.10.01 Sun my first alt.sys.pdp10 thread discussing implementing an 10 in an FPGA http://neil.franklin.ch/Usenet/alt.sys.pdp10/20001001_PDP_10_in_an_FPGA_chip B Franchuk does FPGAs, uses Altera but claims OTP (?, Actel?) links on his website show he uses BurchED boards with Altera chips http://www.jetnet.ab.ca/users/bfranchuk/luna/right6.html BurchED http://www.jetnet.ab.ca/users/bfranchuk/luna/right2.html Altera 2000.10.05 Thu Discussion about open source tools, no back ends, secret bitstreams http://neil.franklin.ch/Usenet/comp.arch.fpga/20001002_Amplify_experience vendor tools only for WindowsNT/Solaris, ev also for HP-UX/AIX must use Win tools under Wine http://www.polybus.com/xilinx_on_linux.html got tip that one should do "one hot" FSMs in FPGAs, and synchronous logic also suggestion to go with an pre-built prototyping board mentioning of gEDA free VHDL and Verilog simulators and synthesisers but all are only down to EDIF or XNF, then vendor back end tools take over also story of Neocad, company that reversed engineered a Xilinx chip pointed out reverse engineering is explicitely protected in some countries 2000.10.07 Sat Guccione List of FPGA-based Computing Machines, XKL/Toad-1 is 2 * XC4010E-3 http://www.io.com/~guccione/HW_list.html 2000.10.17 Tue Discusion about using FPGAs for cloning old CPUs http://neil.franklin.ch/Usenet/alt.folklore.computers/20001017_FPGAs_for_old_CPUs I ask about programming languages VHDL vs Verilog http://neil.franklin.ch/Usenet/comp.arch.fpga/20001017_VHDL_vs_Verilog from reading courseware on a web site I don't like either of them possibly try cnets or PamDC, both C++ based instantiation of FPGA elements 2000.10.18 Wed L Brinkhoff pdp10.nocrew.org PDP-10 processor features comparison http://neil.franklin.ch/Usenet/alt.sys.pdp10/20001016_PDP_10_processor_features also discusses his plans to port gcc, binutils, Linux to PDP-10 also source for ITS (kernel only) and links to other ITS page also list of PDP-10 emulators, all unfinished and not available 2000.10.22 Sun APS http://www.associatedpro.com/ look at Virtex boards V240 (XCV50-800) http://www.associatedpro.com/v240.html VCC http://www.vcc.com/ fairly expensive XCV but with BGA, many pins Virtual Workbench http://www.vcc.com/vw.html 2000.10.24 Tue BurchED http://www.burched.com.au/ very cheap XC4010 board BED-XILINX-4000+ http://www.burched.com.au/bedxilinx4000.html 2000.10.30 Mon visited cnets web site 2000.11.01 Wed L Brinkhoff announces he is porting gcc to TOPS-20, is getting payed by XKL http://neil.franklin.ch/Usenet/alt.sys.pdp10/20001101_Planned_gcc_gdb_gas_port_to_PDP_10 question about JBits, I visit JBits site, is pure Java tool also works on instantiation of FPGA elements, will it work on Linux? http://neil.franklin.ch/Usenet/comp.arch.fpga/20001101_JBits http://www.xilinx.com/products/software/jbits/index.htm 2000.11.02 Thu downloaded historic XKL prospects http://www.inwap.com/pdp10/td-1a.html http://www.inwap.com/pdp10/td-1b.html 2000.11.12 Sun sketched XC40-010E pinout, to see what pins are free, this last update http://neil.franklin.ch/Projects/PDP-10/XC40-010E-Pinout looks like there are too few pins on PLCC84 ask Xilinx if JBits will work on Linux, yes it does, is used, but no support so that decides tool (JBits) and chip family (Virtex/Spartan-II) Virtex data sheet http://www.xilinx.com/partinfo/ds003.pdf weaknesses seem to be: array wide, not high (XC4020 56x28 vs XCV50 32x48) TBUFs/BUFTs only 2 out 1 in per 4 LUTs, not 4 and 4, can be circumvented Spartan-II are architecturally Virtex, same bit stream, same tools http://neil.franklin.ch/Usenet/comp.arch.fpga/20000829_Spartan_II_vs_Virtex 2000.11.26 Sun sketched XSV and APS-V240 pinouts, to see what pins are free this date is actually last update, not recorded first date http://neil.franklin.ch/Projects/PDP-10/APS-V240-Pinout more free, ZBT RAM 18bit, better http://neil.franklin.ch/Projects/PDP-10/XSV-Pinout right RAM unusable, left only 16bit 2000.11.29 Wed JBits 2.4 installed, read ReadMe, Virtex architecture guide, JBits tutorial 2000.12.01 Fri E Smith I know from a.f.c and a.s.p10 asking about JBits http://neil.franklin.ch/Usenet/comp.arch.fpga/20001128_Virtex_ROM_ques in my Answer announced plans for some historic CPU cloning PM discussing cloning, Cypress, present plans (8->11->10) may actually drop 11, as complex instruction set and no help for 10 2000.12.04 Mon KA/KI can boot from console paper tape reader, good for clone (from PC RS232) http://neil.franklin.ch/Usenet/alt.sys.pdp10/20001204_Do_KS10_support_card_punch_reader 2000.12.14 Thu alt.sys.pdp10 pointer to Gorin XKL architecture book, excellent to be found at ftp://toad.xkl.com/ARCH-PART[1-5].PS.1 for download reading them I found out that (X)KL microcode has lead to complex instructions things like EDIT, no wonder the KL has been nicknamed KL-udge looks like I will do an KI with IBM 360/44|95 style trap+emulate for KL/XKL call this EmulateUUO, possibly also FP and VM in EUUO like i386, i486SX also possibly console and (some) IO devices in EUUO, like i386SL SMI mode 2000.12.19 Tue started re-read of Java programming language book, for using JBits Xilinx Mail announce of JBits 2.5 BurchED announce of BED-SPARTAN2+ and BED-FPGA-CPU-IO http://neil.franklin.ch/Usenet/comp.arch.fpga/20001219_FPGA_and_Board_for_Microprocessor_Design BED-SPARTAN2+ http://www.burched.com.au/bedspartan2.html BED-FPGA-CPU-IO http://www.burched.com.au/bedfpgacpuio.html Uses XC2S200, is 2/3 XCV300, but 1/6 price of APS V240-XCV200 board 2000.12.22 Fri web search SRAMs IDT, Hitachi, Micron, Motorola, Samsung ZBT only TQFP and BGA, Sync/Burst PLCC and TQFP, only Async in DIPs 2000.12.23 Sat JBits 2.5 installed, further reading of release notes, JBits history 2000.12.24 Sun BED-SPARTAN2+ only place for DIP8 config PROM (17xx?), I want EEPROM, Atmel? but their AT17C020 is also PLCC22, do own socket, use Xilinx XC18V02 PLCC44 2MBit - XC2S200 1.33MBit = >20.5kword*36 for EUUO and boot code 2000.12.25 Mon one can generate null bit file also by readback and running MakeNullBs in tools http://neil.franklin.ch/Usenet/comp.arch.fpga/20001223_Question_about_programming_xcv100 so I will be working in DeviceSimulator with XCV300 until I get a board then switching to what I have downloaded from that board mainly this means any chip size restrictions on board selection have gone 2000.12.30 Sat alt.sys.pdp10 "implement 10 in FPGA" question post, second in 3 months I will reply to it, but first get my docs up to standards needed while thinking over it in bed, decision to go direct for 10, no 8 or 11 first 11 complex instruction set and no real use (got Supnik simulator for Unix) 8 no real use (got no software for it and no real stepping stone for 10) go directly for an 10, historic good and extended is usable as daily system will make it as an full open source project, all code and docu life on line should start by documenting what has been done, as log+todo file 2000.12.31 Sun unsubscribed alt.sys.pdp8|11 as interest is going direction of cloning an 10 opened up URL for PDP-10 project http://neil.franklin.ch/Projects/PDP-10/ start this log file, retroactively log all the done stuff searching for first PDP-8/X post, found in a.f.c 2000.05.03 emulator tread http://neil.franklin.ch/Usenet/alt.folklore.computers/20000503_PDP_10_Emulator posted announce of this project, as followup to 2000.12.30 question http://neil.franklin.ch/Usenet/alt.sys.pdp10/20001231_PDP_10_in_an_FPGA_chip_starting read Xilinx XAPP138/139/151 on Virtex configuration architecture CLBs are 18x48bits, LUT FF and BRAMdata positions are known 2001.01.01 Mon D G Conroy suggests microcode decoding by 512-way dispatch into 16k ctrl store is the same technique as used in Z80emu Z80 emulator for 8088 PCs fits nicely in XCV200 or XC2S200 leaving 20.5kword of 2Mbit EEPROM left over 16kword for ucode, 4.5kword for booting or ucode "breakouts" if 32kword of RAM is reserved for EUUO mode, that leaves 11.5kword for data but external microcode is slow as it has to be retrieved into chip 2001.01.02 Tue further re-read of Java book syntax chapter and applications chapter repeat went through JBits tutorial, lessons 1 and 2 (started), doing exercises for this copies null300.bit and JBitsHelloWorld.java javac JBitsHelloWorld.java, does not find com.xilinx.JBits.Virtex.* wrong CLASSPATH ~neil/src/JBits2.4, not /usr/local/JBits2.5, set right, OK java JBitsHelloWorld -XCV300 null300.bit JBitsHelloWorld.bit can't find com/xilinx/demo/JBitsHelloWorld, killed "package" line in source 2001.01.03 Wed repeat JBits tutorial, lesson 2 (continued) and 3 and 4 discovered that it says that direct lines only run E-W, not N-S the S[01][FG][1-4] "PIP Muxes" also only have constants for this discovered that the "Single" class is actually deprecated in the class list 4 separate classes for different connection types downloaded PDP-6 166 Processor schematic print set http://www.ai.mit.edu/people/tk/pdp6/pdp6-schematics.ps will not display in gv, gives error messages for each page content is a series of 80 PostScript files bp.0001.ps to bp.0080.ps unpacked first 4, gv one of them, it hangs without error message 2001.01.04 Thu test printed first 4 schematics, go OK, to fine resolution for on screen unpacked all 80 schematics to separate .ps, made .tar.gz for upload make graph of Virtex CLB routing PIPs layout, which ones exist http://neil.franklin.ch/Projects/PDP-10/Virtex-CLB-PIPs output muxes done, begin with input muxes idea alternate EUUO implementation BRAMs 1k*4*9 code, 512*8*2 dispatch table this would lose BRAMs for cache, but no problem with todays RAMs until 100MHz while no external RAM and BRAMs for code, only use part each 2001.01.07 Sun continued graph of Virtex CLB routing PIPs layout input muxes finished from single/direct/gclk, no hex lines rearranged output behind input, not below, in same diagram 2001.01.10 Wed continued graph of Virtex CLB routing PIPs layout out to single muxes, tidyed up direct feedback thoughts about single to single arrangement looked again at XC5200 docu picture, detailled routing on page 15 of 73 http://www.xilinx.com/partinfo/5200.pdf reread Virtex routing docu reworked some of the older entries in this file some reading in ftp://toad.xkl.com/ARCH-PART1.PS.1, 1 up to KS-10 2001.01.11 Thu read PDP-10/TOPS-20 user experience paper from Frank da Cruz http://www.columbia.edu/kermit/dec20.html 2001.01.12 Fri looking for web picture of KI-10 front pannel I remember seeing, re-found it http://www.ultranet.com/~crfriend/museum/machines/KI-10.html further reading in ftp://toad.xkl.com/ARCH-PART1.PS.1, rest 2001.01.13 Sat reading on PDP-10 user instruction set http://www.inwap.com/pdp10/hbaker/pdp-10/pdp-10.html ftp://toad.xkl.com/ARCH-PART2.PS.1 noticed that 100ffffmm (ffff=function, mm=mode) instr SETx/ANDx/ORx/XOR/EQV can be implemented as one 4MUX per bit with instr bits 3-6 as inputs and 2 data bits as select 4MUX is 6-input, one CLB per bit, total 2x18 CLBs datapath and on TOAD-1 architecture in ARCH-PART3.PS.1 2001.01.17 Wed reading on PDP-10 architecture in ARCH-PART4.PS.1, up to KS-10 this project got mentioned on Slashdot, web server got a bit of work http://slashdot.org/article.pl?sid=01/01/17/1315253&mode=thread one reader suggests it is a 2 month project, gets shot down as unrealistic 2001.01.19 Fri Kolja Sulimma mail, offer to use their development board they are making also claims that TQFP chips are hand-solderable, so it seems to be true 2001.01.20 Sat for post about display widths 72 vs 80 char looked up VT05 specs http://neil.franklin.ch/Usenet/alt.folklore.computers/20010116_HELP saw it needs 2240 (64x7x5) bits char set ROM -> 1 BRAM for 64x8x8 and 9816?? (72x20x6) bits refresh buffer -> 3 BRAMs for 2048x6 reading on PDP-10 architecture, ARCH-PART4.PS.1 and ARCH-PART5.PS.1a discovered that KI-10 hat 4 register sets, oposed to KL-10 8 and KA-10 1 ideal for implementing as one CLB per bit, 2x18 CLB array total and gets around the Virtex lack of TBUF inputs problem downloaded Manuals from Eric Smith http://www.36bit.org/dec/manual/ek-1080u-sd-003.pdf System Description http://www.36bit.org/dec/manual/ad-h391a-t1.pdf Processor Reference read the System Description manual, nice overview paged through the Processor Reference, base text for ARCH-PART*.PS.1 but has the KI-10 and KA-10 console operations appendix 2001.01.23 Tue studied PDP-10 instruction table and KI-10 console operation from P Ref manual 2001.01.24 Wed made 00README file, tried to reconfigure server to display it first, failled made 0FAQ file, initially based on Usenet announce thread questions and personal mails triggered from that and from Slashdot post entered opcodes on instruction table, is incomplete, at least UUOs are missing while thinking over it in bed, decided that first hardware coding will be logic unit for 100ffffmm instr, 4x16x36 register set (using only set 0), AD IR, AR, instruction decoder for bits 3-6,9-12,32-35 for case of bits[0-2]=4 separate 4x16 word instruction memory with bits 30-35 of PC to drive it first addition will then be inserting the registers set into address space then doing full E effective address calculations then add further instructions, more complete instruction decoder 2001.01.25 Thu read Processor Reference, looking out for what instructions are in KI-10 also operators console and indicator pannels description for KI-10 2001.01.26 Fri read operators console and indicator pannels description for KA-10 2001.01.27 Sat - 2001.02.03 Sat was on holiday skiing, offline, but did a bit of planning work operators console and indicator pannels implementation using 74LS245s for all LEDs and 1/2 7400s for each button FF is lots of work use an separate XC2S50 for all LED and button connections is less parts but it needs custom board with TQFP layouting, more software use an grid of LEDS with transistors, like memory chips do just one shift register for bits and line selector for which to drive for buttons use same line selectors, load 2nd set of shift registers updating display on every machine cycle will give RFI problems so better update chip-internal registers fast and without RFI danger and slowly output them to LEDs like output from an video card to monitor console terminal use same key scanning method, mechanisms from old PC board but this requires making own wiring, better use unchanged keyboard convert PC key status codes, not scanned in key positions, BRAM table idea of making an CLB/LUTdata/BRAM/BRAMdata dump/modify bits2ASCII program based on XAPP151, with support for typical ROM/RAM data distribution patterns what disk to emulate and with what hardware, RP04 is about 100M, RP06 double use parallel port ZIP drive, may not fit if 512kWord->4kByte (3/8 loss) also slow drive, also if multiple drives wanted, use lots of space/cost better use an EIDE or SCSI drive and emulate multiple RP06es or even RP20s implementing EIDE or SCSI bus will be most difficult part of project at least all the hard analog stuff is done in the drives controller 2001.02.04 Sun morning in bed further musing on console display scanning display method suggest not using LEDs but use an monitor, no wiring this allows anyone to have operators console this suggests going with commercial prototype board, not university made one as they will not want to make 10s or 100s of board part sets because of console terminal also monitor save space with only one monitor make console display at bottom, VT05/indicators/both switchable at top continued graph of Virtex CLB routing PIPs layout added JBits code used for setting the different groups of PIPs found bug in direct east/west connections, 0/1 go west, not east, 6/7 go east reversed OUT0..OUT7 to OUT7..OUT0, reversed OUT_TO_SINGLE PIPs at same time reversed S[01]_[XY] lines, left counting up, right count down further bug in junction for going to east, lower line should be longer one while on bugs, I found one in the JBits docs, OUT_EAST5 instead of OUT_EAST6 mailed Xilinx about it, also Tutorial VAG and JBits improvement suggestions added SingleToSingle PIPs to diagram while I had XAPP151 open reread it for making dump/modify program, also XAPP138 2001.02.06 Tue Xilinx Answer to mail, is OUT_EAST6, suggest using JRoute2, not PIPs by hand 2001.02.07 Wed went through alt.sys.pdp10 news server looking for KLAD posts, put them on web http://neil.franklin.ch/Usenet/alt.sys.pdp10/20001216_KLAD_Sources_now_in_PDP_10_archive 2001.02.10 Sat looked at JBits JRoute and JRoute2 docs for a second time not much intro, will need direct analysis of JavaDocs reference manual 2001.02.11 Sun big Usenet post on implementation, board usage, FPGA questions http://neil.franklin.ch/Usenet/alt.sys.pdp10/20010211_warning_long_post 2001.02.14 Wed started reread decsystem 1080/1090 System Description 2001.02.17 Sat thinking on naming, so far still nothing that really strikes me NF-10 (Neil Franklin's 10, like TS-10), KC-10 (Clone, but KC was for Jupiter) C-10 (Clone, like E-10 Emulator), KF-10 (FPGA or Franklin) PT-10 (Personal Ten, but that duplicates 10), PC-10 (Personal Computer 10) 2001.02.18 Sun made braindump of hardware ideas http://neil.franklin.ch/Projects/PDP-10/Hardware further reading System Description reread "Tony in RH20 Land", although not KI-10 relevant it is still fun 2001.02.20 Tue mentioned the clone in an C64, emulator and FPGA discussion in other news group http://neil.franklin.ch/Usenet/alt.ascii-art/20010216_OT_Spamfighting read Origins and Development of TOPS-20 http://www.opost.com/dlm/tenex/hbook.html downloaded TOPS-10 Operator's Guide 7.03 http://www.36bit.org/dec/manual/aa-h283b-tb.pdf Operator's Guide 7 2001.02.21 Wed looked at Virtex/JBits docs corrections: exchanges W and E in all input lines, redone SingleToSingle added Tristate buffers and lines, do not yet completely comprehend Tbufs may try an design entirely based on Muxes, as the PDP-6 seems to have been 2001.02.23 Fri read first 2 chapters of TOPS-10 7.03 Operator's Guide 2001.02.24 Sat first explorative JBits coding http://neil.franklin.ch/Projects/PDP-10/src/ derived from JBits Tutorial examples, compiles and runs BoardScope crashes X server, lack of memory, Java bloat, increase swap space found another JBits docu bug doc/BoardScope/BoardScope.html com.xilinx.XHWIF.XHWIFException: XHWIFWithEvents reference not created. Invalid system name: - - -> -simulator:xcv300 encoded general layout algorithm (each unit has an offset) 32 word memory (18x2 CLBs), 100ffffmm boolean logic unit (18x2 CLBs) AD temp register Mux, PC increment/reload Mux and increment adder 2001.02.25 Sun redesigned layout algorithm, so sections don't need to know neighbor section Dev ( Proc ( Data ( Logic Temp Instr Prog Mem ) Ctrl ( ) ) ) bug in 100ffffmm boolean logic, table reversed, corrected it reworked 100ffffmm to use only 1 slice per bit, F/G as 2:1-Muxes and F5 Mux found another JBits docu bug doc/VirtexArchitecture/Slice_Internals.html D: Controlled by same mem cells as D -> as R also questions which inputs and output of RAM_32x1 and DUAL_MODE also questions which inputs control writing to LUTs also questions about Tbufs, 2nd Mail to jbits@xilinx.com reading Virtex docs, discovered V/H Longlines and reading JBits they have TBufs, but not run-time switchable ones 2001.02.27 Tue read chapter 3-13 of TOPS-10 7.03 Operator's Guide 2001.02.28 Wed read rest of TOPS-10 7.03 Operator's Guide 2001.03.04 Sun started analysing time states for control state machine http://neil.franklin.ch/Projects/PDP-10/Time-States 2001.03.06 Tue further work on the time states designing for first part implementation discovered that same as FSM->OneHot, also Mux->Bus&Enables(=AND&wideOR) original data path design will need reworking for this type of Muxes ideal would be to use sectiones of TBUFs, but only 1 exit per CLB so implement such Muxes with CLBs and wideOR on carry logic 2001.03.07 Wed further work on the time states and control circuit analysed IO pins for selecting where external memory will go, where processor for Virtex TQFP240: 1-60 28IO, 61-120 27IO, 121-180 19IO, 181-240 24IO TBUF databus bits come to Side 1/3, also BRAMs there APS-V240 1: ISA, 2: R/L pin, 3: L/T pin 4: U pin or ZBT Ram XSV 1: Key/Vid, 2: SRAM R, 3: Flash, 4: SRAM L BED-SPARTAN2+ 1: top/bot pin, 2: bot pin, 3: bot/top pin, 4: top pin, RAM bot so it seems that side 2 is the best place, arrange processor bot/left corner reordered data path now memory, addr mux, PC, IR, data mux(0), AR, logic unit revised data path to used separate enables needed by control circuit 2001.03.08 Thu looked at op code table, 2nd instruction group to implement will be 3xx found bug in Time-States, was not incrementing PC open question: when is it incremented? Reread Processor Reference seems to be all subroutine calls save PC+1, so increment direct after use seems to be also a problem with Mux set (begin of cycle) vs ClkE (end of cycle) possibly no problem, as these are Clk enables, not actual clocks so long clocking FFs does not change derived values too fast to disable, OK 2001.03.14 Wed 2nd Mail answer came from Xilinx, RAM_32_X_1 BX 5th address, BY data out, SR en improved memory section comments to reflect this actual working code in subroutine pdp10(), only Java/JBits overhead in main() decided against cutting up into further subroutines global variables not visible in other subs, and no gain in code legibility updating free row/col on separate line, after assigning current element multi-column elements loop first on col then on row, update col +1 in loop 2001.03.17 Sat Xilinx Mail announce of JBits 2.6, tried install, failled, program hangs sent them a mail reporting the problem 2001.03.18 Sun post asking about Virtex TBUFs, and replacement for them http://neil.franklin.ch/Usenet/comp.arch.fpga/20010319_TBUFs_in_Virtex_and_later_chips_going_out_of_fashion_what_instead seems they are going out, and that my MUXCY hack is the best way to do it 2001.03.19 Mon work on control circuits, making actual LUT patters and placing them found control logic bug, if IR.X not cleared instruction may not start 2001.03.21 Wed Hans B Pufal has scanned and OCRed TOPS 7.03 Monitor installation Guide (MiG) ftp://aconit.org/pub/dec-10/MIG703.TXT went to Tim Shoppas web site to look for KLAD tests of KI-10 http://pdp-10.trailing-edge.com/pdp-10/KLAD_SOURCES.HTML unlike KS-10 (DSK??) the KI-10 (DBK??) seem to not be entirely complete reworking control logic because of IR.X needing zeroing for inst decoder so introduced 2 different Muxes for bits 0..17 and 18..15 noticed further bug, index calculation should fetch mem(IR.X), not mem(IR.Y) improved various comments in http://neil.franklin.ch/Projects/PDP-10/Time-States and http://neil.franklin.ch/Projects/PDP-10/src/pdp10.java 2001.03.23 Fri 1970 version of reference manual on Al Kossows site, but seems to be KA-10 only http://www.spies.com/~aek/pdf/dec/pdp10/1970_PDP-10_Ref/ 2001.03.24 Sat control logic coded and added to source, using Fpga.set(CtrlRow, xxxCol, ) rewrote all LUT definitions from Util.IntToIntArray + Util.InvertIntArray to use Expr.F_LUT or Expr.G_LUT, compacter and a lot more readable code every comment line /* */ is heavy, just one /* */ set, but that looks strange does Java know //, look in book, yes, use that, better visible, not so heavy 2001.03.25 Sun Thread on cloning an old CPU with bit slice TTLs http://neil.franklin.ch/Usenet/alt.folklore.computers/20010325_Are_AMD2901_bit_slice_chips_still_available I suggest using an FPGA, and mentioned this project 1 participant points out PDP-10 was building full of designers, now 1 pers 2 participants, including above, take interest in using FPGAs for cloning control logic showed even larger problem with JBits row/col being CLBs, not LEs also switching to Expr.F_LUT makes this problem bigger thoughts about subclassing com.xilinx.JBits.Virtex.Bits to make new Fpga.set() convert LE x,y to row=y/2, col=x/2, slice=x%2, LUT=y%2?G:F and while doing so swap row/y,col/x to x,y but this seems to collide with Java language restrictions, no preprocessor no structs (must make objects, using them is more code than I save) come to the conclusion that I do not like Java as language switching to Expr.F_LUT made program slow, because parsing strings at run time and code bloat because properly needs error test (why not try{} used?) and also dependant on LUT F or G 2 different functions but hand generated bitpatterns and conversion was awkward so I made a class L (Lut) to set LUTs fast, easy and without test uses 4 constants for out=in LUTs and Java bitwise operators but L.xx syntax bloated, better define the I1 to I4 and L() in every class swapped space calculating Row,Col to Col,Row as in X,Y cartesian coordinates 2001.03.26 Mon further reorganising of space allocation algorithms and code aim for every coordinate having names, so that routing can add easily for bug catching print out allocated CLBs vertically also 2001.03.27 Tue Eric Smith adds to sunday thread that FPGAs are not difficult to do http://neil.franklin.ch/Usenet/alt.folklore.computers/20010327_FPGAs 2001.03.29 Thu Xilinx Mail announce of JBits 2.6.1, mentions 2.6 Linux install trouble 2001.04.04 Wed tried 2.6.1 install, failled also, same hang, try on Solaris tomorrow at work shows problem with closed source non-free software and license enforcement shit I have 2.5 install for sure, as tar.gz and on backups but I don't want to be dependant on such stuff for future upgrades and for new programmers (must get newest from Xilinx, as I can not copy) I really need to get open source and freeware tools start impulse for making this project 2001.04.05 Thu Solaris systems at work only have Java 1.1.x on them, upgrade to 1.2.2 that wants newer Solaris 2.6 patches that we do not have installed I will have to update our 1.5 year old recommended patch set no time for that at the moment (begin of new semester) looked at JRoute and JRoute2, use seems to be Fpga.route(src, sink) where src/sink is Pin(row, col, wire) with wire from ResourceDB but JRoute2 seems to have no Pin(), is this missing in the docs? 2001.04.06 Fri further studying JRoute and JRoute2, conclusion JRoute2 uses JRoute Pin class for generating routing of buses in loops I need for each line coordinates make an coordinate row and col array, run for () on Bit=0..DataBits-1 may want to change from Col and Row variables to single 2 element arrays general organisation may want to put System.out.print at end of blocks first attempt at method for managing Pin names, make symbolic names may be better at beginning of block, also Pin array while configuring despite various tricks I have not managed to get an optimal design through Java particularly random logic ends up with about 10 code lines per gate problem is that I really need something like an C functions and structs but without using Java objects, which requires separate source file and so loses access to my various global variables using an method call with many parameters loses struct/object advantage I want an optimally compact code that does not obfuscate logic same global variable problem prevents making of subroutines for sections this is just one case of me getting frustrated with Java being a B&D language I need an non-Java but also low level tool, will have to make one myself 2001.04.07 Sat go back to for () with Row/Col and fill arrays and single Pins, use them later revising of Time-States file format, simplified LUTs part, may remove entirely conclusion that JRoute2 uses JRoute Pin class is wrong compiling shows that JRoute2 wants Pin objects from JBits.CoreTemplate 2001.04.10 Tue further Pins coding for routing, Addr section compile gives int Bit redefined error, make it global and reuse is less verbose then using multiple MemBit/AddrBit/... variables long variable names AddrCtrlRow/..., make Row and Col global, use them more generally reorganise placing code, less variables, more simple var++ for ther moment leaving calls to Router.route away, far faster test runs Name collision int AddrMuxPC for row and Pin AddrMuxPC for output rework without the series of int Addr positions put all System.out.print("??? at " + ???Col + "," + ???Row); at end 2001.04.11 Wed looked at the HTMLised MEM manuals from Tim Shoppa Operators and Software Install Guide parallel PDFs from other sites but HTML is faster format, so get these, delete PDFs from web cache OS Commands and User Utilities are new to me and needed read OS Commands manual until end of command M* 2001.04.13 Fri read rest of OS Commands manual and User Utilities manual 2001.04.14 Sat changed again to for () with Bit and compute Col and Row, use ?: function this makes datapath like control circuits, where Row/Col are computed put System.out.print("??? at " + ???Col + "," + ???Row); back before for () changed it to use Col and Row, to catch wrong setting of them get rid of ???Col, ???Row and ???CtrlRow, direct Col and Row from Path??? data bits LSB..MSB changed to run 35..0, not 0..35, as PDP-10 is big endian do address bits LSB..MSB run 35..18 or 17..0 KI-10 console operator panel shows PC register as MSB..LSB 18..35 but Java array indexes always run 0..n, no base != 0 possible, grrrrr this requires awkward Bit-(DataBits-AddrBits) calculations in indexes so back to using Bit going 0..17|35 as in little endian processors reworked control logic in ~/Time-States deleted LUTs section, develop LUT splitting direct in source code results in less parallel stuff that needs to be maintained reworked control LUTs in ~/src/pdp10.java extracted all Logic-dependant stuff from Mem/Addr/Instr/Arith sections added routing to Mem and Addr sections, to the existing Pin definititions added Pin definitions and routing to Prog and Instr sections bug in Instr loading, IR.I is single bit, Virtex can only ClkEn pairs so reloading IR.I will at least reload IR.AC[1], need to redo Mux functions 2001.04.16 Mon rename IR.OP+AC+I+X+Y into IR.OP+AC+I+X and MA registers as in PDP-10 docs checked that IR ist 18 bits in KI-10 and KS-10, but even only 13 in KL-10 selective reloading of IR and MA IR IR.OR+AC from memory then stay, I memory or stay, X memory or zero intget all mem, index X from 0 rest stay, indirect I+X from mem rest stay MA insget/indir from memory and index from adder because no selective 1 bit ClkE for I, ClkE all and use diff Mux controls those that stay are implemented as mux load from self needs insget all load mem, index IR.OP+AC+I self IR.X 0 MA adder indir IR.OP+AC self IR.I+IR.X+MA mem, split mux ctrl on bit 0..12/13..35 mux enable lines for the 2 sections IR13-Mux= and IR23-Mux= 2001.04.18 Wed still dislike that Bit is running LSB..MSB 0..35, comments bits clashes this problem with Router.route Arrays going 0..17 for addresses 18..35 can be solved with large and complex [Bit-(DataBits-Addrbits)] but can also with setting all 36 bits and routing control signals to them reverse Bit counting to PDP-10 big endian, calculation of MSB/LSB indexes direction/end of for (Bit; >=; --) loops, Col/Row zigzagging Bit%2==1 extend enables and clock enables to full data bus width for full arrays rename memory address pins from 4..0 to 31..35 to fit mem addr mux out found bug, mem only connects address bits 0..3 for first 16words, connect other rework Time-States to reflect IR.Y -> MA renaming collision of usage of MA fuer memory address mux and memory address register rename memory address mux to MAM so that IR.Y can become MA completed effects of renaming IR.Y->MA in .java source rename code blocks Addr to Mam, Instr to Instr and Maddr found another bug, setting prog counter to 000000,,000020 would have set ...001 put it inside for (Bit;;) loop with test if (Bit==31) added further data path routing, MA/IR.X/IR.AC -> MAM MAM should only be 18bit for PC and MA, IR.X and IR.AC are only 4 bits split into 2 subsections with and without wideAND doing so found another bug, not selected S0Control.Y.Y for using wideAND also bug IR.AC used IR.OP as address bits, did not fit MAM width any more 2001.04.19 Thu rearrange Instr so that only one for () loop, use if () inside for OP/AC/I/X rename Instr and Maddr sections to both be IrMa, many common variables split Muxes index/load and self/load at Bits 35..13 and 12..0 use Bit going 22..0 instead of 35..13 because Java arrays are always 0 based 2001.04.20 Fri LUGS mailing list thread in which I let out my frustration at Java limitations bad at global variables, because "everything is an object" ideology non extensibility of precompiled binary classes, like JBits is one no preprocessor to get round these limits would actually like to have an C compiler that makes JVM .class files found a web site about other programming languages for JVM http://grunge.cs.tu-berlin.de/~tolk/vmlanguages.html one of these is a gcc back end, a patch set, highly experimental http://www.csee.uq.edu.au/~csmweb/uqbt.html#gcc-jvm I once tried to compile gcc, without patches, failled, this is not for me 2001.04.21 Sat routed Arith section only 3:1-Mux for address bits, 2:1 rest, split like MAM/Proc/IrMa splitting duplicates much code, makes less readable (what is different?) merge split loops with if () in the resulting one loop improved commenting, added section dividers, sub-split sections routed Logic section decided to move _log parts of control back where they were split off from also move ProgInsget back to IrMaInsget set initial FSM bit in insget found bug, state bits should use XQ output, not X found bug, identifying logic instruction is not a state, no XQ the same applies also for insxnot0, insdoing, insfinish 2001.04.22 Sun tidied up commenting a bit reworked control logic in ~/Time-States deleted logic equations section, develop equations direct in the source code results in less parallel stuff that needs to be maintained rolled change from IR+MA separate clocks to separate muxes back into diagrams after state diagram section with only state equations added to these the subsets for insxnot0, insdoing, insfinish, loginstr found bug, ArithOut should also be XQ/YQ, not X/Y, like in ProcOut/IrMaOut 2001.04.23 Mon further comment tidy up and expansion, dito Time-States eliminated LogBoth state, folded it into LogAc, LogMem second trigger all LogAc|LogBoth in Mem and Mam -> LogAc, for Insget added LogFinish 2001.04.25 Wed started reading Computer Structures: Readings & Examples, first 2 chapters as it is out of print I have to use the online version at http://www.ulib.org/webRoot/Books/Saving_Bell_Books/Computer_Structures:_Readings_and_Examples/ this is badly done, OCRed into non-iso-8859-1 charcter set, dingbats wrong also all scanned image as .jpg at low resolution badly readable 2001.04.26 Thu continued Computer Structures, chapter 3 and part 2 / section 1 intro 2001.05.02 Wed write code for loading an program and data from pdp10.mem into memory description of using files in my Java book is even worse than rest, unusable colleagues suggest O'Reilly Java in a Nutshell, went to web site and read http://www.oreilly.com/catalog/javanut3/chapter/ch04.html that solved the problem, how to code Java file operations produced first pdp10.mem file, 017 words of data, 017 words of program looking for TPC and TAP file formats, TPC Link on pdp-10.trailing-edge.com pointed to ftp.wku.edu, but site has moved to http://www.process.com/openvms/ checked new URL as OK and notified shoppa@trailing-edge.com of stale link first load into BoardScope notice how slow Java/Swing tools are to use also annoying features such as shows too little info per CLB also does not show CLB tags when in show data mode, makes them near useless also tagging is per CLB and not per slice of LUT/FF possibly to save bits as there seems to be only 12 (0x0000..0x0fff) looking at LUTs shows bugs Mem G LUTs loaded with all 0, missed editing MemBit test for 1 -> '1' Mem bit 34 empty, missed editing Row test for 0 -> 1, all 2nd col 1 row up second load, looking at LUTs shows all is positioned and loaded right looking at core view all black, should add tags running a few clock steps shows no action, seems that clock is not being used added Fpga.setTag() calls to make design parts appear in BoardScope "core view" added Fpga.set(,, S0Clk.S0Clk, S0Clk.GCLK0) to activate clock pins im Mem to drive WrEn, in Proc/IrMa/Arith XQ/XQ/YQ, in IrMA/Logic XQ third load, will still not clock, Device Simulator uses GCLK1 per default my code was on GCLK0 so it ignored the clock, changed code to GCLK1 fourth load, PC gets the clock, as it increments 020->021, add/mux/load works but IR and MA did not get loaded, so all-0 instruction assumed and so instr exec FSM bit goes lost immediately, instant frieze found bug while checking decoder, incomplete edit, LogicInstr no insexec& instead LogicImm and Logic1st still have insexec& too much 2001.05.05 Sat testwise set PC to always increment, counter works, increment and load Mam show address in FFs and testwise always EnPC, address appears there Mem show output in FFs, nothing appears there, always 0 suspect the LUT-RAM mode setting is wrong, redid it, now the data appears but top half data appears only on YQ FF, XQ FF has bottom half data looks like X F5 mode is missing, added it, no effect visible but after 16 clocks when Mam[31]=0 then XQ=YQ, F5 seems reversed: 0/1:G/F testwise set insget to always be active, PC and EnPC again proper from insget IR gets loaded with all instructions, boolean logic unit reacts but addresses mixed up from forced insget active insget proper, now insget loads, after insget is gone, decoder dies again this is an logic bug in the Time-States design, back to redesigning that tidied up Time-States logic flow diagram section to better show dependancies reworked instruction execution FSM, decode insdoing -> state insexec states insidx and insind -> decodes, decode insexec -> insready states logimm and log1st -> decodes state equation part of Time-States now near meaningless, only in source, del seems to now just about execute one instruction, then loses state bit commented pdp10.mem, so that I can check better what it should be doing found contradiction on http://www.inwap.com/pdp10/ opcodes.html vs hbaker/pdp-10/Boolean.html swap Memory and AC checked with Reference Manual, opcodes.html is right, mail jsmith@inwap.com 2001.05.06 Sun moved IrMa state machine after control circuits, to untangle control lines a bit of tidying up, extended System.out.print()s, grouped Tag+=1; with them checked bool logic instr arrangement, had high=C(E)=AR and low=C(AC)=MD swapped improved commenting logic section, incl sections from Ref Manual, with page no test run, to repeat what happened yesterday, is same thing first instr SETZ seems to work, next instr fetch wrong address ...011101, despite PC=...010001, seems to be ORed IR.AC from SETZ logac second instr from 035 is ORCMI@(), (10) fetches 0, not 1, possibly adds, X=0 @4 does @10 fetches 1, then no load to MA and insexec bit is gone, crash testwise show Mam enables to see when wrong, on first fetch IR.X+PC+MA active testwise show all IrMa decodes, adding tests see insind LUT formula wrong triggered on non-indir index, not on index, most likely what lost FSM bit Mam still has IR.X and MA permanently enabled, suspect missing input lines insidx is missing line to MamEnIRXInsidx, insind missing MamEnMAInsind test run shows no stray enables any more, but 2nd instr fetch still addr 21->35 the fetched index+indirect ist properly executed now, was state machine suspect Mam wideOR logic to be always ORing in IR.X and IR.AC wrongly wired, should be using YB output, not Y for wide-ORed muxes still wrong, must also be inverted LUTs for wide-OR and no XOR_CARRY thats is, it now fetches proper 2nd instruction AR Mux has same error, here YQ FF is needed, so route YB to BY and so FF test run shows state machine working, but log unit makes wrong output 2001.05.12 Sat discussion of Alteras Linux port of their tools and Xilinx port possibilities http://neil.franklin.ch/Usenet/comp.arch.fpga/20010510_Finally_an_FPGA_tool_chain_for_Linux_Altera_Quartus_II too late for my project, I will stay with existing path, also Xilinx better Phil Hays says he would prefer an TOPS-20 port, if hardware were available I make an remark about TOAD-1 and this project 2001.05.16 Wed add DebugDisp variable to conditionally include code for displaying state these are special wiring to use FFs as Display in BoardScope/DeviceSimulator also DebugMemROM to prevent changing memory, no need to track change effects test run with DebugMemROM, does not go off, still modifies memory first 3 instr go right, but SETMB stores AC and at same time changes AR all Bit%2==1 are missing, gone to 0, so store of MA gets wrong data debug showing of ArithCLkE shows it is not active when bits lost it seems that ArithWrEn is always being clocked for Bit%2==1 column ArithWrEn needs to be connected to all 36 S0_CEs, no Bit/2 as in Prog/IrMa remains problem with Mem not switching to ROM, don't do S0RAM stuff, stay ROM but with this, the XQ/YQ do not display any more, despite real out data XQ/YQ display is more important than ROM, so this attempt has failled while running more instruction it looks like memory is always writing reread Mails from Xilinx, can't find claim S0_SR for LUT-RAM enable tried using S0_CE instead, that seems to work as intended further test run with S0_CE=0, that was it, no memory change as milestone 1 is reached, make archive copy to ../PDP-10/Milestone-20010516 move all of ../PDP-10/src/ to main ../PDP-10/ directory post to newsgroup project status and path ahead as forseen from here on http://neil.franklin.ch/Usenet/alt.sys.pdp10/20010516_FPGA_clone_status_1st_milestone_reached 2001.05.20 Sun further work getting into Virtex, look at programming BRAMs nothing in Intro or Tutorial or VAG, only JavaDocs reference manual to go by http://neil.franklin.ch/Projects/PDP-10/Virtex-BRAM-PIPs looks like pure PIP setting, JRoute will do that automatically 2001.05.23 Wed get rid of Ctrl section in placing algorithm, also merge Proc and Path to Proc no tagging CLBs as not used for debugging anyway, also too little granularity mux for immediate operand bypassing AR, saves one wasted clock more important it also saves needing halfwide larger mux for AR added logic for section, but not connected to Logic or reduced Arith section 2001.05.24 Thu continue mux for immediate operand bypassing AR, reduced Arith data path Logic change data path naming from SelNNN to DatNNN, and Bit to Funkt rewired Logic data path to use Immed DatImm, not Arith DatAR Arith reduced control, got rid of MA/logimm part which is now in Immed need to redesign Locic control section to drive these fully decode all 4 modes of instr, then simpler drive states from that run insready direct to state generators, not through instr type decoder this results in shorter critical timing path, higher clock possible drop Time-States being maintained any longer, as upkeep just dual work updated PDP-10/OOREADME, PDP-10/OFAQ and PDP-10/Hardware files 2001.05.25 Fri - 2001.05.27 Sun was at a Linux User Group camp for the weekend, offline, no programming showing my project to others for the first time noticed on BurchED website he is now selling modified batch 3 models ex 24MHz osc of Spartan2+ and CPU-IO Plug-On are now 1..100MHz programmable planning implementing instruction group 011 CAI/CAM/JUMP/SKIP/AOJ/AOS/SOJ/SOS sees to be compare/subtrace 2 values or add/sub 1 to an register, then test test for zero/negative/both, ev invert, on 1 jump or skip instr format is 011aaaicc (aaa=action, i=invert, cc=condition) so need one LUT/bit data path for complex subtract/incr/decrementer and then massive 36bit in OR to detect zero, and MSB for negative OR 9*4bits, 2*4quad-bits, 1*final, then 1LUT zero/neg/both, 1LUT inv 2001.05.29 Wed made various Data* and Addr* (*Bits, *MSB, *LSB) constants to "final" generalise linking of central mechanisms and work units/sections move Logic internals dependant parts of control functions to Logic section like with LogFinish part being taken out of IrMaInsget MemClkELog, MamEnIRACLog, MamEnMALog, AR-Mux=MD, AR-Mux=logout, Imm-Mux=MA split random gates part into control and state, as in IrMa eliminate 1-input gates for LogArithEnMD, LogArithEnLog, LogImmedMuximm just set Pin variable that will be wired to, to be pin out goes to continued planning instruction group 011 CAI/CAM/JUMP/SKIP/AOJ/AOS/SOJ/SOS is compare (AC-0,,E, AC-C(E), AC-0, C(E)-0) or add/sub 1 (AC+/-1, C(E)+/-1) test never/negative/zero/both, ev invert, jump (PC=E) or skip (PC=PC+1) big massive OR of 36 bits will use wideOR logic, after mux/subtract in LUTs wrote comment block for beginning of arithmetic testing section 2001.06.04 Mon split Logic state random gates part into instr decoder extension and FSM extens Logic proper control of using Immed section and drop 1 clock state activate Immed mux and do same C(AC) read and operate as for loggetacc after this directly end at logstoacc state, widen Arith driver OR gates compiling gives to high a chip, 33 CLBs, won't fit into 32 2001.06.06 Wed Logic reduce hight of chip, lognormal/logimmed and logmemory/logboth each 1 CLB Logic implementtion looks bulky, tidy up, also IrMa IrMa also split state random gates part into instr decoder and FSM parts collect all relevant random logic functions to get better overview http://neil.franklin.ch/Projects/PDP-10/Logic-Functions IrMaInsget rename input from Logic to just Log like with all other functions extended by Logic and others rename all section dependant extensions into subparts LogicFinish rename to LogIrMaInsget to fit naming for subparts noted contradiction Logic vs Log, leave it for the moment general tidy up differences IrMa vs Logic splitting of controls/decoders/states loggetmem and logimm move to control, as precomputed subfunctions 2001.06.09 Sat small bit of tidying up, improved some unclear commenting Logic moved mode description comments to beginning tidying up differences IrMa vs Logic ctrl/decode/state continued with IrMa insready is part of decode, precomputed for all actual instruction decoders integrate insidx and insind into insexec, move insidx and insind to control put them after control, for shorter paths, dito for loggetmem and logimm decode part is only precomputes, real decoders are in other units drive ClkE-AR direct from sections, not indirect from AR-Mux=* 2001.06.10 Sun further improving of some commenting IrMa insready is only used for control and state, so not decode precompute left over decode precompute insindex can only be used in IrMa, move there test changes since milestone for no unwanted side effects 2001.06.14 Thu go through Reference Manual on arithmetic testing, completing description noticed AO* and SO* set flags, investigated flags system, where should flags go one possibility with PC, as they are saved with it also they are mainly used and cleared with JFCL, that also changes PC or together with AR, as they are extension to it, also nearer computation but AR is temporary register, often rewritten, unlike flags or together with ALU, but problem with multiple partial ALUs best have ALU sections generate flag set signals and PC section store or their own data path slice, to give enough place for generating and ctrl but that wastes data path wastes space, so only if PC section too small Trap has no effect with paging off (case at moment, as no paging implemented) Carry0 and Carry1 and Overflow (C0^C1) are only used for PC store and JFCL so do not implement them for the moment 2001.06.15 Fri printed out http://www.inwap.com/pdp10/opcodes.html for going on holiday print chapter 2 of ref manual http://www.36bit.org/dec/manual/ad-h391a-t1.pdf failled, because printer not 2-side, made .ps file to split and rearrange Xilinx Mail announce of JBits 2.7, mentions Linux and NT install troubles 2001.06.16 Sat test run to see if changed I handling works, SETZ goes ANDI fails AR instead of and(mem(15),4), loads mem(4), loads mem(15), ands, then stores looks like it is still doing old separate load method, no change show FFs for Logic instr decoder and control precomputes SETZ misses LogicNormal but works, ANDI sets LogicNormal and does that found bug, moving LogicImm and LogicBoth from F to G, was still LUT.SLICE0_F changed to LUT.SLICE0_G and it works this F/G different source (as opposed to Row variable) is annoying need better methodology, along line of RTPCore LE granularity SETZ worked despite broken LogicNormal, because of an logic bug formula insready&(~logimmed) will also fire on all non-Logic instructions should be insready&(lognormal|logmemory|logboth) or for less input lines insready&loginstr&(~logimmed) but that puts some LUTs over 4 inputs, need redesign Logic random logic tidy up changes done to random logic stuff in last session IrMa no precomputes insidx and insind, put direct into LUTs where used gives less LUTs, we are now in the 0..27 range for a XC2S200, test works rename insready to insdecode, as it drives the instruction decoder 2001.06.17 Sun split up the .ps file generated from ad-h391a-t1.pdf on friday setup, 51, 52, .., 198, shutdown, also p2, p3, p, p-odd, p-even, p-even-rev mend Logic instruction decoder to only fire on proper instructions change loggetmem and loggetac to use lognormal|logmemory|logboth that fixes bug, but whole Logic decoding is still bloated, not elegant 2001.06.19 Tue printed out the split .ps file generated from ad-h391a-t1.pdf 2001.06.20 Wed reorganised begin of this Logfile, more history, first computing all events linear (no back dates), more old Usenet posts (all with FPGA in) musing on chip display better than BoardScope, in true 2x3 CLB shape even 4x4 pixels for LUT disp, only 8x12 per CLB, X2S200 42*9x28*13=378x364 so 2x2 pixel per bit for LUTs are possible, and below 8x4 for FF state allows user to see used space (LUT!=0) and different units (diff LUTs) is better than the tag() from JBits, with separate viewer and needs code use details in XAPP151 to implement this, also BRAMs (3pit/pixel), IOs 2001.06.23 Sat - 2001.07.07 Sat was on summer holiday, offline, but did some planning and designing designed data path for 011/101/110 instruction groups started designing for 010 group, done 01000 and 010111, started 01001 instr groups 000 and 111 also look simple, and presently not completable 000 needs system/user modes, for now just physical addr 40/41, MUUO->LUUO 111 needs IO devices, for now just do "device" returning 0 decided that all instr groups writing back to AR is going to make large Mux particularly if making all units with separate data paths and so also outputs some like shifting even with multiple outputs. Muxes are FPGA weakness Mux inefficient of space and lines to it inefficient of speed also needs lots of control, unit and AR, better all units individual "AR"s existing AR is then only temp register for first operand from mem, no Mux will also save control section logic and wiring it to AR Mux and CE as it feeds Imm Mux, use FFs from same row of logic elements, call it OpIm data path will be Mem -> BX/BY->FF -> LUT-Mux->X/Y -> user for multi-AR Mux write to memory, 8:1 Mux with 1 port per instr group groups with multiple "AR"s need their own additional internal write muxing instead of 8-enable Mux driven from instr groups make it 3-select by IR0-2 requires less drive logic, less bugs possible, is also slightly faster thoughts on SMP, only of use when multiple exectable programs cheap performance multiplier for many user machine, useless for single user needs code-costly multiple processors in 1 FPGA, not worth it to save FPGAs or multiple FPGAs and bus sharing, is how Intel&Co do it, so right way this would require then memory with multiple ports, more extra cost better make one single processor fast, so far one FPGA has space for it should enable XC2S200 going up to about 30 times KL-10, enough for anyone 2001.07.14 Sa looked at XAPP130 (BRAM layout) and noticed it is pipelined needs clocking change, as I will be going to external memory, skip BRAMs 2001.07.15 Sun improved commenting a bit, updated status section to include Imm got rid of SysCol/Row, direct load of ProcCol/Row with 0/0 no common AR (only used for operand from memory, individual "AR"s in all units Logic output to local "AR", and from there direct to memory Arith no input from Logic output, no AR input Mux at all, no LUTs used memory data write 8:1-mux driven by IR bits 0..2, Logic out to MdmIn4 2001.07.17 Tue while at work musing on doing an "chip photo" display program from XAPP151 info with CLB = 4x4bit/8x8 pixel, so BRAMs are 10x24bit/20x48pixel space aim for colour styling like that seen in microscope images http://micro.magnet.fsu.edu/chipshots/index.html 0=cyan, 1=yellow style, good red/blue invert, blue grid, green neutral will definitely have to make such an tool improve the new Arith and Imm and Mdm commenting made an simple index.html page for the projects website better than an raw Apache Index, also Links to a.s.pdp10 and external 2001.07.18 Wed calculating RP06 space, looked in existing sim_2.3d code, 18b and 11 differ what is in 10, got simh26b, same cylinder/track as 11, less/larger sectors RP06 815cylinders * 19heads * 20sectors * 128words * 36bit = 176MByte implement as n-drives * 1024c*32h*32s*2*512byte = nGByte, 2.5" ATA HD? try to compile simh to install and install/learn TOPS-10 gcc fails entirely to compile 11 or 10, seems to be an \ problem moved "co", "ro", "ds" commands for compiling/testing from aliases to scripts coded arithmetic testing unit data path, comparison subtractor, zero detect NOR 2001.07.19 Thu Logic-Functions file, get rid of double editing and associated errors mark lines for L-F with //-, added script "lf" to automatically filter them improved section introduction commenting, what the sections are actually for 2001.07.25 Wed improved commenting a bit moved loggetmem/logimm from control to decode where it fits better thoughts on improving still unsatisfactory Logic section control circuit thoughts on changing IrMa control of load/index/indir, logic in Muxes Logfile back-added forgotten holiday thoughts on not doing SMP for chip display it would be nice to have comments in the chip coded 4x4 pixel in 16bit int font, for putting text patterns in LUTs 2001.07.26 Thu write test code for testing font, tested it, font is left-right mirrored corrected it, retest, corrected 2 missed and 1 oddball glyphs marked all sections with code letters MAPIAIW34, in top row of XC2S200 put revision info text into last column of FPGA, also last column for XC2S200 2001.08.01 Wed co test for .java->.class compile success before .class->.bit compile rename co to make, delete ru (never used), rename ds to run make script collides with the make program, use comp (compile) general tidying up of code, make it more readable term state precompute insdecode is clumsy, change it to decode decode insdecode also looks clumsy, rename back to decode insready putting decode insready before states intget and insexec is clumsy, merge d+s IrMa name confusing, normal only 1st letter of section capitalised, ren Irma dito LUT inputs from IrmaOut ren Irop0-8 Irac9-12 Irind13 Iridx14-17 Maddr dito Mam inputs and controls new naming to fit same naming scheme in consequence also Logic Mam subparts for Irac and Irma renamed dito ImmedMA and ImmedAR to ImmedIrma and ImmedArith Logic dislike complex multi level, too large, normal/immed/memory/both decoder direct use of IR.OP.7-8 in decode and state LUTs, no normal/immed/memory/both rename logimm to logimmed, now that old logimmed is gone consequently also loggetmen to lognonimm and loggetac to lognon2 bad design LogicFunct should not drive 36 inputs from Irop buffer Irop with LogicFunctBuf like done with MdmSelBuf bug some Prog* variables (in control) were names Proc*, corrected Irma dislike separate 13+23bit enables, messy Bit-13 syntax make all Mux/add LUTs driven direct by insindex and insindir gets rid of split loading of enable Pin arrays gets rid of 4 controls for driving the 2*2 enables code now shows 4 different types of LUT, no IR.OP+AC = IR.I (w diff enables) side effect also different LUT patterns for IR.OP+.AC IR.I IR.X MA sections 2001.08.08 Web Mail from Xilinx that there is now an JBits discussion list jbits@yahoogroups.com, subscribed to it 2001.08.15 Wed officially opened subproject to make an "chip photo" viewing tool named this tool VirtexView, command vv created VirtexView project directory and started logfile http://neil.franklin.ch/Projects/VirtexView/Logfile will implement it after reaching PDP-10 2nd milestone updated index.html, added links to ts10 and SIMH and to prototype board Atest check over data path and rework and comment it missing carry in from BX for adder/subtractor, is surprisingly always 1 LUT function seems to be wrong, need 2 function select lines for 4 functions drive function lines via buffers, like Mdm select and Logic function zero detector multi-stage NOR code is badly readable and voluminous replace by an carry chain wide-NOR, time hidden behind subtract computation Atest control buffer IR.OP function bits detect condition never/lower/equal/loweq, and invert condition to doit decode the 3 subclasses CA* vs JUMP/SKIP vs AO*/SO* renamed Logic-Functions to pdp10.lf, more systematic, no collision with Logfile replace //- foo with // #foo that comment indention cleaner visible test compile in LogicFunctBuf0Irop3 getting strange error message: com.xilinx.JRoute2.Virtex.RouteException: Unable to route sink CLB(18,11,S0_F1) other 3 buffers are OK, also 2 buffers in Atest, also with IrmaOut[3] moving LogicFunctBuf0Irop3 after LogicFunctBuf3Irop6 moves error also the other w (4..6) route as they are supposed to send mail to JBits@yahoogroups.com to see if anyone knows what is up 2001.08.16 Thu mail answer from Xilinx, suspect routing resources all used up test with jroute.getFanoutRouter().debug = true; sent test result back to Xilinx, also dumped pre-crash bitfile and sent that all Output Muxes used up, JBits routes every route from out, no Mux reuse must make Pin array as target for each IrmaOut and just route that once 2001.08.20 Mon further mail answer from Xilinx about situation, suggest using cores+Nets+Buses but I do not comprehend the documentation for that, also big style change simulate with Pin array, this make array of large size then when all Pins there copy to an fitting sized array and route that alternatively hand use horizontal longlines, hand route output once to them then route all LUT inputs from longlines for this Xilinx says I need to use ResourceFactory to reserve resources unfortunately JBits does not know longlines as place and route-to resources need to select and set all routing PIPs by hand, lot of work 2001.09.03 Mon khtsoi@pc90026.cse.cuhk.edu.hk published Linux parallel port download program http://neil.franklin.ch/Usenet/comp.arch.fpga/20010903_Linux_download_bitstream_w_source there are only 12 horizontal longlines per CLB, only 2 drivable per CLB http://neil.franklin.ch/Usenet/comp.arch.fpga/20010903_Virtex_Architecture_Interconnect so additionally to work, collision if MemOut and IrmaOut are 6 CLBs distant longlines seem to have been reduced to nearly as useless as tristate lines 2001.09.05 Wed will try variant with Pin array as it is a lot less work avoid copying by using fitting array, but needs adjusting for new connections 9 bits of IrmaBus Pin array and IrmaPos int for allocationg space in them only 9 bits, as AC/I/X/Y only in few places, use normal one-to-one routing leave IrmaOut->IrmaOld separate, fast connection and we can have 2 routings MdmSel*/AtestFunctBuf*/LogicFunctBuf* from 0..2/3..4/3..6 AtestInstr/LogicInstr from 0..2, AtestCond/Doit from 6..8 AtestCompare/JmpskipAddsub from 3..4/3..4/3, Logic* 5 times from 7..8 this bug that cost 3 weeks only exists because tool implementation broken can not be fixed because closed source, needs workaround, I need open tools download JBits 2.7, try install, fails like 2.6 and 2.61, Install friezes, del 2001.09.10 Mon Discussion of implementing an cache inside Virtix/Spartan-II BRAMs http://neil.franklin.ch/Usenet/comp.arch.fpga/20010920_Data_cache_for_fpga_cpu_using_Xilinx_BlockRam 2001.09.12 Wed for Atest state logic design, first tidy up for existing Irma/Logic design docs integrate description into source as comments, not separate Time-States file improved Atest and Logic introductionary comments documenting instructions improved Irma and Logic description of state machine logic comments switch from "go to" to "come from" logic, as that is what is implemented switch terminology from decode/state to detect/state made tool sld, analog to lf, but to list out state logic lines marked with @ improved sld and lf to cut away the actual comment characters, just comments Updates hardware ideas file with new ideas about universal board for other clones, and sizing as ISA/PC104/portables designed Atest design state logic diagram, old 3 detects are useless, delete 2001.09.16 Sun already twice forgotten to advance date for TextRev, generate it automatically has additional advantage of using .bit generation date, not .java edit date Atest needs 3 IR.OP bits for decoding sub-instructions, no room for insready use 4th unused AtestInstr input, instr decode slightly slower, but not much proper answer to decoding time is to pipeline instruction decoder for consistency also change Logic to process insready in LogicInstr coded 6 subinstruction decodes and 3 further state bit FFs for testing AC!=0, for added store to AC state, detect insacc like insindex coded AtestInsget, expanded IrmaInsget to take signal from it requires 7 inputs, make 2 LUTs, F5-mux as OR, route nameless pins Y to BX extend IrmaBus connection counts, add 6 to IrmaBus3/5, 4 to IrmaBus4 coded control ClkE-atestAR, similar to atestwracc and atestwrmem found bug AtestZero taking from AtestOut registers, should be direct added direct AtestOutval output and routed from that name detect is good for Irma aux LUTs, but not for Atest/Logic instr decoders rename decoding LUTs to decode, rename insready to insdecode, it drives these Added DRAM plus SRAM config and floppy for DECtape to Hardware ideas 2001.09.19 Wed modified comp to generate pdp10.run run log file when running java pdp10 Atest make controls, 7 for Mem/Mam(2)/Proc(2)/Arith/Immed wired them from the decode/state LUTs, expanded ORs of targets, wired them Arith and Immed are driven by single inputs, no LUT, like with Logic AtestMamEnIrac and AtestProcClkE have more than 4 inputs AtestMamEnIrac use F5-Mux as OR for speed, AtestProcClkE not, to save code actually entire instruction decoder scattered, long signal lines, is slow may need all ANDs to be entirely centralised, direct after Irma AtestProcClkE not direct to ProcClkE as jump/skip is conditional rename ImmedMuximm to ImmedMuxImm analog to ProgMuxIncr Atest already was 32 CLBs high, now 5 CLBs added, will not fit XCV300 use multiple LUTs in one CLB, presently enough to fit XCV300 also multi LUTs per CLB in Logic as fits XCV300, but too large for XC2S200 Irma insdecode is also speed critical, speed up by fast connect from insindex eliminate insindir from state/detect by direct including, just normal control insindir is only driving IrmaSel and MamMux, include in these, eliminate side effect so many routes from IrmaOut[13] that no Muxes, use an IrmaBus move Irma specifics out of MamMux and ProgMux/ClkE, better code modularity sort controls in locally driving controls and remotely driving control subparts 2001.09.20 Thu Atest is implemented, do a round of testing first test if Logic still works after all the changes to it and central stuff PC goes through Mam and increments, but IR only recieves 1 set bit, IR.AC.9 Mam and Irma controls are OK, dito Mem output, is G-LUT Irma Mux always 0 was missing edit F->G after cut&paste Irma Mux logic, fixed IR gets instr, exec puts IR.AC in Mam, AR no reaction, Insget back active InsDecode is aktive, LogicInstr also, but not LogicNonimm LogicNonimm LUT is wrong, does I1&I2&I3 is because of missing (), fixed inverts I2 twice instead of once and then AND and then second invert but instead active AtestInstr, AtestCai, AtestInsget and so Insget was missing edit LUT 100->011 after cut&paste AtestInstr, fixed LogicInstr triggers, Mam is MA, data 0, AR stores, state is LogicNon2 next clock Mam is IR.AC, logAR is 0 (SETZ), state is LogStoac, OK next clock Mam still IR.AC, state goes to Insget, but Mem word all 1 (not 0) 2001.09.22 Sat continued Logic regression testing, for debug display Mdm FFs, why Mem inp is 1 Mdm, like Mam, if DebugDisp clock FFs to see what is being output, dito Immed noticed that new logAR FFs have GCLK missing, added, dito atestAR FFs if DebugDisp also clock call ontrol logic FFs, see what is going on there logAR out is 0, Mdm out is 1, that makes Mem get and store 1 unused Mdm inputs are 1, so it is most likely selecting wrong input suspect that F6 like F5 is counterintuitively driven, invert BY, works jumping back and forwards between pdp10.java and pdp10.mem is annoying also for Atest testing we will need another test program so we will need multiple .mem files, as .mem format not conditional file switching for compiling different tests will be even worse file .mem was invented for large programs in BRAM, but not going to do this better put test programs direct in .java, in Mem section, Mem[] = "..." can also use Java conditionals and commenting, no .mem file any more 2001.09.23 Sun continued Logic regression testing, first instruction SETZ goes OK but second instr ANDI, far too many bits set in logAR FFs, should be only b33 Immed and Mem are delivering correct data, dito function selection buf Mam set correctly to IR.AC, also correct LogicInstr, LogicImmed, LogicStoac is reading error on my part, output is X, Y FFs irrelevant, blank them out also Atest CLB 22 Sl1G AtestDoit set, PC jump, and becomes zero (not 4) forgotten to AND in atestClkE-PC into AtestDoit LUT, fixed next test run, all of Logic works, including Irma indexing and indirecting Atest wrote test code for new instructions, shortened Logic program to 8 instr now we have jump&skip, start properly with PC on last "read-in" instr = 037 first Atest test run, PC is reset to ...10101, not ...11111 is S0Control.XffSetResetSelect which is X/Y dependant, duplicate code in F/G second test run, get AtestInst und AtestJump, proper controls, Mam and Mdm but PC gets cleared instead of load from MA, missing input connection, fixed and missing AtestInsget, seems to be F5-OR problem, but it works in MamEnIrac also IrmaInsget is active, as next clock does insget 0 instr from Addr 0 is because DebugDisp enabling of FFs is only XC2S200 range, not XCV300 fixed by making constants DeviceMaxRow/Col, from Device, and using them while doing so also display real JBits DeviceName, presently XCV300 third test run, display is OK, PC gets loaded, but with MA+1 is carry 1 being added, take BX carry-in from ProgMuxIncr, not fixed from 1 while fixing noticed that Atest adder +1 carry-in wrongly has invert set first instruction JUMPA now works OK 2001.09.29 Sat Xilinx Mail announce of JBits 2.8, still mentions Linux and NT install troubles does not seem anything attempted to correct them, stay with 2.5 2001.10.01 Mon Discussion of XAPP151 control register flags, Virtex-E conf identical to Virtex http://neil.franklin.ch/Usenet/comp.arch.fpga/20011001_CTL_Register_in_Virtex_E_Configuration 2001.10.06 Sat corrected some comments of the test program still claimed start at 020 and claimed to only test boolean logic moved to separate test program and data section, separate from memory itsself added descriptive text to PDP-10 entry on Projects/index.html Page 2001.10.09 Tue Thread of resetting FPGAs without the logic going unsynced or metastable http://neil.franklin.ch/Usenet/comp.arch.fpga/20011008_FPGA_reset 2001.10.10 Wed after ideas while at work, updated/expanded/reorganised hardware ideas file 2001.10.15 Mon comp.arch.fpga Discussion pointed to an JTAG downloader for Linux http://www.cse.cuhk.edu.hk/~khtsoi/project/Xilinux/ 2001.10.17 Wed further reworking of hardware ideas file re-read Xilinx XHWIF (Java call API) and XVPI (VIR 32bit interface) docs 2001.10.19 Fri read about FlexATX board format, smaller that MicroATX format searched Intel Website for board format specifications, found format site http://www.formfactors.org/developer/motherboard.htm updated hardware ideas to reflect possible use of this format 2001.11.01 Thu rename Tpd to Rin (for Read-In), RinLast variable to set PC from in Proc set PC bits to 1 if extracted "Bits" from RinLast are '1' placing no separation of processor and rest (memory, IO) rename ProcCol and Row to PlaceCol and Row, moved them to setting up section found in Atest some Prog wrongly written Proc, corrected them still to powered out to concentrate on Atest testing, start later sections set up code sections for the 6 instuction unit section not yet implemented commented them on when they will be implemented, 110, 101, 010, 000, 111, 001 other 6 instruction sections than Logic and Atest added rest of summer holiday analysis to source, as intro comments 110ooamma Btest and 101tootmm Hword done a bit more work on analysing them designed the data path LUTs and FFs for these 2 sections both use same L/R swap 2:1Mux from 0,,E/C(E), possibly separate section 010xxxxxx, 001xxxxxx worked out the bit patterns for different subsections added ISA plus PC/104 variant to hardware ideas, also that without proto area 2001.11.04 Sun to simplify analysing BoardScope Dislpay 1 LUT per CLB as often as possible get rid of as many Row-- shared CLBs as possible, all in Irma and Logic tidied up some Row++/-- and Row+=0 to be more systematical code with Row+=0 got rid of all Row-- backpedalling, to simplify code, Row++ is final also put carry-in stuff inside data path for loop compiler error (should be warning) about not initialised Pins converted ProgIncrSeed, AtestNegative and AtestZero to 1 element arrays also make Row = Bit%2==1 ? Row : Row+1; also in 1 column data paths do not put Row++; in the "G" branch of if , making code more uniform doing so found bug, S1Control.AndMux.ZERO missing for "G" code branch re-ordered buffers for more logical bit ordering, LSB at bottom, MSB up top continued testing Atest implementation, result of comparison not visible storing into FFs is only for AO*/SO*, for debug display always store now data visible, but with 1 added to it, JUMP/SKIP I1-0 should be no carry so AtestCarryin needs to be LUT generated, in control section move carry-in logic analysis to LUT, dito also PC c-i analysis to controls 2001.11.05 Mon D G Conroy announces finished PDP-4/X clone and soon PDP-1/X, in XC4010 may be continuing than with an PDP-10 http://neil.franklin.ch/Usenet/alt.sys.pdp10/20011105_Another_DEC_computer_in_an_FPGA later this thread runs into discussion of hardware/boards for FPGA clones continued testing Atest implementation, JUMP is correct CAI subtract is wrong, from bit 32 on, ...00110, for a while then again right bit 30: ... bit 31: I1=0, I2=0, LUT=1, cyin=0, XOR=1, MUXCY=cyin, cyout=0, cy borrow bit 32: I1=0, I2=1, LUT=0, cyin=1, XOR=1, MUXCY=in1, cyout=0, 0-1in borrow bit 33: I1=1, I2=0, LUT=0, cyin=1, XOR=1, MUXCY=in1, cyout=1, no borrow bit 34: I1=1, I2=0, LUT=0, cyin=1, XOR=1, MUXCY=in1, cyout=1, no borrow bit 35: I1=0, I2=0, LUT=1, cyin=1, XOR=0, MUXCY=cyin, cyout=1, no borrow cyin: BX=1 cyout=1, no borrow this analysis gives ...11110, exactly what should be, bit 32 doing borrow data I2 is OK (visible in Immed Mux FFs), for I1 set Logic always MemData, OK suspect obscure code problem or BoardScope/DeviceSimulator bug, Mail Xilinx 2001.11.11 Sun still waiting for Xilinx answer, give them 1 week until Mon in the mean time started work on my VirtexView project 2001.11.14 Wed sent mail to Xilinx if my first mail has been lost 2001.11.15 Thu got answer, Mail was seen, may be lost internally 2001.11.16 Fri got answer, they think my code is right, also can not find an tool bug send test code, compiles here and makes different wrong result mail them URLs with .java/.class/.bit of test code and my code 2001.11.25 Sun still waiting for second Xilinx answer, sent "refresher" mail 2001.11.26 Mon installed Java 1.2.2 on now up to date patched Solaris 2.6 at work fetched JBits 2.8, ran installer, transfered result as .tar.gz to home Linux recompiled .java to .class, run to make .bit, tested that on 2.8 BS/DS exactly same wrong bit pattern, verified there are really proper input data mail to Xilinx describing that mail back suggests using new 2.8 feature check what the CLB inputs/outputs are, click on their name tags doing so shows wrong CLB input data on bit 3 (row 1 G2) from the Immed Mux data should be from ImmedOut bit 3 (row 1 S0_Y), but code has S0_X, bug! corrected that to Y, recompiled, works, was cut&paste F/X -> G/Y missed X->Y this bug that cost 3 weeks only happend because of F/G code duplication shows that I need to get F/G (and Sl0/Sl1) independant code fast as possible this would be the case if I used my own program development tools 2001.11.27 Tue discussion about connecting modern IO to an FPGA 10 http://neil.franklin.ch/Usenet/alt.sys.pdp10/20011127_Like_to_see_more_action 2001.12.08 Sat discussion about implementing front pannels, desired user experience http://neil.franklin.ch/Usenet/alt.sys.pdp10/20011208_Wants_needs_was_Re_Another_DEC_computer_in_an_FPGA 2001.12.09 Sun went through Hardware file noting implementation details for different IO ports read up on details some PC IO devices and of AT and SCSI buses added ideas about using an 8051 for configuring, ev also use it as FEP 2001.12.16 Sun continued testing Atest implementation, CAI now works, CAM also SKIP should write C(AC), state atestwracc becomes properly active but at same time also atestinsget, missing invert on insacc input, corr, OK this was right in #state part, falsely copied to Fpga.set(... LUT. ...) shows up problem with JBits Java code bloat, many lines per single LUT shows that I need an programming tool that is more expressive AOS works, SOS does not subtract one, changed 0xFFFF to (~0), same effect RinLast renamed to RinStartAt 2001.12.21 Fri discussion about PDP-10 architecture flaws, supposed cacheing trouble http://neil.franklin.ch/Usenet/alt.sys.pdp10/20011221_PDP_10_architectural_flaws I sketch out how an 3 read port register set can avoid this problem also show rough equivalency of logic density for XC2S200 and 80486 2001.12.23 Sun XKL is reopening PDP-10 TOAD-1 production, doing new XKL-2 processor http://neil.franklin.ch/Usenet/alt.sys.pdp10/20011223_XKL_2 also intention to after make an single board CPU/Mem/Net/Disk system 2001.12.28 Fri SOS does not subtract one, -1 is actually +0 with borrow=0 subtracting 1 get rid of entire XOR 0xFFFF or ~0 stuff from ALU, change carry-in generator in Hardware file updated ideas about configuring per 8051 for use as FEP added sharing RS232, keyboard and floppy connectors 2001.12.29 Sat continued testing Atest implementation, SOS, sets MA to all onesa result totally crazy, retest AOS, works, check up program is bug in test program, had @1 in its bit pattern, not just 1 as in comment ALU still does not subtract, rechecked ALU, seems to be coded right test further, AOJ works and jumps because N = not equal, so can't test SOJ change reg 16 to reg 1, which is all ones, so that all zeroes appears rerun SOS, after load of instr, before clocking "subtracted" data I1=1, LUT=1, XCarrySelect.LUT_CONTROL, BX=0, Cin.BX, XB=0, XOR/X=1, hmmm is my code for -1, redesign, with adding all ones, no carry, works AOJ works as before, but reg 16-+ only changed in comment, also do in code AOJ now works, does not jump, SOJ works, jumps to 31 (CAM), testing done as milestone 2 is reached, make archive copy to ../PDP-10/Milestone-20011229 updated index.html.en file with links to milestone 2 corrected new link to SIMH, added link to KLH10, added links to alt.sys.pdp10 posted to newsgroup m2 project status and path ahead as forseen from here on http://neil.franklin.ch/Usenet/alt.sys.pdp10/20011230_FPGA_clone_status_2nd_milestone_reached 2001.01.31 Mon while out for an walk, thinking on memory/register and read port and pipelining separate C(IR.AC) read port gives immediate data, no read cycle, no Mux ctrl can directly fetch C(MA), or even already act on 0,,E separate C(IR.X) read port gives immediate IR.Y+C(IR.X) without reloading MA saves update cycle and MA-add/IR.X-delete Mux, and driving from IR.X!=0 separate Reg/Mem gives fast C(MA=0..017) without wait for memory cycle also IR.I direct 1 memory cycle C(C(MA=0..017)), no MA reload 1write/3read registers and 4*16 registers will use 3*/(4mem+1mux) CLB columns is 15 of 42, or 35% of chip space, perhaps only do 3*1 CLB col and swapping also on same walk thinking on later bitmap display3*1/2/3/4bit should fit 36bit more than this (3*6/8/10/12) will need 72bit or even 144bit bus) with enough bus width and cache size UMA video is fast, see SGI O2 machines 2002.01.02 Wed updated some stuff in 0FAQ numbered LUTs in control logic sections, for easier finsing while debugging use variables SysClkS0 and SysClkS1 (now fixed S0Clk.GCLK1 and S1Clk.GCLK1) need 2 variables to set clock source for each type of slice make reset put chip into defined state, clear all FSM FFs, not just set insget dito PC bits, force all to required 0 or 1, not just set the 1s go back to read-in test data and program from separate pdp10.mem file merged was not a good idea, got rid of need for 2 windows open but needs scrolling Rin/logic, so I used 2 edit views to be faster separate file gets rid of need for .java syntax, more usable space on line set initial PC to start from read-in amount of words on test bit 31 is 0 instead of 1, bit 30 resets 31 because of no Xff->Yff corrected, remains broken, RinStartAt is correct, ON/OFF formula also reset BS/DS before reload, is now OK, is BS/DS bug when only load new bitfile 2002.01.05 Sat planning on how to do 3 read port changes, which step after which recorded the thought work from 2001.01.31, which I forgot to do then while doing this, idea doing without same-time read/write ports of registers could use just 3 times 64bit/2CLB columns, no need for swapping to save space no need for doing mem/reg and read/write before separate AC and X ports but needs 3 sep Muxes for read PC/MA|IR.AC|IR.X vs write MA/IR.AC address also loses on space, delays signals, requires control logic write registers parallel to PC load from memory so no time loss but lose on ability of fast PC load from registers when still writing them nice idea but seems to not be so practical to implement better waste G LUTs on separate read/write, simplest, fastest, costs space 3rd alternative to +12 CLB cols space waste or reg swapping is modifiy the OSes for TOPS-10 use modified KISER.MAC with register saving code from KASER.MAC looked up source sizes, for 6.03: KASER.MAC 50blks, KISER.MAC 166blks this suggests first making an KA-10 compatible, then extending to near KI-10 I intended expanding KI-10 to partial KL-10, so deviate from lower down on as TOPS-10 6.03 and ITS run on KA-10, and TOPS-20 needs an KL-10B, this is OK under any of these relocation instead of paging is not critical like Unix so go for KA-10, updated 00README and 0FAQ to show this change in plans 2002.01.10 Thu present code is too much details, F/G dependant, Sli 0/1 dependant needs higher abstraction level, get rid of such nitty-gritty details planning on how future code should look, intend assembler-like code labels to name LUTs, instructions set LUTs, activate features, wire inputs no execution, just description, so no loops to make repeated stuff rather use macro-like expansion to generate repeated code design language, look for Macro-10 manuals, found assembly language handbook http://www.spies.com/~aek/pdf/dec/pdp10/1973_AsmRef/00_1973AsmRef_SysRef.pdf but only the system reference part is there, not the macro and later parts 2002.01.12 Sat further additions to Hardware file, result of musing on pin count limitations better generic IO ports and adapters, or possibly use BGA or second IO FPGA also wide 72pin memory is out, even 36bit may need multiplexed addr/data so any high color video is out, unless (F)BGA cases are used designing method to make code LUT F/G and Slice 0/1 independant look at RTPcores, as I remeber that Xilinx had a method in there 2.8 do not have such logic any more, are F/G dependant, use Slice[] names 2.5 used Java [][]..., with xxx[Slice][LutFG]... indexing /usr/local/JBits2.5/src/com/xilinx/JBits/Virtex/RTPCore/Basic/LUT4.java define with private static int ctl[][][][] = {{ctl0X,ctl0Y},{ctl1X,ctl1Y}}; and private static int pin[][] = {{pin0X,pin0Y},{pin1X,pin1Y}}; add 2 further indexes Sli and Lut to existing Col and Row replace existing Col+= and Row+= code with next_col|sli|row|lut functions codes arrays of constants for all CenterWires pins, even unused SR and CLK arrays of constants for modifying LUT value and other CLB resources generated new more systematic naming scheme for them, no ON/OFF reordered Bit/Row/Col to Col/Row/Bit, added Sli and Lut variables to them moved project status done so far from pdp10.java to this file, just before todo later moved done to after todo, so that todo direct after current logging 2002.01.13 Sun moved LUT function generating code after the new LUT independant constants moved null bitstream file name out to device name and size constants make use of the new place independant constants, to make code independant replaced SysClkS0 and SysClkS1 with SysClock = SelClock_1; always use SysClock[Sli], exept end debug display SysClock[0] and ...[1] replaced all other Fpga.set() constants with new ones for TextRow always use [Sli][1] to get top LUT, for TextCol use [0][n] for dual-LUT logic with fixed [Sli][0] and [Sli][1], else with [Sli][Lut] for single-LUT logic add Lut = Bit%2; to last line in loop replaced all CenterWires.* constants with Pin..[Sli][Lut] ones for dual-LUT logic with fixed [Sli][0] and [Sli][1], else with [Sli][Lut] got rid of FX/GY dependant dual code, done Prog Irma Arith Immed Atest so from now on FX->GY edit bugs, that cost 3 weeks, are a thing of the past found bug in calculating Lut, for 2nd Bit it is still 0 Bit%2 still uses old value, not yet through for(), use 1-Lut instead same F/G independance also for vertical revision info text loop reordered Col/Sli/Row/Lut/Bit to Col/Sli/Bit/Lut/Row as Row is Bit dependant further reordered to Bit/Col/Sli/Row/Lut as Col can also be Bit dependant got rid of space wasting use of 2 Sl0 instead of an pair of Sl0+Sl1 was originally done so to save needing dual code Sl 1 is left and Sl 0 is right, so start with Sli = 1, done Mem Mam Logic for visual consistency in BS/DS also switch rest of logic to use Sli 1 change all fixed [0] and [1] indexes to opposite sense, done Mdm Atest split Atest 2 sub-units adder/subtrator and zero detector into 2 separate loops one for each slice, add Sli = 1-Sli; at begin and end, change [0] to [Sli] also for 2nd slice 2 LUTs in controls, use same Sli = 1-Sli; technique fails in second loop with routing null pointer is because Row = 18 being counted further, runs out of space fails now because in logic routing MemOut to LogicDatMDF out of resources is because Mem now in one Column, halved number of output muxes up to now used 5 per bit, now only 4 available Hardware file added possibility of using PAL to program FPGA 2002.01.14 Mon MemOut out of routing resources, convert to use MemBus like IrmaBus use an array of DataBits arrays of 5 positions each, route in an loo avoid bugs from wrong bus lengh count, make large and then extract actual this method should always be used for any high fanout signal apply same method to IrmaBus, to all Bits, some with IrmaPos == 0 unused now that I have the easy non-count mechanism, convert all IrmaOut to it IrmaBus[Bit][IrmaPos[Bit]++] = ???[Bit]; compile crashes with NullPointer, on Bit 17 separate Atest 2 slices, put condition test ProgClkEAtest in 2nd slice controls change that instead of ProgClkEAtest only AtestDoit test, AND in first slice 2002.01.15 Tue IrmaBus compile crashes with NullPionter, on Bit 17, is MamIridx[Bit] should be MamIridx[Bit+18] because Bit is 17..14 and MamIridx has only 35..32 dito MamIrac[Bit+23] because Bit is even 5 lower by then was an editing oversight when converting IrmaBus to new method text font also set as array of constants, not as function that inits an array added rest of characters, for full ASCII 0-127 character set but with a-z using duplicates of A-Z (a-z too small), nonprinting as blocks 2002.01.19 Sat merged VirtexView sister project with up to now unpublished libvirtex project named merged project as VirtexTools, VirtexView is now just one tool in it http://neil.franklin.ch/Projects/VirtexTools/Logfile at some time in the future this PDP-10 project will be recoded using them 2002.01.20 Sun looked at sync reset stuff, no docs on sync to what (clock assumed) also no docs on when used is suggested or not desirable switched to always use sync reset, is most likely superior while doing so noticed that SnControl.nffSetResetSelect is source select, not polarity, only usable for such if only SR or BY used renamed my constants arrays and changed code to reflect how it works the entire Fpga.set(c,r, n[][], n[][]) notation is clumsy replace it by an short fpga(n, n) function, or 2 for Sli vs Sli+Lut dependant this will be a large set of changes before getting done for this placing variables Col/Sli/Row/Lut need to be moved out of pdp10() equivalent to assembler "current PC" notion, just 2 dimensions and 2 part also switch to general @Col:Sli|Row:Lut format when printing position out but variable Bit not placing, should not be outside, not with them at all define it directly in for()s, can also catch false usage outside of for()s while at putting placing in static variables, also put Place* vars there while at making static variables, also put Debug* stuff there, not in pdp10() 2002.01.23 Wed switched to assembler-like column:slice|row:LUT space allocation for placing get rid of Place* variables entirely, replace PlaceRow with 0 everywhere put Row = 0; Lut = 0; just before System.out.print() of start position write section letter into DeviceMaxRow:1 LUT after System.out.print() replace PlaceCol += with Col += and put at end of sections, after Col use revision text replace Col:Sli (and setting it) with DeviceMaxCol:0 put Row = 0; Lut = 0; after Col += as then new column:slice is being used for this set initial Row and Lut when Col and Sli are set because of this and revision text Row = DeviceMaxRow move it to end in for(Bit...) moive Lut = before Row = , done for every bit, Row only some atest control where G LUTs used, change Row += 1; to Lut = 1-Lut; then change special case PinIn1[Sli][1] to normal PinIn1[Sli][Lut] 2002.01.26 Sat - 2002.02.02 Sat was on holiday skiing, offline, but did a little of planning and designing decided on using normal [Sli][Lut] convention for F5/F6 Mux LUT groups define each of the LUTs and all it logic, then step to next, strict in blocks where neccessary use align() fuctions to ensure starting on F-LUT or 1-slice 2002.02.09 Sat convert multi-LUT Fpga.set(... n[fixed][fixed]...) code to normal n[Sli][Lut] with normal stepping of Sli and Lut, so we can later use normal set(n, n) places to do this are Mem (data 2-LUT-RAM), MAM (address 2-LUT), Mdm (data 4-LUT), Atest (control twice 2-LUT), Logic (data 2-LUT) while search found and corr Prog/Irma/Atest Bit == DataLSB [0]->[Lut] AtestInsget straight forward, split Y->BX Link into 2 Pins and route() ensure beginning with F-LUT with if (Lut != 0) and then Lut = 0; Row++; AtestMamEnIrac is an 5-OR, G-LUT does nothing other than pass I1 through send G I1 signal directly to BX input of F5-Mux, no G-LUT LogicOut straight forward, even easier, because no Y->BX Link as at begin of data path, Lut is already always 0, no need to ensure MdmOut same, but with 2 slices, 4 LUTs, output from Y, use last LUT, slice 0 ensure beginning with 1-slice with if (Sli != 1) then Sli = 1; Col++; MemOut same 2-LUT as LogicOut but with all memory setup and loading stuff in MamOut same 2-LUT as LogicOut but only on some bits, some only G-LUT simplify Fpga.set(c,r, SetLUT[][], L(f)) -> lut(f) so no need for [][] and L() less drudge code to type, less stuff distracting reader from actual logic to also use this function for LUT text, convert these first as special text is not addressed with Row, Col, SetLUT[Sli][Lut] but rather with DeviceMaxRow, Col, SetLUT[Sli][1] use Row = DeviceMaxRow; Lut = 1; lut(); so move texts to end of sections SetLUT[][][][] is now only used once, in lut(), move it to there L() is now only used once, in lut(), integrate its functionality into there hide lut(Font[]) implementation mechanism behind lut_text() 2002.02.10 Sun simplify Fpga.set(c,r, What[][], To[][]) -> lcell(W, T), so less drudge code and also Fpga.set(c,r, What[], To[]) -> slice(W, T), for slice affecting bits ModeLUT_RAM and ModeLUT_Shifter have mixed lc/sli presently correct that with separate On/Off constants for all settings while doing so rename array constants, systematic hierarchial naming for what: ThingWhat and for to: ThingWhat_To, with _To being often _Off _On also in lut() section renamed SetLUT to LutFunction move FlipflopSyncreset after FlipflopResetTo, als later more important put in a test for sli() being used on Lut != 0, got triggered too much, drop no ConfigurationException any more in pdp10(), remove it would be good to also get rid of remaining RouteException, and try { } changed Prog for (Bit) loop from Data* to Addr*, on if (Bit>=AddrMSB) any more routing arrays like ProgMux and ProgWrEn only AddBits wide because of Java arrays 0..17, no 18..35 possible, use Bit-18 because of these leave all single routes with DataBits width, 0..17 unused after loop jump over (DataBits-AddrBits)/2 unused Row places use Addr* only in actual address width stuff (Mam and PC) not for MA and instr field width stuff (Irma and Immed), there use 18 this is not nice, should really use some further constants same change also for Mam, leave the if()s for Bit>=AddrLSB-3 total rewrite of Mam later, when switching to separate memory/registers check up instruction set differences for different models up to now only documented diffs KI-10 vs KL-10 as intending to make an KI-10 now also KA-10 vs KI-10 and KA-10 FPU/BU options, as initially making KA-10 change docu for 001 instr group to reflect what was in what model at same time added docu on KL-10B extended addressing changes 2002.02.12 Tue simplify Pin Name = new Pin(.., r, c, Which[][]) -> Pin Name = pin_l(Which) and also version name = pin_s(which) for slice affecting pins, such as PinCe hide JRoute2 object Router.route() and RouteException in route(From, To) also needs routem() for route to multiple pins, code more readable anyway ProgCarryIn wanted routem() but AtestCarryIn worked with route() was usage of ProgCarryIn array vs AtestCarryIn[0] element standardised on using route() and so on *CarryIn[0] at same time changed generator LUTs .lf descriptors from control to carryin got rid of try { } out of pdp10(), reduced indention by 2 spaces still dislike carryin array hack to fix Java "may not have been initialized." could stop it by putting carryin before for() loops but I dislike that even more, it does not feel as belonging to its LUT while at it moved carryin stuff to where carry is used, after lut() same also Irma index adder and Atest wide-NOR carry start in all 4 cases merged double comments to one consistent one Irma and Immed use set of new Instr*MSB and Instr*LSB constants for if()s while at it changed Irma IR.X and IR.AC wiring shifts to computed formulas also changes Mam width calculation for larger Mux to computed formulas 2002.02.13 Wed control LUTs input pins systematic naming with output_input, for readablility Logic control subparts were still old Log* name, changed to Logic* same Insget state subpart and also LogClkE, also corrected one use of IrmaInsindex still used Idx as input name, changed to Insidx bug IrmaInsexec_Insexec was missing route from IrmaInsexec, added AtestCarry changed from AtestFunctBuf1 to direct IrmaBus[4], time critical states with same logic as the previous decode, merged into one block first both # lines, then decode, then FF and Q pin, no Row+=0; any more AtestCam/AtestCam2, AtestAsos/AtestWrmem, LogicNonimm/LogicNon2 renamed LogicNon2 to LogicNonimm2, now with pin() I have more space for it had a look at other non-logic blocks: similarly merged ProgMuxIncr and newly named ProgCarry, also same logic used systemat carry naming: carry in on data path and carry generator in control better commenting on one-input control subparts, explained Pin passthrough 2002.02.17 Sun make an list file pdp10.lst, formatted like an assembly list file for each lut set, list into it: place (col:sli|row:lut), lut value, lut name fought with Javas java.io input/output, which is totally assymetrical comfortable readln() in BufferedReader, no writeln in BufferdWriter comfortable println() in PrintWriter, no input counterpart list data conversion, lut value in hex zero-filled Sli and Lut symbolic as L/R and F/G, Col and Row decimal zero-filled put all position format stuff into pos(), for re-use, in placing section add an comment tag to all lut() and lut_text(), usually LUT output name renamed IrmaMamEnMad_Insexec to IrmaMamEnMaddr_Insexec, missed on Wed now that actual calculated positions for LUTs are logged into listfile remove hand generated position in control sections from source switch pdp10.run System.out.print to use pos() for same output format requires just reporting begins, and "begin of unused" at end 2002.02.18 Mon new pdp10.run too wide and single letters non intuitive d000L/000 -> data 000L/000, c000L/018F -> control 000L/018F, u -> unused drop s and p, as pdp10.run is only progress report and fit test now state/decode stuff before control/subpart stuff more routes to targets, easier code to read, Irma, Arith, Logic move AtestProgClkE after AtestDoit, so it routes its input from there now last G LUT of first Atest slice is not being used, move "3" tag there 2002.02.20 Wed thread on getting into FPGA development, differences CPLDs to FPGAs http://neil.franklin.ch/Usenet/alt.sys.pdp10/20020220_Getting_started_desiging_CPU_s 2002.02.27 Wed found one missed Pin(Pin.CLB, Row, Col, PinIn1[Sli][Lut]) to pin_l(PinIn1) conversion, for MamIridx[Bit] =, corrected it zigzag placing replace one formula using Bit..., with if(Bit...) and 2 formulas needed because Bit is part of the repeated allocation loop while the actual Sli/Row details are going into the placing infrastructure further reducing different (and particularly visible) uses of Row get rid of debugging display section at end, set clocking where LUTs defined reverse revision text to go bottom to top, like all logic goes, same formula analysed what placing operations exist, what code they should be, naming them changed lcell(), slice(), route(), routem(), lut() error messages to use pos() changed ProgCarryIn array to full DataBits width, use ProgCarryIn[AddrLSB] same for AtestCarryIn[DataLSB], AtestNegative[DataMSB] and AtestZero[DataMSB] 2002.03.02 Sat converted from using sld/lf/comp/run shell scripts to using make + Makefile made an Makefile to replace them, added it to the website no sld/lf/comp/run any more, as were archived in Milestone 2, links to there change from direct manipulation of Col/Sli/Row/Lut to packaged functions no appearance of the variables Col/Sli/Row/Lut in code or in comments have comments all speak of column/slice/row/LUT, that is users mental model standardised writing on F LUT, G LUT, F/G LUT, 0 slice, 1 slice corrected versions with LUT or slice in front and versions with - in them now all main code in pdp10() is independant of LUT positions in CLB compact code to use all LUTs in control logic, and to use all slices in Irma some of the controls run out of routing resources, skip G LUTs same also in Atest with some controls, also skip some G LUTs with this all presently planned programming style/methodology changes are done now I can go back to improvements of the actual processor design started designing how and in what steps to add separate registers 2002.03.06 Wed renamed Mdm section into Mdwm, as there are now going to be 2 memory data muxes Mdwm for writing to memory, Mdrm for reading from Memory or Registers renamed MdwmIn3 to MdwmIn_Atest and MdwmIn4 to MdwmIn_Logic expanded RinMem to 48 words, is Mem and Regs so renamed it to RinImage shifted Mem from 000..037 to 020..057 by using repeat due to no addr decode problem with RinStartAt wrong calc, temp back to only 32 word coded Reg 16 word data path, preliminary controls (ClkE) coded Mdrm 2:1-Mux to read from memory or registers, data path controls (Sel) for naming consistency with Mdrm and Mdwm always use Sel for Mux select pins ProgMux* -> ProgSel*, consequently AtestProgMux*->AtestProgSel* dito ImmedMux* -> ImmedSel*, consequently AtestImmedMux* and LogicImmedMux* for Mux lut pattern consistency with Mdrm and Mdwm, change ImmedSel to PinIn3 renamed all PinCe wires from *WrEn to *Ce, as clock enable is what they do using ClkE instead of Ce is already in use, ClkEn ist too similar merged zig2 and zag2 to nextzigzagsli, dito zig4 and zag4 to nextzigzagclb in both cases the if { zig } else { zag } code is now once centrally found nextzigzagsli bug, if Sli +-1 goes over CLB border then Col+-, fixed merged firstlut() and firstsli() into nextzigzag*() and secondsli() improved commenting on how zigzag works, all at next* call, not section begin changed AtestInsget to use secondlut() instead of the less expressive nextlut() found AtestMamEnIrac bug, G LUT must deliver 1 when *_Wracc is ORed, fixed Reg address bits from Mam, data input bits from Mdwm, same as for memory makes Mam after-for(Bit)-loop routem() list even longer, better route in loop add MemAddrBuf[] and RegAddrBuf[] address buffers to Mem and Reg as side effect this also hides Mem multi-LUT needing multi-routing from MAM 2002.03.08 Fri wire Reg and Mdrm into data path, change MemBus to come from Mdrm while at it rename IrmaBus and IrmaPos into IrmaInstrBus and IrmaInstrPos eliminate Instr*MSB and Instr*LSB constants and calculations with them just make code less readable, no advantage as instr format is constant rename MemBus and MemPos into MdrmDataBus and MdrmDataPos move all Bus/Pos stuff from Mem to Mdrm section single route of MemOut and RegOut to Mdrm inputs writing an comment, doubts that "registers" is official name looked up in ref manual, they are called fast memory, rename Reg to Fmem Fmem control for selecting what to read onto data bus, 14-NOR from MAM.31..18 control for selecting which to write to, duplicate MemClkE_* to FmemClkE_* add RdrmMuxFmem into the 2 *ClkE functions to only write to appropriate one project status split off "doing:" section from "todo:" section started work on 101tootmm half word Hword and 110ooamma bit testing Btest units changed pin names of MdwmIn5/6 to MdwmIn_Hword/Btest, 0/1/2/7 to MdwmIn_0/... changed the numeric 3/4/5/6 lut_text tags to mnemonic A/L/H/B ones put in System.out.print pdp10.run, for(Bit) loops, tags, minimal nextsli()s put in *instr decoders and *insget state subparts controls, extended insget 2002.03.16 Sat work on Hword unit data path, somewhat similar to Logic improved path design comments, for all units and other sections up to now set up the 2nd and 3rd for(Bit) loops, and System.out.print()s and nextsli()s middle of 3 loops of processing data is 2 slices, so call then steps refresh what the design, made a while ago, is intended to do took quite a lot time because design comments insufficient, improved them implemented half word swapper for HLL/HRR vs HRL/HLR and buffer to drive it implemented dest/zeros/ones/extend modifier and buffers to drive it implemented swapper/modifier selecton for H*R vs H*L and buffer to drive it numbered data path bits with lut_text, 2 slices for tens and ones digits 2002.03.17 Sun work on Btest unit data path, fairly similar to Atest refresh what the design, made a while ago, is intended to do set up the 2nd and 3rd for(Bit) loops, and System.out.print()s and nextsli()s implemented half word swapper for E,,0 and CS(E) and buffer to drive it 2002.03.24 Sun work on Btest unit data path implemented test pattern ANDer and zero/nonzero wide-NOR in on slice of LUTs implemented nothing/zero/compl/ones modifier and buffers to drive it designed Hword control logic states and actions similar to Logic, function bits and 4 modes, copy from Logic but also use IR.AC for self mode instead of both mode 2002.03.27 Wed designed Btest control logic states and actions similat to Atest, TR+TL and TD+TS like CAI and CAM, copy from Atest but with write back like after Atest AO*/SO*, conditional from IR.OP.3+4 inconsistency of titles of extensions in @ sld but not in # lf, changed to none also tag 2nd and 3rd slices of Atest, Hword and Btest, with "2" and "3" tags 2002.03.28 Thu compile test for stuff up to now, just a few small small errors in .java but massive run out of routing resources from ImmedOut ImmedOut needs to use an routem()-once bus like MdrmOut and InstrOut one remaining pesky "Unable to route sink" on just one(!) data bit, number 32 move bus routing before revision text, to use coordinates for debugging added all the nextlut(), nextsli() and System.out.println() stuff per bus confirmed that it is bit 32, the second bit of the second(!) row of CLBs not routing just that one bits gives no error not routing the F/X bit of the same row of CLBs also gives no error not routing to the swapped bits has no effect, same error not routing to Atest simply gives error in Logic, first target suggests ImmedOut problem, but that CLB has only 1 route from each X/Y out and without Hword/Btest it had 6 routes without any problem 2002.03.30 Sat rolled back all ImmedData but stuff, but kept rest of changes, compiles OK apart from expected ImmedOut trouble, from Hword left half (5th routing) on Arith/Immed CLB 1st Arith->Immed, 2nd Atest, 3nd Logic, 4rd Hword unswapped 5th Hword swapped, right half works(!) only left fails, 6th Btest all fail try leaving Atest and Logic on route() and just Hword and Btest on bus while editing noticed in diff buggy version still had IrmaOut not ImmedOut looks like an editing omission after cut&paste, corrected it, all works OK started implementing hword controls, state machine sld reversed to-mem/to-acc to from-acc/from-mem naming because more obvious found bug, self needs to read memory for both operands after second read always store to same, if mem and self mode also to accu 2002.03.31 Sun finished implementing hword controls added control ClkE decoder and missed HwordCe pins driven by it added all control subparts and extended their target ORs Mem and Fmem have duplicate ClkE ORs, logic units should not have to know this single OR for combining them in MDWM, same place as data for Mem is selected while changing Mem/Fmem put MemAddr and FmemAddr pin declarations in control also changed *AddrBuf to *Addr, as these are the "RAM chips" address pins only 1 input, no LUT, change to no intermediate Pin name, direct route() target implemented btest controls added ClkE decoder and missed BtestCe pins driven by it state machine, added missing btestClkE driving terms in sld added all control subparts and extended their target ORs, MamEnMaddr now 5-OR Btest BtestMem2->BtestSecmem analog to HwordSecmem naming Logic LogicNonimm->LogicMem and LogicNonimm2->LogicSecmem analog to Hword/Btest reorder state machine, logimmed before logmem as in sld, analog Hword/Btest Logic @sld and #lf rename log consequently to logic, as in all other 3 units 2002.04.01 Mon renamed lut_text() to luttext(), more in fitting with other names rename data path pins systematically to SectOut_In like done with controls MdrmOut->MdrmMux, Mdrm[Mem|Fmem|Sel]->MdrmMux_[Mem|Fmem|SelFmem] while at it control MdrmMuxFmem->MdrmSelFmem and MdrmAddr->MdrmSelFmem_Mam MamOut->MamMux, Mam[Iridx|Irac|Prog|Maddr]->MamMux_[Iridx|Irac|Prog|Maddr] Mam[Iridx|Irac|Prog|Maddr]En->MamMux_En[Iridx|Irac|Prog|Maddr] now *En->En*, like in controls, before impossible because name collision ProgOut->ProgCnt, Prog[Ce|Old|Maddr|Sel|CarryIn]-> ProgCnt_[ClkE|Old|Maddr|SelIncr|Cin] while at it control ProgCarryGen->ProgCin IrmaOut->IrmaIns, Irma[Ce|Old|Mem|Index|Indir]-> IrmaIns_[ClkE|Old|Mem|SelIndex|SelIndir], corr IrmaMamEnIdx->IrmaMamEnIridx ArithOut->ArithReg, Arith[Ce|Mem]->ArithReg_[ClkE|Mem] ImmedOut->ImmedMux, Immed[Sel|Arith|Maddr]->ImmedMux_[SelImm|Arith|Maddr] MdwmOut->MdwmMux, Mdwm[Sel*|In*]->MdwmMux_[Sel*|In*] now MdwmSelBuf*->MdwmSel*, no awkward Buf names, before name collision AtestOutval->AtestALU, Atest[Negative|Funct0|Funct1|DatMem|DatImm|CarryIn]-> AtestALU_[Neg|SelFunc0|SelFunc1|Mem|Imm|Cin] now AtestFunctBuf*->AtestSel*, no awkward Buf names, before name collision while at it control AtestCarryGen->AtestCin AtestOut->AtestReg, AtestCe->AtestReg_ClkE AtestZero stays, AtestZeroin->AtestZero_ALU Login no direc out, Logic[Funct0|Funct1|Funct2|Funct3|DatMDF|DatMDG|DatImm]-> LogicALU_[SelFunc0|SelFunc1|SelFunc2|SelFunc3|MemF|MemG|Imm] now LogicFunctBuf*->LogicSel*, no awkward Buf names, before name collision LogicOut->LogicReg, LogicCe->LogicReg_ClkE HwordSwapOut->HwordSwap, Hword[Src|SrcSwapped|Swap]-> HwordSwap_[Imm|ImmSwapped|SelSwapped], also Sel* HwordModifyOut->HwordMod, Hword[Mod0|Mod1|Dest|SwapTopR|SwapTopL]-> HwordMod_[SelMod0|SelMod1|Mem|SwapTopR|SwapTopL], also Sel* moved wiring from HwordSwap to where pins defined, no reason for later HwordOut->HwordReg, Hword[Ce|Swapped|Modifed|Sel]-> HwordReg_[ClkE|Swap|Mod|SelTarget], also Sel* BtestSwapOut->BtestSwap, Btest[Pat|PatSwapped|Swap]-> BtestSwap_[Imm|ImmSwapped|SelSwapped], also Sel* BtestZero stays, Btest[TData|TWith]->BtestZero_[Mem|Swap], also Sel* BtestOut->BtestReg, Btest[Ce|Mod0|Mod1|MData|MWith]-> BtestReg_[ClkE|SelMod0|SelMod1|Mem|Swap], also Sel* for all LUT pairs/quads in lut(, "") change string, separate F/G off to .F/G 2002.04.03 Wed further renaming of data path pins to make code more systematic and readable only register pins (out, ClkE, straight in) called Reg, rest by function HwordReg_[Swap|Mod|SelTarget]->HwordDest_[Swap|Mod|SelDest] BtestReg_[Mem|Swap|SelMod0|SelMod1]->HwordMod_* LogicALU*->LogicFunc*, AtestALU*->AtestComp*, because ALU is awkward ImmedMux_SelImm->ImmedMux_SelMaddr, because Maddr is selected, Imm is output all registers use Reg names for out and ClkE IrmaIns->IrmaReg, IrmaIns_ClkE->IrmaReg_ClkE ProgCnt->ProgReg, ProgCnt_ClkE->ProgReg_ClkE, rest of ProgCnt_*->ProgNext_* rename Mux outputs to what is muxed MamMux->MamAddr, MamMux_*->MamAddr_* MdrmMux|ImmedMux|MdwmMux->*Data, Mdrm|Immed are also now equal to bus names unify multi-bit selector naming/numbering scheme today Mdwm 2^n 1/2/4, units n 1/0 or 0/1, new all use 2^n 4/2/1 order Pin declarations and controls/buffers by high first (by IR.OP bit no) done Mdwm Sel4/2/1, Atest SelFunc2/1, Hword SelMod2/1, Btest SelMod2/1 noticed that Hword and Btest control->datapath was crossed out, corrected noticed that Logic Mux wrongly named, Func are inputs, Data are selectors LogicFunc_SelFunc[0|1|2|3]->LogicFunc_Func[8|4|2|1] LogicFunc_[Imm|MemF|MemG]->LogicFunc_Sel* Prog and Irma order Pin declarations and "= pin_l(PinIn*)"s in row *=1,2,3,4 move all "// @" lines after data path, before FSM controls (which they define) dito data path comments separate from intro, just before defining their pins 2002.04.07 Sun further renaming of data path pins, systematic SectOut_In, also in memories MemOut->MemData, Mem[Ce|In|Addr*]->MemData_[ClkE|Mdrm|Addr] FmemOut->FmemData, Fmem[Ce|In|Addr]->FmemData_[ClkE|Mdrm|Addr] name collision [Mem|Fmem]Data[-|F|G]->[Mem|Fmem]DataPreset[-|F|G] further renaming of data path pins to make code more systematic and readable unify multi-bit selector naming/numbering scheme, also in memories [Mem|Fmem]Data_Addr[31|32|33|34|35]->[Mem|Fmem]Data_Addr[16|8|4|2|1] changed [Mem|Fmem]Addr array to single pins, only *_Mam as array, like Mdrm renamed buffers Fmem-Addr[16|8|4|2|1], and re-sorted them high->low same as all selectors/buffers, Mdrm also reverse addr bits order high->low LogicFunc_Sel[Imm|MemF|MemG]->LogicFunc_Sel[2Imm|1MemF|1MemG] better control space utilisation in Atest/Btest move *ProgSelIncr stuff to zero detector slice, together with *ProgClkE speed up Atest AtestDoit->AtestProgClkE, old AtestProgClkE->AtestNow for consistency BtestNow as second name for BtestProgSelIncr while edit noticed cut&paste error in BtestProgClkE input pins, corrected changed IrmaInsacc and IrmaInsdecode to use busses like MdrmData etc more extensible without running out of routing, 1 less alignlutf() in Irma extended routing section to full System.out.print() structure with "control" (only in Irma) and "unused" (in all) 2002.04.14 Sun analysed if it possible to reduce size of Atest control section seems like JUMP and SKIP can be merged with AOJ/SOJ and AOS/SOS would give 4 instead of 6 subdecoders, smaller controllers driven by them 2002.04.16 Tue further Atest size reduction analysis 4 LUTs saved on atestasoj and atestasos decodesr and jumped LUTs 1 LUT saved on atestMAM-Mux=IR.AC control only 1 LUT insted of 2, and no F5 1 LUT cost on atestwrmem, is actually the old atestasos "un-saved" cost on atestwracc and possibly insget, need mode complex decoders most likely neutral on ClkE-atestAR redesigned state logic diagram, redo state machine logic formulas main reason for complexity is wrmem before wracc in Skips swap to write accu first, redesigned state logic and started logic formulas now 1 LUT each for jump, skip, wracc, wrmem ?, insget ? 2002.04.17 Wed further redo Atest state machine logic formulas and implementation wrmem needs 2 LUTs for AOJ/SOJ and AOS/SOS cases, insget still missing also did control circuit logic formulas and implementation further 1 LUT saved by not needing the atestnow, direct in atestClkE-PC 2002.04.20 Sat further redo Atest state machine logic formulas and implementation atestinsget is large, perhaps better if go back to doing wrmem before wracc sketched out both as diagram and formulas, wrmem first is better so switch back to doing it this way round, redone atestwrmem and atestwracc atestinsget to use 3 LUTs 1 and 2 going to 3rd, same atestwracc 1 go to 2nd result of this staged design no F5s in controls, saves even more space analog btestinsget also 2 LUTs as 1 going to 2nd, no F5 needed, simpler renamed cam2 to seccam, analog to *mem2 renamed to *secmem inserted alignlutf()s until all "output-Mux used up" routing errors disappeared code is now ready for testing for 3rd milestone, no more features intended 2002.05.06 Mon after mail discussion about using microcontroller for booting/configuring Rolie Baldock says that 8051 is primitive, so change to no specific type revisited Hardware file to make text more flexible, no specific type named reworked entire config loading options section, text now better blocks microcontroller also without Flash, using shared floppy/HD/PCMCIA/CF split IO devices into 3 sections user IO, storage, expansion connectors reworked expansion section, now better blocks of similar options first generic pins (non-bus) based ones, then bus based ones 2002.05.18 Sat regression test Atest JUMPA/CAILE/CAME/SKIPL OK AOS comments in .mem AO*/SO* wrong, corrected, AOS()/SOSG/AOJN/SOJGE OK change 037 JMP to go to logic instructions, for testing them 2002.05.19 Sun regression test Logic SETZ/ANDI/ANDCAM/SETMB/ANDCM()/SETAI()/ANDCBM@/EQVB@ with this all regression tests were successfull, now to testing the new stuff 2002.05.27 Mon improved commenting, the part about reader can skip all the auxillary code moved the comment to the beginning of the auxillary code sections expanded pdp10.mem to have 48 lines instead of 32, space for Hword and Btest moved existing Atest 30..37 to 50..57, 3x for Hword, 4x for Btest added sub-format comment for these 2 instruction groups at bottom pdp10.java enabled pre-written new lines in Rin to read-in the extra 16 words, and in Mem to use them wrote test instruction sequences for Hword and Btest checked in BoardScope that all .mem bits are in right LUTs PC has been loaded right, fetch 057 (JUMPA) PC incr to 060, JUMPA loaded executes JUMPA properly to 020, where SETZ waits, change go to 030 (HLL) 2002.05.31 Fri mentioned looking for an microcontroller to colleagues I want direct compressed bitream and decompressor in microcontrollers Flash told them about possible selections at the moment, they suggest Atmel AVR 2002.06.03 Mon went looking at microcontrollers for FPGA loading Zilog Z80/Z180 I know the instruction set, but no microcontrollers with it only Zilog microcontroller is Z8 which is different instr set, and mask ROM Z280/eZ80 webserver has all peripherals, but only mask ROM no flash Intel 8051 totally primitive, no space for bitstreams, best is 8751 EPROM external flash can not be addressed directly, only via special instr and uses up the few IO pins real fast, no left for FPGA, RS232, Floppy, IDE Motorola 68HC11 website ist unusable, can not even find data sheets Atmel AVR is a real processor, megaAVR large Flash versions up to 128kByte is actually an Harvard architecture RISC with 64k*16bit program space 2002.06.07 Fr testing with BoardScope is slow on my AMD K6-2/350 colleague suggests remote usage of new Athlon XP 1700+ at work tested machine while at work an got 10 times spead 3s/cycle to 0.3s/cycle tried running it from home over 256k/64k cable modem and it is dirt slow takes about 1 minute to draw initial screen, about 20 to draw updates is problem with Java Swing draws into local buffer then copy over X and they dont seem to have heard of compressing the MBytes of bitmap 2002.06.11 Tue after Mail from Harry Reed re-checked eZ80, has no mask ROM, no ROM at all eZ80 Webserver Developer's Kit has 1M Flash, but that is a multi-chip system I really do want an single chip solution, or I will prefer to use an SEEPROM 2002.06.14 Fri am presently contemplating change from Linux to NetBSD problem may be connecting FPGA programming circuits looked into how they are accessed under Linux: iopl() set to 3 opens ports or alternative ioperm(from, num, on) for sections instead of all then process can simply outb() and inb() direct to/from IO addresses so accessing hardware is as easy as under DOS, exactly the same methods BTW: the iopl() system call was added for XFree to access video card regs 2002.06.15 Sat found it for NetBSD, the equivalent of iopl() is called i386_iopl() also have i386_get_ioperm(32x32bitmap), for sections, up to 1023, else iopl() also there is an /dev/io, that when opened sets the IOPL register 2002.06.16 Sun mail from Hubert Feyrer from NetBSD, points to i386_iopl() equvalent of inb() and outb(), is bus_space_*(), abstracted from bus type so connecting an FPGA programmer is as easy as under Linux or even DOS 2002.06.17 Mon also mail from Ken Stailey FreeBSD uses /dev/io, no iopl() but i386_set_ioperm(), name as in NetBSD but usage as in Linux an actual data transfers with outb() and inb(), same as in Linux 2002.06.22 Sat further attempts to use fast machine from office colleague suggested VNC, installed it, runs a lot faster than raw X but not really faster than running locally, but feels better result bits are here faster, but then still updates rest of window there is also low bandwidth optimised version called tightvnc, try that next comp compile times home K6-2/350 vs office Athlon XP 1700+, 7 times faster tried running it, WOW! near full speed as if local in front of the Athlon no flackering from screen updates any more, just solid drawing 2002.06.24 Mon started testing Hword stuff, HLL fetches proper data but does not compute actually input data and computed X/Y is right, but XQ/YQ are wrong HwordClkE is properly set to 1, and routed to CE pins, but FFs not clocked is because forgot to select clock source with slice(ClockFrom, SysClock); added clock source to Hword and to Btest, where same ommission was done HLL retested and it works now also added if(DebugDisp) clock to swapper and modify stages, intermediat data while at that also added if(DebugDisp) clock to Atest and Btest zero stages put them after pin_l(PinOut), also changed to always after in controls further test, HRLZ works, HRRO proper swap but 0s instead of 1s signals to data path LUTs are OK, but LUT pattern wrong, no 1s in 3rd row is because 1 & I3 &(~I4) should be 0xFFFF & I3 &(~I4) to give 1 HRRO works now, same HLRE, HLLI, HRLM, HRRS(), HRLOM, so all Hword are tested having to copy all of pdp10.* to office machine for testing is slow needs all instead of just .bit because else make complains instead of running make bs only starts BoardScope, does not even load actual pdp10.bit load and reload done by File Open, no real dependance, take out of Makefile restored use of separate Milestone-20011229/run, but now named its bs so office machine only neads pdp10.bit bitfile and bs script switched pdp10.mem to next time test Btest, updated test program a bit 2002.06.25 Tue started testing Btest stuff, TRN gets right data, but result is wrong is also wrong function in data path LUTs, may be not enough ()s in lut() added complete bracketing, changed 0 to 0x0000 (also Hword for consistency) now set of 4 functions is right, first line is all zero but 2nd and 3rd lines are swapped, is right but not intuitive is from use of I3 as MSB and I4 as LSB in mux control is also so in Hword, not noticed in Atest, as 2nd and 3rd lines are same changed all three to I* as LSB (*_Sel*1) and I4 as MSB (*_Sel*2) also changed row of *_Sel* buffers to LSB->MSB in Mdwm, Atest, Hword, Btest makes them also consistent with LSB->MSB arangement of data path TRN works now, same TLZ, TDC, TSO, TRNE, TLNA, skipped TDNN(), TSCA modifying happens before testing, also in opcode, so reorder steps in chip while at it, 2nd and 3rd step are weakly named, give them proper names same also in Bitnum and Atest where there are multiple steps as milestone 3 is reached, make archive copy to ../PDP-10/Milestone-20020625 updated index.html.en file with links to milestone 3 posted to newsgroup m3 project status and path ahead as forseen from here on http://neil.franklin.ch/Usenet/alt.sys.pdp10/20020625_FPGA_clone_status_3nd_milestone_reached 2002.07.02 Tue RCS archive set up, loaded with all Milestone source files, not generated ones using ci -l -r1.0 "-mMilestone 1 20010516" * as revisions 1.0, 2.0 and 3.0, work will now be 3.x, 4th Milestone then 4.0 while at it added copies of 00README 0FAQ Hardware and index.html.en to the 3rd Milestone archive, do that they can also be traced Makefile added ci target to check in all source files but it can not be used at present, because revision numbers go out of sync 2002.07.03 Wed up to now big chunk of non-PDP-10 auxillary code before interesting code this is bad for legibility, as it confuses readers who have no need for it test if Java can define functions and globals after use, yes it can so move all the auxillary stuff to the end, no "start reading at" comment now still left main() with non-PDP-10 stuff before interesting code move all list file stuff to an auxillary code section, after placing stuff writelistfile should test if file is open, and only list if it is move all bitstream read/write stuff into an auxillary code section gets rid of Java error handling out of main() move all JBits initialising and chip type to an auxillary code section initialising should automatically determine chip size, not user supplied also saves the global variables for filenames, as these now parameters just a set of local variables as "set up" section in pdp10() main() now only contains of pdp10() and aux section calls (3 before, 2 after) move the aux section calls into beginning and end of pdp10() main() now only calls pdp10(), no function, merge them, only main() name move "understanding requirement" JBits docs to intro of aux sections compiling with make fetches sld and lf from RCS with co, despite no rule damm automatisms that do things that were not asked for 2002.07.06 Sat RCS trouble that is unpacks old lf and sld scripts archived Makefile as RCS revision 3.1, separate as make ci broken fixing make looks like an large job, better eliminate old files from RCS have only the ones I am working with currently, in current milestone use RCS only for documenting intermediate state of current development keep documentation of Milestones only in their directories, and own RCS for files in the RCS archive with pre 3.0 revisions, delete these they only contained the files from the first 2 Milestones anyway so the archives all start with 3.0, will have 3.x, and 4.0 at end then move them to the 4th Milestone directory, start new with only 4.0 in Irma naming prefix duplication to IrmaIns instead of Irma archived pdp10.java as RCS revision 3.2 IrmaIns->IrmaLoad, IrmaInsget->IrmaGet, IrmaInsacc->IrmaAcc IrmaInsindex->IrmaIndex, IrmaInsexec->IrmaExec, IrmaInsdecode->IrmaDecode also _Ins[get|acc|ind|idx|exec|decode]->_[Get|Acc|Indir|Index|Exec|Decode] also [Atest|Logic|Hword|Btest]Insget->[Atest|Logic|Hword|Btest]IrmaGet analog to all other subparts in format IrmaInstr[Bus|Pos]->IrmaReg[Bus|Pos], analog to all other buses [|] ins vs Irma inconsistency, also dislike Irma name, rename Irma* to Instr* _Irop/_Irac/_Irind/_Iridx/ is also non systematic like short ind/idx naming _Irop[0..8]->_Instr[0..8], _Irac[9..12]->_Instr[9..12]|_InstrAcc[9..12], _Irind13->_Instr13, _Iridx[14..17]->_Instr[14..17]|_InstrIndex[14..17] also *MamEnIrac->*MamEnInstrAcc, *MamEnIridx->*MamEnInstrIndex archived pdp10.java as RCS revision 3.3 2002.07.07 Sun addendum to above _Irac/_Iridx, _Instr[Acc|Index][9..12]->_[Acc|Index][9..12] and also all *MamEnInstr[Acc|Index]->*MamEn[Acc|Index] moved listing file section to after bitsream read/write section F5-Mux/AND|OR hide implementation behind auxillary functions as code for AND/OR only once, larger comments how it functions, and is wired MamAddr code is messy, difficult to read, and unneccessary slow because uses an 2 LUTs wide-OR, because I did not know about F5-Mux ORs then also all the special casing for Bit>=32 and <32 for wide-OR or normal OR switch to an F5-OR, now only half the code, less if() cases, better to read now that same code for Bit>=32 and <32, arrange Prog/Index/Maddr/Acc in the same row they are in the controls section and controls subparts test of new MamAddr, works as it should archived pdp10.java as RCS revision 3.4 2002.07.10 Wed lots of _ names are defined just to be used immediatly results in 2 lines of code where one would suffice, and this quite often use pin_l(PinIn) directly in the following route() line the long strams of control section code have been shortened by about 1/4 the entire code has been shortend from 3868 to 3606 lines, 6.12% only use an _ name when route later when source exists now all tidy up operations planned before milestone 3 and delayed, are done I can now start with adding further functionality for 4th milestone found Bug in Btest, BtestReg was using PinOut instead of PinOutQ, corrected archived pdp10.java as RCS revision 3.5 PDP-10 planned post milestone 3 changes done, now ready for new features but first I want to improve documentation there, for that I need VirtexView also I want to start education colleagues on using FPGAs, that also needs vv so now I am going to work on VirtexTools for a bit, until enough is running 2002.07.14 Sun went looking for Linux tools for programming microcontrollers found assemblers (ava, avra) and download tools (avrprog, uisp) for AVR one C compiler and simulator (sdcc and sdcc-usim) for 8051/AVR/Z80 simulator (gpsim, sumulpic), assemb (gputils, picasm) download (picp) for PIC of above I have looked at 8051 and AVR; so also went and looked at PIC PIC16Cxx are too small, PIC18Cxx large enough, but seems messy like 8051 2002.09.10 Tue while doing VirtexTools and looking for Virtex-II config info saw documentation for SystemACE TQFP144 device for config from CF card added this to Hardware file as boot option 2002.09.22 Sun VirtexTools is nearing 1st milestone (vd, VirtexDump), just tests and man page planning for 2nd mi (vv, VirtexView) which will be used for making pictures so I synchronised planning on future interaction of both projects VirtexTools 1st milestone (vd) released, now on to 2nd (vv), then back to here 2002.10.15 Tue VirtexTools 2nd milestone (vv and libvirtex/virtex.h) released as I now have the visualisation tools from VirtexTools, now back to here Logfile back-add RCS check-in times for 3.1 to 3.5, as recorded in VirtexTools 3.1 was Makefile added ci, RCS 2002/07/06, but Makefile edit date 2002/07/01 and Logfile claims that Makefile added ci on 2002.07.02 funnily 3.0 was start of archiving, RCS claims 2002/07/01 Logfile claims no activity on 2002.07.01, and 2002.07.02 Tue RCS set up will put "archived 3.1" on the 2002.07.06 Sat entry, at beginning 3.2 was moving of non PDP-10 JBits stuff to end, RCS claims 2002/07/06 but Logfile gives 2002.07.03 Wed for doing this will put "archived 3.2" on the 2002.07.06 Sat entry, before renaming 3.3 is also RCS 2002/07/06, seems to be just after work, put at end of day 3.4 is RCS 2002/07/07, MamAddr, last in log, put at end of day 3.5 is RCS 2002/07/10, RCS file contains Btest fix, put at end of day added on 2002.07.10 remark that now switching to VirtexTools project Makefile add -r to Makefile ci, change comment, now as it works in VirtexTools rename 00README and 0FAQ to README and FAQ as users expect them today fixed references in README, FAQ, Makefile, index.html.en Makefile added make tar target, $(DIR), make, index.html.en added link to it index.html.en README and FAQ in intro section, only Logfile in status section reorganise web site, move Milestone- to ../PDP-10- this puts them parallel to ../PDP-10 and ../PDP-10.tar.gz, fix FAQ index.html.en changed all references to point to new place, added .tar.gz pdp10.java various improvements, get rid of ------ ------ duplicate at begin that was sensible when first lots of infrastructure/implementation stuff separate implementation off from rest with large -------------------------- rename WriteFont[] to LutFont[], and luttext() to lutchar() LutFont[] replaced by the optimized one developed in VirtexTools rename readnullbitstream and writedesignbitstream to readbitstream and writebitstream, as neither null nor design dependant 2002.10.21 Mon index.html.en tidy up HTML code formatting, remove "on BurchED hardware" part in Links re-classify BurchED as possible, and add Trenz as other possibility expanded "basics" section with motivation/situation that lead to project and with what has changed to that situation since then, DGCs project Usenet section added links to DGCs 2 PDP-10 project threads expanded status section to describe what has been done and what is planned to be done, both from the Logfile status section on maine (newer IM) made pdp10logo.png (vv -q -z 1 pdp10.bit) for website Makefile add to make tar, and added make target logo -> pdp10logo.png added an of pdp10logo.png to index.html.en, as title picture made pdp10.vd.gz and pdp10.vv.png (on maine for IM) of current and milestones but vd and vv will not work on 1st milestone pdpd10.bit file, header wrong "vv: expected stream synchron missing, not a standard bitstream" using "od" shows that there are 2 FFFFFFFF words in the pdp10.bit "dd bs=143 count=1" from newer file, "dd skip=155 bs=1" old one, then cat Makefile added vd -> pdp10.vd.gz and vv -> pdp10.vv.png targets 2002.10.26 Sat some small improvements to new home page content made PDP10-20010516/pdp10.vv.html descriptive text for 1st milestone short intro how FPGA works, how I used it, then detailed column wise will later edit/extend this for 2nd and 3rd milestones and current added links to all 4 descriptions to index.html.en, and added to make ci/tar links in download for each milestone and current, they and easily missed so main page graphic at top also as link to current description page 2002.10.27 Sun PDP10-20010516/pdp10.vv.html text corrections formatting same style as VirtexView man pages bold for terms, italic for emphasis instead of and use and , for later browser/CSS styling 2002.10.29 Tue PDP10-20011229/pdp10.vv.html descriptive text for 2nd and 3rd milestone all 3 milestones added with the link to pdp10.vd.gz one to pdp10.java adapted descriptive text also for current state fixed lack of mnemonic in revision text column inconsistancy regenerated all milestones .tar.gz files, with descriptions, final versions 2002.10.30 Wed index.html.en moved alt.sys.ppd10 announcements out of "single files:" list archived all changes as RCS revision 3.6 index.html.en rework "done:" section, do that milestones are better visible also "todo:" section to better show future planning yesterdays .tar.gz files were without all generated files add them, as most people have no JBits, re-genearate .tar.gz files again change make tar to also pack up entire current directory, not selective announced the availability of description pages and website changes FAQ in "What is this FPGA stuff?" added link to the description page re-read PDP-10 reference manual looking at the 010xxxxxx instructions 2002.11.04 Mon design 010xxxxxx fixed point, as only partially done in summer holiday 2001 see entry for 2001.06.23 Sat - 2001.07.07 Sat, for how far I got then it has taken 1 year to implement all the stuff planned then split up into subgroups, and see what each group/instruction does while doing *MUL/*DIV copied B/I/M/B modes from Logic noticed comment error, C(AC) and C(E)/0,,E are swapped, fixed it also swapped "Source1" and "Source2", making C(AC) Source1, like in arithm done all other than JRST and JFCL, as these are fairly large and complex 2002.11.06 Wed looked at JRST, requires extension to MA reg, to restore flags from 36b indir can not simply load direct, as load/noload only known when instr is loaded read up sect 1 of Reference Manual, KA and KI E only 18 bits, no top carry requires dual flags registers, one load with instr/indir, other with PC and at JFCL which turns out to be simple, bit test and jump on 4 flags 2002.11.07 Thu while reading comp.arch.fpga referrence to an online book on processor design http://www10.dacafe.com/book/parse_book.php?article=BITSLICE/index.html based on the AMD 29xx series, by one of their technical staff reading it may be usefull for designing the 010xxxxxx data paths just came at exactly the right time for me 2002.11.10 Sun extended mail discussions with Andrew Grillet about his new prototype board uses 4 large connectors (nice in Trenz), but all on front (nice in BurchED) he is interested in PDP-8/10/11 cloning and wants to offer front panels! looked at various issues, such as connectors and system layout front panel (rows of LEDs for what data, and width), memory vs IO buses updated home page "Auxillary" section, boards list with all the prototype boards I have considered, and comments on them 2002.11.13 Wed home page further additions in boards section and corrections in history rename Artihmetic Register (AR, Arith) to Memory Operand (MO, Memop) while hunting down Arith and AR referrences, improved commenting noticed inconsistency of Hword 1st/2nd operand naming relative to all others fixed up pdp10.vv.html to new naming, tagged as "O" (operand) regenerated both pdp10.vv.png and pdp10logo.png pictures with "O" 2002.11.14 Thu with Andrew Grillet started exchange on flexible FPGA boot option which allow storing multiple designs and chosing at boot time which to load load from floppy/EEPROM/CF/IDE/SCSI, run by CPLD/small-FPGA/uC(8051/AVR/Z80) 2002.11.18 Mon with Andrew Grillet started exchange on possible ATX format board possibly with large chip than 200 size, ideal for KL compatible machine discussion about including an PC "legacy IO" chip for PS2-key/PS2-mouse/serial/parallel/floppy/ISA interfaces 2002.11.27 Wed updated this file with 2002.11.14 to 2002.11.25 entries read up on entire PDP-10 system layout, what elements where 2002.11.28 Thu got news about Xilinxes XC2S400E and 600E chips, large, many BRAMs and cheap with this Spartan-IIE (and so Virtex-E) becomes interesting for me E series chips are not supported by JBits, so they will require recoding this will require me to get on with VirtexTools to do this 2002.12.03 Tue mail from Andrew Grillet that he wants to use the XC2S600E for his ATX board his target project is to run ESAs Leon Sparc clone on the board but is interested in making board PDP-10 usable, so long no design conflict he will be using largest chip, because overhead is more than chip cost anyway this seems to be XC2S600E-FG676, with 514 user IO lines, IO galore! 2002.12.08 Sun decided that an underused large board for KA-10 and then expanded design is cheaper than first small board for KA-10 and then large one for expanded and it saves the time making RAM and IO modules for small/prototype board so better to get Andrew up to optimal speed for the large board this means I will have to convert to E capable tools for first chip running so switch to standard Webpack tools and vas coding as fast as possible started file Boardspec with spec for Andrews XC2S600E board basically take my Hardware file and run it through Andrews constraints these are: good for ESAs Leon Sparc clone, ATX format, PCI connectors (this file evolved into todays BoardSpec600E.html file, in FPGA-PC project) 2003.01.14 Tue VirtexTools project got an offer for contributions so will switch to working on both at same time, not block switching 2003.06.04 Wed decided to get on with VirtexTools for the moment 2003.06.18 Wed looks like getting well into VirtexTools, so I will be staying there a while so index.html.en links to Boardspecs, so people can see at least something moved link to Hardware file down to after proto boards dropped duplicte links to Burched and Trenz from "External Stuff" sect made separate "Hardware" section for proto and own board stuff added the 2 BoardSpec*.html links to this section 2003.10.04 Sat main PC HD crash, needs complete rebuild of system, no data loss (backup) 2003.12.22 Mon after 1 month rebuild, then 1.5 months since doing nothing, here or VirtexTools noticed that reason is total loss/lack of interest in both projects both only wanted for the other, PDP-10 to test tools, tools to make PDP-10 2003.12.23 Tue decided to give up both projects, get them off my mind unsubscribed alt.sys.pdp10 and comp.arch.fpga as no further interest in them did archiving .tar.gz of news server and backup of them deleted them both from news server, news fetch and news reader 2003.12.24 Wed updated Logfiles and Websites to reflect both projects being canceled 2003.12.25 Thu moved Hardware file and BoardSpec*.html into separate FPGA-PC project even if no intention to do anything on it, still better for others finding it retroactive removed all board spec stuff from this file, from 2002.12.09 on ------ project status doing: nothing, this project and VirtexTools canceled on 2003.12.24 todo: atest2 source add comment why not used 9*4bit+2*16+1*16|16|4 zero detector no space saving (1 col also), not faster (carry hidden behind ALU), more code wire control signals fastest/nearest to time critical LSB of carry chains so data path at top of chip, control starting from LSB side, downwards nextlut() allocate from top, so data path is alligned, tags at bottom row change data path for (int Bit ..) loops to count 0->35 instead of 35->0 for LC options instead of may slice() and lcell() func, make single feature() or even merge this with lut() to lutx/lc(, ) instruction unit 010xxxxxx fixed point, design data paths instruction unit 010xxxxxx fixed point, design/implement data paths, control instruction unit 001xxxxxx byte operations, design, data paths, control regression test Atest, Logic, Hword and Btest test fixed point, will require snd test program, as small LUT-RAM32 memory tidy out old symlinks for 00README 0FAQ *.tar.gz Milestone-* archive and announce 4th milestone do first KLAD tests, as now only UUO/float/byte/IO missing for many different tests, allow Mem/Fmem reload without recompiling design separate program for this, for faster prog tests, no rebuild logic or better use "vm" from VirtexTools (3th milestone) for this for larger test programs make 512 or 1024 (2 cols zizzag) word BRAM memory BRAMs fixed output FFs require support for memory wait states or possibly some inverse clock trick, so that it registers at 1/2 cycle rework memory loading, no fixed for (memsize), but while (lines) or better directly use "vm -b" from VirtexTools (4th milestone) for this archive and announce 5th milestone instruction unit 111dddddd.dooo input/output get into PDP-10 IO device and interrupts stuff internal processor control "IO"s memory managment "IO"s get into PDP-10 memory management, system/monitor mode stuff instruction unit 000mooooo local/monitor user unimplemented ops study use of IOBs for external hardware board spec wait for comments from Andrew get real hardware board study download/readback of bitfiles, make dl/ro tools, remote BoardScope external memory, but no BoardScope testing possible any more LEDs&switches (indicator panel and operators console) for debugging RS232 console tty PTR using RS232, or PTR or DECTape using FD to boot HD (ATA/EIDE or SCSI) further user ttys instruction unit 001xxxxxx floating point operations faster microengine, fast mem multi-port read and hidden write KA-10 has facultative fast mem between Mem and Mam, just access time speedup KI-10 can access both Mem and fast mem same time, cut read cycles IR.AC and IR.X addressed data always direct from fast mem, no MDRM delay present Hword implementation may screw up here, how it missuses MO reg also investigate Hword first/second naming inconsistency logic for SETZ/A/M doesn't need memory read, optimise away or use 0,,E only PC and MA through MAM to mem, MAM/IR.AC/IR.X through FMAM direct f m second data bus to places using C(AC), ev muxes for select C(AC)/C(E) if MAM not in range 00..17, read/write regs at same time as memory no need for Arith temporary register any more "both" same speed as "mem" write FPGA with 3 read ports for C(PC/MA),C(IR.X),C(IR.AC) and separate write port C(AC) direct, no FMAM delay and no control logic space and delay C(AC) and C(MA) need 2 different input ports, do not share MemData C(IR.X) direct, to conditional add to MA, no FMAM and memory/fast test direct use of Y+C(IR.X) as MA, no wasted cycle for writeback first but writeback anyway, else write register before C(MA) changes MA if IR.I and C(C(MA))) no IR.X or IR.I, extra Mux output direct to Memaddr for writing fast mem extra MA/IR.AC addr mux, are only write addr sources write behind pipelining, while already next C(PC) instr fetch PC pipelining, 4/5-stage pipelining, scoreboarding, register bypassing re-name ARs to pipeline stage registers, dito Arith and second Arith anything KL/XKL, extended addressing, addition instr, no string, no G float bluesky expansion ideas console terminal using keyboard and monitor (VT05 or VT52 or VT100 clone) show operators console at bottom of console terminal display switch for console and multiple user ttys, multisession terminal, windowing terminal with mouse and bitmap with fast IO or even bitmap DMA from memory S/390 style LPARs or support for CP/67 and VM/370 style VMs, for mult OSes would allow TOPS-10 and TOPS-20 and ITS and ... all at the same time linking multiple redundant processors, disks and IO, preferably hotswap together with LPARs or VMs this gives virtual rackspace servers find name for this processor, presently best suggestion KF-10 in NF-10 system done: understanding Virtex FPGA and Java language and JBits toolkit and PDP-10 architecture, as far as user instructions go implemented are so far are LUT logic and place-and-routing of data path and control circuits and state machine for: temporary memory (32 words, at address 020..057) with system to load memory with test programs and data fast memory (16 words, at address 000..017) memory data read mux to select input data between the 2 memories address mux to select PC/IR.X/IR.AC/MA to address memory program counter PC and its incrementer/jump load mux instruction register IR and instruction loading, modifying IR.X, .I and .MA with central instruction execution finite state machine (FSM) memory address MA register and 0,,E calculation, consuming IR.X and IR.I arithmetic register AR for temporary holding C(E) or C(AC) input parameters immediate data selection mux for AR (C(E) or C(AC)) vs MA (0,,E) memory data write mux with one in port for each of 8 the instruction groups instruction unit 100ffffmm boolean logic, data path and mode execution FSM instruction unit 011tttmmm arithmetic testing, data path and mode exec FSM instruction unit 101tootmm half word, data path and mode execution FSM instruction unit 110ooamma bit testing, data path and mode execution FSM