http://neil.franklin.ch/Projects/PDP-10/FAQ author Neil Franklin, last modification 2002.10.30 Frequently* Asked Questions (FAQ) for the PDP-10 FPGA clone project * not really frequent, but that is what such files are called Q: Why are you building an microprocessor? A: Because I have since about 15 years liked processor design. I have always wanted to build an processor. But before FPGAs building hardware was a lot of work, with hundreds of parts, soldering. And with TTL it would be slow (from all that wiring) and require heavy power supply. FPGAs have turned it into an programming job, and made fast and small stuff possible. Also they fit my experimental iterative design methodology better (no rewiring). Q: What is a PDP-10? A: A large 36bit (not 32bit!) computer built by DEC (Digital Equipment Corporation) in various models between 1963 and mid 1980s, and cloned by multiple companies (Foonley, SC, XKL), some still producing today. Has what is considered by many to be the most elegant instruction set ever designed. Q: Why make an PDP-10, why not something more modern? A: I could make yet annother RISC processor (YARP), but I would be the only user, as there are already a few of these around. I could make an PDP-8 or PDP-11, but there exist good and fast emulators for these, and these processors are only good for toys or historical value today. An PDP-10 hardware implementation can actually be used as an productive system, and there are people who would like to do that. While the first year of this project 3 PDP-10 emulators (TS10, SIMH, KLH10) have become available (E10 has died), so this is less pressing now, but some would still like an pure hardware 10, without an host OS underneath it. Q: What PDP-10 are you making A: Where ever the models differ, I will have to chose compatibility with one specific model. Initially, to reduce time to first usable version, I will aim for the simplest, an KA-10. Initially this will be an model 1040 (DECTape only, using an floppy as "tape") or an model 1050 (with IDE disks as Massbus). This should be full binary compatible for using an unchanged OS. Then for paging an KI-10 in model 1070 configuration is taken as canonical. This one may be only near compatible, to avoid the chip space cost of having 4 times the 16 registers. From then on random KL-10 or even XKL-1 features will be added. Q: Why an KA-10 or KI-10, why not an KL-10 (like E10 emulator) or KS-10 (like TS-10)? A: Because KI-10 is the last "real" 10, implemented in state logic, with an real (blinkenlights) console and directly connected user terminals. The KL-10 was already an microcoded system. It had some crufty instructions (string stuff), used an PDP-11 FEP as console and further PDP-11s to connect to its users. Note, that I intend to later add some KL-10 extensions, particularly its multi-section extended addressing (even up to XKL-1 30bit wide), so that large programs can be run. But it will stay an KI-10 style state machine structure, possibly extended with an trap&emulate sytem to save logic usage, like the IBM 360/44 and 360/91 did it. Q: Is this an hardware design, or another software layer design? A: Hardware. To be more precise I will be mainly working on developing an FPGA configuration file. This is equivalent to an module list plus wiring list for wiring standard TTL (or the original DEC 1960s Flipchip) logic. Q: What is this FPGA stuff? A: For an basic description of what FPGAs are, read in my Usenet archive: http://neil.franklin.ch/Usenet/alt.sys.pdp10/20001231_PDP_10_in_an_FPGA_chip_starting from the line: Message-ID: <6un1d98vl6.fsf@chonsp.franklin.ch> onwards. Or look at the the chip design graphic and description at: http://neil.franklin.ch/Projects/PDP-10/pdp10.vv.html Q: Why are you using hardwired logic and trap&emulate, why not microcode? A: Because this is ideal for FPGA implementation. Hardwiring large finite state machines (FSMs), particularly in one-hot implementation, is easy, due to relatively abundant FFs in the chip. Internal microcode ROMs will not fit and external ones cost chip pins (which are relatively scarse) and IO transactions (which are relatively slow). Trap&emulating on complex instructions at least uses the standard RAM pins and only costs speed on the seldom used complex instructions, not on all others. And being only a few instructions it may even fit into on-chip ROM, like the Pentium doing some CISCy x86 instructions in microcode for its internal RISC machine. Quite apart from this, microcoding was an technology to shift complexity from single gates (high volume and cost) to ROM (compact and cheap), at cost of slower execution. FPGAs automatically shift complexity into programmable logic and its config ROM/RAM, so why waste the speed. Q: What will be trap&emulated? A: Presently I expect this to be floating point (a la Intel 386 without 387, this was also an option on the real KA-10), the commercial instructions (MOVS*, CMPS*, CVT*, EDIT). Possibly also some IO device internal implementations (such as disk controller translation to SCSI or EIDE, or console terminal internal processing). This is still an entirely open issue. Q: Will this processor do SMP? A: Initially not. But I am leaving this open as an possible extension. With todays fast memories I will not be having the KL-10s cache SMP problems. And even if I need to cache each processor, I can use Pentium-style MESI stuff. OTOH this processor can be up to 10-30 times KL10 speed, and used by an single user (mostly single process active), so SMP is not at all important. Q: Why are you using Xilinx Virtex and JBits, why not VHDL or Verilog? A: JBits is the only tool available for Linux. It is also a lot faster than VHDL or Verilog (compile times in seconds..minutes, not hours). Also I like Assembly language level working and I regard JBits as FPGA Assembler, while I looked at VHDL and Verilog and failled to comprehend them. The choice of JBits does limit the FPGA chip choice to Virtex or size compatible Spartan-II models. But those are among the better FPGAs anyway. Q: What are you using as memory? A: Either 4bit wide or 8bit wide async SRAMs, 18bit wide ZBT SRAMs, or (fairly unlikely) 36bit wide 72-pin SIMM DRAMs. This really is still an totally open issue, partially also dependant on which prototyping board I use, and how many FPGA pins I have free. Q: Will there be parity or CRC/Hamming ECC? A: No need for it with todays memory chips. Save worktime and FPGA space for other features. Also I simply do not know the required maths. Of course as the project is open source, anyone who wants ECC can add it. Q: What are you using for IO? A: Initially an LEDs and buttons operators console, RS232 for an VT100 and for an simulated PTR. Then an floppy drive as pretended DECtape and/or an IDE or SCSI hard disk as pretended Massbus drive. Then PC keyboard and VGA monitor as terminal or Ethernet will be added. From then on the further course is open. Q: What are you using as FPGA board? A: Initially an prefabribated commercial prototype board with application specific extensions (memory, disk interface, possibly operators console) to save work (time) and make it easier for others to follow the project. I may one day make custom hardware, but at the moment do not intend to. I am collecting my ideas for such custom hardware: http://neil.franklin.ch/Projects/PDP-10/Hardware Q: What OS will you be aiming for? A: Initially TOPS-10 6.03 or ITS, unmodified versions for KA-10. Later, with extended addressing, TOPS-20, or even an port of Linux or NetBSD are possible. Q: Where can I get code? A: The newest (read: in edit, sometimes not functional) from: http://neil.franklin.ch/Projects/PDP-10/ or as .tar.gz as: http://neil.franklin.ch/Projects/VirtexTools.tar.gz Various milestones (read: archives, working) from: http://neil.franklin.ch/Projects/PDP-10-/ or as .tar.gz as: http://neil.franklin.ch/Projects/VirtexTools-.tar.gz