PDP-10-20020625/ 0000755 0001755 0001755 00000000000 07557631203 011277 5 ustar neil neil PDP-10-20020625/index.html.de 0000777 0001755 0001755 00000000000 10342642375 016254 2index.html.en ustar neil neil PDP-10-20020625/index.html.en 0000644 0001755 0001755 00000017220 07506170534 013676 0 ustar neil neil
This is actual hardware (clone), as opposed to software (emulators), such as ts10 or SIMH or KLH10.
ASCII art of Virtex CLB PIPs
list of Virtex BRAM PIPs
Pinout Xess XC40-010E board
Pinout Xess XSV board
Pinout APS V240 board
My alt.sys.pdp10 archive
Early discussion of cloning an PDP-10 in an FPGA
Announcing this project
Modern IO devices for PDP-10 on a FPGA
Who is working on PDP10 hardware emulators/fpgas?
Links to PDP-10 Emulation Webpages
Doug Conroy's PDP-4 done, mentions his PDP-10 plans
Discussion of emulating/replacing IO devices
PDP-10 index, 36 bits forever!
DEC 36-bit computers
DECsystem-10/DECSYSTEM-20 Processor Reference Manual
DEC PDP-10
PDP-10 Software Archive
Project: ts10 (KS-10, KL-10, VAX)
SIMH (many systems, including PDP-10)
KLH10 (KL-10, KS-10, with NIA20 networking)
SPARTAN2+ FPGA Prototyping Kit, the board I am going to use
This page is by Neil Franklin, last modification 2002.06.25
PDP-10-20020625/00README 0000644 0001755 0001755 00000004411 07431537044 012316 0 ustar neil neil http://neil.franklin.ch/Projects/PDP-10/00README
author Neil Franklin, last modification 2002.02.10
Introduction to my PDP-10 FPGA clone microprocesor project
Aim
To make an PDP-10 compatible processor clone in an FPGA chip. In cases where
model specific differences are relevant, I will for fast initial success
implement compatibility with KA-10, the simplest model. Later extensions will
include to near KI-10 compatibility (paging, but ev no 4*16 registers), and
then partial KL-10 functionality (extended addressing, cache, definitely no
G-Float (KL10-D only anyway) and fairly shure no string stuff), and then go
above with some XKL-1 (fully extended addressing).
The FPGA should contain all components need to run an full PDP-10 OS, initially
TOPS-10 and/or ITS, later TOPS-20 and/or other. Presently I plan that to be:
processor, memory (external to FPGA), console terminal on chip (using PC
keyboard and VGA monitor), "paper tape" reader for booting (using RS232 from
PC), some form of hard disk controller/device. Later extensions may include
bitmapped video IO for desktop workstation style use, or Ethernet for remote
login or server style use.
Also I intend to implement the console operators panel and indicator lights,
but it shall be optional for users who want to avoid the costs (money, time
wiring it, space). Possibly I will make an console panel and indicator pannels
on the console terminal monitor.
Tools
I will be using the Xilinx Virtex or Spartan-II chips. Initial target is
XCV300 or XC2S200. They will be programmed using the JBits toolset. JBits
is an Java .class library offering an API to modify Virtex configuration
bitstream files, so my code will be Java code calling JBits functions.
I will be working on an Linux/x86 system, but due to the use of Java the
project should be fully portable to any system with Java 1.2 or newer.
Code
This project is fully open source. Everything I write is immediately available
for download. If I write a bug you crash the next day. Documentation gets
written together with the code.
State
The work, as far as it has progressed, is documented in an Logfile that is
updated whenever I do something:
http://neil.franklin.ch/Projects/PDP-10/Logfile
Questions
There is a FAQ file at:
http://neil.franklin.ch/Projects/PDP-10/0FAQ
PDP-10-20020625/0FAQ 0000644 0001755 0001755 00000017305 07431540244 011712 0 ustar neil neil http://neil.franklin.ch/Projects/PDP-10/0FAQ
author Neil Franklin, last modification 2002.02.10
Frequently* Asked Questions (FAQ) for the PDP-10 FPGA clone project
* not really frequent, but that is what such files are called
Q: Why are you building an microprocessor?
A: Because I have since about 15 years liked processor design. I have always
wanted to build an processor. But before FPGAs building hardware was a lot
of work, with hundreds of parts, soldering. And with TTL it would be slow
(from all that wiring) and require heavy power supply. FPGAs have turned it
into an programming job, and made fast and small stuff possible. Also they
fit my experimental iterative design methodology better (no rewiring).
Q: What is a PDP-10?
A: A large 36bit (not 32bit!) computer built by DEC (Digital Equipment
Corporation) in various models between 1963 and mid 1980s, and cloned by
multiple companies (Foonley, SC, XKL), some still producing today. Has what
is considered by many to be the most elegant instruction set ever designed.
Q: Why make an PDP-10, why not something more modern?
A: I could make yet annother RISC processor (YARP), but I would be the only
user, as there are already a few of these around.
I could make an PDP-8 or PDP-11, but there exist good and fast emulators
for these, and these processors are only good for toys or historical value
today. An PDP-10 hardware implementation can actually be used as an
productive system, and there are people who would like to do that.
While the first year of this project 3 PDP-10 emulators (TS10, SIMH, KLH10)
have become available (E10 has died), so this is less pressing now, but some
would still like an pure hardware 10, without an host OS underneath it.
Q: What PDP-10 are you making
A: Where ever the models differ, I will have to chose compatibility with one
specific model. Initially, to reduce time to first usable version, I will
aim for an KA-10. Initially this will be an model 1040 (DECTape only, using
an floppy as "tape") or an model 1050 (with IDE disks as Massbus). This
should be full binary compatible for using an unchanged OS. Then for paging
an KI-10 in model 1070 configuration is taken as canonical. This one may be
only near compatible, to avoid the chip space cost of having 4 times the 16
registers. From then on random KL-10 or even XKL-1 features will be added.
Q: Why an KA-10 or KI-10, why not an KL-10 (like E10 emulator) or KS-10 (like
TS-10)?
A: Because KI-10 is the last "real" 10, implemented in state logic, with an
real (blinkenlights) console and directly connected user terminals. The
KL-10 was already an microcoded system. It had some crufty instructions
(string stuff), used an PDP-11 FEP as console and further PDP-11s to connect
to its users. Note, that I intend to later add some KL-10 extensions,
particularly its multi-section extended addressing (even up to XKL-1 30bit
wide), so that large programs can be run. But it will stay an KI-10 style
state machine structure, possibly extended with an trap&emulate sytem to
save logic usage, like the IBM 360/44 and 360/91 did it.
Q: Is this an hardware design, or another software layer design?
A: Hardware. To be more precise I will be mainly working on developing an FPGA
configuration file. This is equivalent to an module list plus wiring list
for wiring standard TTL (or the original DEC 1960s Flipchip) logic.
Q: What is this FPGA stuff?
A: For an basic description of what FPGAs are, read in my Usenet archive:
http://neil.franklin.ch/Usenet/alt.sys.pdp10/20001231_PDP_10_in_an_FPGA_chip_starting
from the line: Message-ID: <6un1d98vl6.fsf@chonsp.franklin.ch> onwards.
Q: Why are you using hardwired logic and trap&emulate, why not microcode?
A: Because this is ideal for FPGA implementation. Hardwiring large finite state
machines (FSMs), particularly in one-hot implementation, is easy, due to
relatively abundant FFs in the chip.
Internal microcode ROMs will not fit and external ones cost chip pins (which
are relatively scarse) and are slow. Trap&emulating on complex instructions
at least uses the standard RAM pins and only costs speed on the seldom used
complex instructions, not on all others. And being only a few instructions
it may even fit into on-chip ROM, like the Pentium doing some CISCy x86
instructions in microcode for its internal RISC machine.
Quite apart from this, microcoding was an technology to shift complexity
from single gates (high volume and cost) to ROM (compact and cheap), at cost
of slower execution. FPGAs automatically shift complexity into programmable
logic and its config ROM/RAM, so why waste the speed.
Q: What will be trap&emulated?
A: Presently I expect this to be floating point (a la Intel 386 without 387,
this was also an option on the real KA-10), the commercial instructions
(MOVS*, CMPS*, CVT*, EDIT). Possibly also some IO device internal
implementations (such as disk controller translation to SCSI or EIDE, or
console terminal internal processing). This is still an open issue.
Q: Will this processor do SMP?
A: Initially not. But I am leaving this open as an possible extension. With
todays fast memories I will not be having the KL-10s cache SMP problems.
And even if I need to cache each processor, I can use Pentium-style MESI
stuff.
OTOH this processor will be 10-30 times KL10 speed, and used by an single
user (mostly single process active), so SMP is not at all important.
Q: Why are you using Xilinx Virtex and JBits, why not VHDL or Verilog?
A: JBits is the only tool available for Linux. It is also a lot faster than
VHDL or Verilog (compile times in seconds..minutes, not hours). Also I
like Assemly language level working and I regard JBits as FPGA Assembler.
The choice of JBits does limit the FPGA chip choice to Virtex or size
compatible Spartan-II models. But those are among the better FPGAs anyway.
Q: What are you using as memory?
A: Either 4bit wide or 8bit wide async SRAMs, 18bit wide ZBT SRAMs, or (fairly
unlikely) 36bit wide 72-pin SIMM DRAMs.
This really is still an totally open issue, partially also dependant on
which prototyping board I use, and how many FPGA pins I have.
Q: Will there be parity or CRC/Hamming ECC?
A: No need for it with todays memory chips. Save worktime and FPGA space for
other features. Also I simply do not know the required maths. Of course as
the project is open source, anyone who wants ECC can add it.
Q: What are you using for IO?
A: Initially an LEDs and buttons operators console, RS232 for an VT100 and
for an simulated PTR. Then an floppy drive as pretended DECtape and/or
an IDE or SCSI hard disk as pretended Massbus drive. Then PC keyboard and
VGA monitor as terminal or Ethernet will be added. From then on the further
course is open.
Q: What are you using as FPGA board?
A: Initially an prefabribated commercial prototype board with application
specific extensions (memory, disk interface, possibly operators console)
to save work (time) and make it easier for others to follow the project.
I may one day make custom hardware, but at the moment do not intend to.
I am collecting my ideas for such custom hardware:
http://neil.franklin.ch/Projects/PDP-10/Hardware
Q: What OS will you be aiming for?
A: Initially TOPS-10 6.03 or ITS, unmodified versions for KA-10.
Later, with extended addressing, TOPS-20, or even an port of Linux or
NetBSD are possible.
Q: Where can I get code?
A: The newest (read: in edit, sometimes not functional) from:
http://neil.franklin.ch/Projects/PDP-10/*.java
Various milestones (read: archives, working) from:
http://neil.franklin.ch/Projects/PDP-10-
A LUT (Look Up Table) is an programmable logic
element, that has 4 inputs that are evaluated to generate 1
output. Evaluation consists of regarding the 4 inputs as an 4bit
number (gives range: 0..15) and using that as index into an 16 line
table containing 1 (output) bit per line.
This graphic shows an grid of 4x4 (= 16) pixel graphics
representing the 16 bits of each look up table, bit 0..3 shown at top
left->right, 12..15 at bottom left->right. The actual table values are
also available as listing of place and 16bit hex
number. The Java code that generated them is here.
Different logic functions require different tables to implement
them, which then appear here as different 4x4 patterns. (Groups
of) identical logic functions appear as (groups of) same
patterns.
The programmable wiring from LUT outputs to inputs, and
the facultative register storage elements after each LUT
are not shown.
Due to the way Xilinx wires their FPGA chips, functional
complexity runs left<->right (with some exeptions), and
bit depth repetition runs top<->bottom, with the
LSB at bottom and MSB at top.
I have placed the data path at the bottom of the chip,
using rows 000F..017G. The 36 times repeated indentical functions
appear as vertical (column/slice) lines. Relative to the
2nd milestone the unused
columns due to inefficient placing method have disappeared, because I
implemented an new position independant coding style and
following that an automatic placing algorithm.
Above these 36 rows appear the control circuits that tell
the data path what function it is to do in the present step of execution.
They are placed in the same column as the part of the data path
that they control. The use of only F has also disappeared with the new
placing system. Any remaining holes are due to avoiding trouble with the
wiring program which gets indigestion in some dense places.
This page is by Neil Franklin, last modification 2002.10.29
PDP-10-20020625/pdp10.bit 0000644 0001755 0001755 00000653647 07506124247 012747 0 ustar neil neil a null300.ncd b
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l > > > > > > > >P ? ? ? ? ? ? ? ?p ? ? ? ? ? ? ? ? . . . . . . . .0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0p . . . . . . . .` @ > > > > > > > >p ? ? ? ? ? ? ? ? ` @ > > > > > > > > , . . . . . . . . @ L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -x -x -x -x -x -x -x -x @ H <0 <0 <0 <0 <0 <0 <0 <0 @ ? ? ? ? ? ? ? ?` > > > > > > > > p H -p -p -p -p -p -p -p -p` -x -x -x -x -x -x -x -x H ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 ? ? ? ? ? ? ? ?` H > > > > > > > > 0 >@ >@ >@ >@ >@ >@ >@ >@0 ` . . . . . . . . . . . . . . . . @ , , , , , , , ,
` > > > > > > > > P ? ? ? ? ? ? ? ? p ? ? ? ? ? ? ? ? p 8 . . . . . . . . 0 , , , , , , , , p . . . . . . . . ` > > > > > > > > p ( >@ >@ >@ >@ >@ >@ >@ >@ ` ( > > > > > > > > (8 / / / / / / / / @ (L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -p -p -p -p -p -p -p -p @ =x =x =x =x =x =x =x =x > > > > > > > >` ? ? ? ? ? ? ? ? p -p -p -p -p -p -p -p -p` -p -p -p -p -p -p -p -p ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 > > > > > > > >` > > > > > > > > 0 ? ? ? ? ? ? ? ?D0 l . . . . . . . .@ , . . . . . . . . @ ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0
l > > > > > > > >P ? ? ? ? ? ? ? ?p ? ? ? ? ? ? ? ? . . . . . . . .0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0p . . . . . . . .` @ > > > > > > > >p ? ? ? ? ? ? ? ? ` @ > > > > > > > > , . . . . . . . . @ L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -x -x -x -x -x -x -x -x @ H <0 <0 <0 <0 <0 <0 <0 <0 @ ? ? ? ? ? ? ? ?` > > > > > > > > p H -p -p -p -p -p -p -p -p` -x -x -x -x -x -x -x -x H ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 ? ? ? ? ? ? ? ?` H > > > > > > > > 0 >@ >@ >@ >@ >@ >@ >@ >@0 ` . . . . . . . . . . . . . . . . @ , , , , , , , ,
` > > > > > > > > P ? ? ? ? ? ? ? ? p ? ? ? ? ? ? ? ? p 8 . . . . . . . . 0 , , , , , , , , p . . . . . . . . ` > > > > > > > > p ( >@ >@ >@ >@ >@ >@ >@ >@ ` ( > > > > > > > > (8 / / / / / / / / @ (L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -p -p -p -p -p -p -p -p @ =x =x =x =x =x =x =x =x > > > > > > > >` ? ? ? ? ? ? ? ? p -p -p -p -p -p -p -p -p` -p -p -p -p -p -p -p -p ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 > > > > > > > >` > > > > > > > > 0 ? ? ? ? ? ? ? ?D0 l . . . . . . . .@ , . . . . . . . . @ ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0
l > > > > > > > >P ? ? ? ? ? ? ? ?p ? ? ? ? ? ? ? ? . . . . . . . .0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0p . . . . . . . .` @ > > > > > > > >p ? ? ? ? ? ? ? ? ` @ > > > > > > > > , . . . . . . . . @ L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -x -x -x -x -x -x -x -x @ H <0 <0 <0 <0 <0 <0 <0 <0 @ ? ? ? ? ? ? ? ?` > > > > > > > > p H -p -p -p -p -p -p -p -p` -x -x -x -x -x -x -x -x H ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 ? ? ? ? ? ? ? ?` H > > > > > > > > 0 >@ >@ >@ >@ >@ >@ >@ >@0 ` . . . . . . . . . . . . . . . . @ , , , , , , , ,
` > > > > > > > > P ? ? ? ? ? ? ? ? p ? ? ? ? ? ? ? ? p 8 . . . . . . . . 0 , , , , , , , , p . . . . . . . . ` > > > > > > > > p ( >@ >@ >@ >@ >@ >@ >@ >@ ` ( > > > > > > > > (8 / / / / / / / / @ (L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -p -p -p -p -p -p -p -p @ =x =x =x =x =x =x =x =x > > > > > > > >` ? ? ? ? ? ? ? ? p -p -p -p -p -p -p -p -p` -p -p -p -p -p -p -p -p ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 > > > > > > > >` > > > > > > > > 0 ? ? ? ? ? ? ? ?D0 l . . . . . . . .@ , . . . . . . . . @ ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0
l > > > > > > > >P ? ? ? ? ? ? ? ?p ? ? ? ? ? ? ? ? . . . . . . . .0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0p . . . . . . . .` @ > > > > > > > >p ? ? ? ? ? ? ? ? ` @ > > > > > > > > , . . . . . . . . @ L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -x -x -x -x -x -x -x -x @ H <0 <0 <0 <0 <0 <0 <0 <0 @ ? ? ? ? ? ? ? ?` > > > > > > > > p H -p -p -p -p -p -p -p -p` -x -x -x -x -x -x -x -x H ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 ? ? ? ? ? ? ? ?` H > > > > > > > > 0 >@ >@ >@ >@ >@ >@ >@ >@0 ` . . . . . . . . . . . . . . . . @ , , , , , , , ,
` > > > > > > > > P ? ? ? ? ? ? ? ? p ? ? ? ? ? ? ? ? p 8 . . . . . . . . 0 , , , , , , , , p . . . . . . . . ` > > > > > > > > p ( >@ >@ >@ >@ >@ >@ >@ >@ ` ( > > > > > > > > (8 / / / / / / / / @ (L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -p -p -p -p -p -p -p -p @ =x =x =x =x =x =x =x =x > > > > > > > >` ? ? ? ? ? ? ? ? p -p -p -p -p -p -p -p -p` -p -p -p -p -p -p -p -p ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 > > > > > > > >` > > > > > > > > 0 ? ? ? ? ? ? ? ?D0 l . . . . . . . .@ , . . . . . . . . @ ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0
l > > > > > > > >P ? ? ? ? ? ? ? ?p ? ? ? ? ? ? ? ? . . . . . . . .0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0p . . . . . . . .` @ > > > > > > > >p ? ? ? ? ? ? ? ? ` @ > > > > > > > > , . . . . . . . . @ L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -x -x -x -x -x -x -x -x @ H <0 <0 <0 <0 <0 <0 <0 <0 @ ? ? ? ? ? ? ? ?` > > > > > > > > p H -p -p -p -p -p -p -p -p` -x -x -x -x -x -x -x -x H ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 ? ? ? ? ? ? ? ?` H > > > > > > > > 0 >@ >@ >@ >@ >@ >@ >@ >@0 ` . . . . . . . . . . . . . . . . @ , , , , , , , ,
` > > > > > > > > P ? ? ? ? ? ? ? ? p ? ? ? ? ? ? ? ? p 8 . . . . . . . . 0 , , , , , , , , p . . . . . . . . ` > > > > > > > > p ( >@ >@ >@ >@ >@ >@ >@ >@ ` ( > > > > > > > > (8 / / / / / / / / @ (L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -p -p -p -p -p -p -p -p @ =x =x =x =x =x =x =x =x > > > > > > > >` ? ? ? ? ? ? ? ? p -p -p -p -p -p -p -p -p` -p -p -p -p -p -p -p -p ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 > > > > > > > >` > > > > > > > > 0 ? ? ? ? ? ? ? ?D0 l . . . . . . . .@ , . . . . . . . . @ ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0
l > > > > > > > >P ? ? ? ? ? ? ? ?p ? ? ? ? ? ? ? ? . . . . . . . .0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0p . . . . . . . .` @ > > > > > > > >p ? ? ? ? ? ? ? ? ` @ > > > > > > > > , . . . . . . . . @ L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -x -x -x -x -x -x -x -x @ H <0 <0 <0 <0 <0 <0 <0 <0 @ ? ? ? ? ? ? ? ?` > > > > > > > > p H -p -p -p -p -p -p -p -p` -x -x -x -x -x -x -x -x H ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 ? ? ? ? ? ? ? ?` H > > > > > > > > 0 >@ >@ >@ >@ >@ >@ >@ >@0 ` . . . . . . . . . . . . . . . . @ , , , , , , , ,
` > > > > > > > > P ? ? ? ? ? ? ? ? p ? ? ? ? ? ? ? ? p 8 . . . . . . . . 0 , , , , , , , , p . . . . . . . . ` > > > > > > > > p ( >@ >@ >@ >@ >@ >@ >@ >@ ` ( > > > > > > > > (8 / / / / / / / / @ (L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -p -p -p -p -p -p -p -p @ =x =x =x =x =x =x =x =x > > > > > > > >` ? ? ? ? ? ? ? ? p -p -p -p -p -p -p -p -p` -p -p -p -p -p -p -p -p ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 > > > > > > > >` > > > > > > > > 0 ? ? ? ? ? ? ? ?D0 l . . . . . . . .@ , . . . . . . . . @ ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0
l > > > > > > > >P ? ? ? ? ? ? ? ?p ? ? ? ? ? ? ? ? . . . . . . . .0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0p . . . . . . . .` @ > > > > > > > .p ? ? ? ? ? ? ? ? ` @ > > > > > > > > , . . . . . . . . @ L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -x -x -x -x -x -x -x -x @ H <0 <0 <0 <0 <0 <0 <0 <0 @ ? ? ? ? ? ? ? ?` > > > > > > > > p H -p -p -p -p -p -p -p -p` -x -x -x -x -x -x -x -x H ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 ? ? ? ? / ? ? ?` H > > > > > > > > 0 >@ >@ >@ >@ >@ >@ >@ >@0 ` . . . . . . . . . . . . . . . . @ , , , , , , , ,
` > > > > > > > > P ? ? ? ? ? ? ? ? p ? ? ? ? ? ? ? ? p 8 . . . . . . . . 0 , , , , , , , , p . . . . . . . . ` > > > > . > > > p ( >@ >@ >@ >@ >@ >@ >@ >@ ` ( > > > > > > > > (8 / / / / / / / / @ (L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -p -p -p -p -p -p -p -p @ =x =x =x =x =x =x =x =x > > > > > > > >` ? ? ? ? ? ? ? ? p -p -p -p -p -p -p -p -p` -p -p -p -p -p -p -p -p ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 > > > > > > > >` > > > > > > > > 0 ? ? ? ? ? ? ? ?D0 l . . . . . . . .@ , . . . . . . . . @ ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0
l > > > > > > > >P ? ? ? ? ? ? ? ?p ? ? ? ? ? ? ? ? . . . . . . . .0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0p . . . . . . . .` @ > > > > > > > >p ? ? ? ? ? ? ? ? ` @ > > > > > > > > , . . . . . . . . @ L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -x -x -x -x -x -x -x -x @ H <0 <0 <0 <0 <0 <0 <0 <0 @ ? ? ? ? ? ? ? ?` > > > > > > > > p H -p -p -p -p -p -p -p -p` -x -x -x -x -x -x -x -x H ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 ? ? ? ? ? ? ? ?` H > > > > > > > > 0 >@ >@ >@ >@ >@ >@ >@ >@0 ` . . . . . . . . . . . . . . . . @ , , , , , , , ,
` > > > > > > > > P ? ? ? ? ? ? ? ? p ? ? ? ? ? ? ? ? p 8 . . . . . . . . 0 , , , , , , , , p . . . . . . . . ` > > > > > > > > p ( >@ >@ >@ >@ >@ >@ >@ >@ ` ( > > > > > > > > (8 / / / / / / / / @ (L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -p -p -p -p -p -p -p -p @ =x =x =x =x =x =x =x =x > > > > > > > >` ? ? ? ? ? ? ? ? p -p -p -p -p -p -p -p -p` -p -p -p -p -p -p -p -p ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 > > > > > > > >` > > > > > > > > 0 ? ? ? ? ? ? ? ?D0 l . . . . . . . .@ , . . . . . . . . @ ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0
l > > > > > > > >P ? ? ? ? ? ? ? ?p ? ? ? ? ? ? ? ? . . . . . . . .0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0p . . . . . . . .` @ > > > > > > > >p ? ? ? ? ? ? ? ? ` @ > > > > > > > > , . . . . . . . . @ L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -x -x -x -x -x -x -x -x @ H <0 <0 <0 <0 <0 <0 <0 <0 @ ? ? ? ? ? ? ? ?` > > > > > > > > p H -p -p -p -p -p -p -p -p` -x -x -x -x -x -x -x -x H ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 ? ? ? ? ? ? ? ?` H > > > > > > > > 0 >@ >@ >@ >@ >@ >@ >@ >@0 ` . . . . . . . . . . . . . . . . @ , , , , , , , ,
` > > > > > > > > P ? ? ? ? ? ? ? ? p ? ? ? ? ? ? ? ? p 8 . . . . . . . . 0 , , , , , , , , p . . . . . . . . ` > > > > > > > > p ( >@ >@ >@ >@ >@ >@ >@ >@ ` ( > > > > > > > > (8 / / / / / / / / @ (L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -p -p -p -p -p -p -p -p @ =x =x =x =x =x =x =x =x > > > > > > > >` ? ? ? ? ? ? ? ? p -p -p -p -p -p -p -p -p` -p -p -p -p -p -p -p -p ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 > > > > > > > >` > > > > > > > > 0 ? ? ? ? ? ? ? ?D0 l . . . . . . . .@ , . . . . . . . . @ ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0
l > > > > > > > >P ? ? ? ? ? ? ? ?p ? ? ? ? ? ? ? ? . . . . . . . .0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0p . . . . . . . .` @ > > > > > > > >p ? ? ? ? ? ? ? ? ` @ > > > > > > > > , . . . . . . . . @ L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -x -x -x -x -x -x -x -x @ H <0 <0 <0 <0 <0 <0 <0 <0 @ ? ? ? ? ? ? ? ?` > > > > > > > > p H -p -p -p -p -p -p -p -p` -x -x -x -x -x -x -x -x H ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 ? ? ? ? ? ? ? ?` H > > > > > > > > 0 >@ >@ >@ >@ >@ >@ >@ >@0 ` . . . . . . . . . . . . . . . . @ , , , , , , , ,
` > > > > > > > > P ? ? ? ? ? ? ? ? p ? ? ? ? ? ? ? ? p 8 . . . . . . . . 0 , , , , , , , , p . . . . . . . . ` > > > > > > > > p ( >@ >@ >@ >@ >@ >@ >@ >@ ` ( > > > > > > > > (8 / / / / / / / / @ (L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -p -p -p -p -p -p -p -p @ =x =x =x =x =x =x =x =x > > > > > > > >` ? ? ? ? ? ? ? ? p -p -p -p -p -p -p -p -p` -p -p -p -p -p -p -p -p ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 > > > > > > > >` > > > > > > > > 0 ? ? ? ? ? ? ? ?D0 l . . . . . . . .@ , . . . . . . . . @ ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0
l > > > > > > > >P ? ? ? ? ? ? ? ?p ? ? ? ? ? ? ? ? . . . . . . . .0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0p . . . . . . . .` @ > > > > > > > >p ? ? ? ? ? ? ? ? ` @ > > > > > > > > , . . . . . . . . @ L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -x -x -x -x -x -x -x -x @ H <0 <0 <0 <0 <0 <0 <0 <0 @ ? ? ? ? ? ? ? ?` > > > > > > > > p H -p -p -p -p -p -p -p -p` -x -x -x -x -x -x -x -x H ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 ? ? ? ? ? ? ? ?` H > > > > > > > > 0 >@ >@ >@ >@ >@ >@ >@ >@0 ` . . . . . . . . . . . . . . . . @ , , , , , , , ,
` > > > > > > > > P ? ? ? ? ? ? ? ? p ? ? ? ? ? ? ? ? p 8 . . . . . . . . 0 , , , , , , , , p . . . . . . . . ` > > > > > > > > p ( >@ >@ >@ >@ >@ >@ >@ >@ ` ( > > > > > > > > (8 / / / / / / / / @ (L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -p -p -p -p -p -p -p -p @ =x =x =x =x =x =x =x =x > > > > > > > >` ? ? ? ? ? ? ? ? p -p -p -p -p -p -p -p -p` -p -p -p -p -p -p -p -p ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 > > > > > > . >` > > > > > > > > 0 ? ? ? ? ? ? ? ?D0 l . . . . . . . .@ , . . . . . . . . @ ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0
l > > > > > > > >P ? ? ? ? ? ? ? ?p ? ? ? ? ? ? ? ? . . . . . . . .0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0p . . . . . . . .` @ > > > > > > > >p ? ? ? ? ? ? ? ? ` @ > > > > > > > > , . . . . . . . . @ L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -x -x -x -x -x -x -x -x @ H <0 <0 <0 <0 <0 <0 <0 <0 @ ? ? ? ? ? ? ? ?` > > > > > > > > p H -p -p -p -p -p -p -p -p` -x -x -x -x -x -x -x -x H ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 ? ? ? ? ? ? ? ?` H > > > > > > > > 0 >@ >@ >@ >@ >@ >@ >@ >@0 ` . . . . . . . . . . . . . . . . @ , , , , , , , ,
` > > > > > > > > P ? ? ? ? ? ? ? ? p ? ? ? ? ? ? ? ? p 8 . . . . . . . . 0 , , , , , , , , p . . . . . . . . ` > > > > > > > > p ( >@ >@ >@ >@ >@ >@ >@ >@ ` ( > > > > > > > > (8 / / / / / / / / @ (L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -p -p -p -p -p -p -p -p @ =x =x =x =x =x =x =x =x > > > > > > > >` ? ? ? ? ? ? ? ? p -p -p -p -p -p -p -p -p` -p -p -p -p -p -p -p -p ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 > > > > > > > >` > > > > > > > > 0 ? ? ? ? ? ? ? ?D0 l . . . . . . . .@ , . . . . . . . . @ ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0
l > > > > > > > >P ? ? ? ? ? ? ? ?p ? ? ? ? ? ? ? ? . . . . . . . .0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0p . . . . . . . .` @ > > > > > > > >p ? ? ? ? ? ? ? ? ` @ > > > > > > > > , . . . . . . . . @ L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -x -x -x -x -x -x -x -x @ H <0 <0 <0 <0 <0 <0 <0 <0 @ ? ? ? ? ? ? ? ?` > > > > > > > > p H -p -p -p -p -p -p -p -p` -x -x -x -x -x -x -x -x H ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 ? ? ? ? ? ? / ?` H > > > > > > > > 0 >@ >@ >@ >@ >@ >@ >@ >@0 ` . . . . . . . . . . . . . . . . @ , , , , , , , ,
` > > > > > > > > P ? ? ? ? ? ? ? ? p ? ? ? ? ? ? ? ? p 8 . . . . . . . . 0 , , , , , , , , p . . . . . . . . ` > > > . . > . > p ( >@ >@ >@ >@ >@ >@ >@ >@ ` ( > > > > > > > > (8 / / / / / / / / @ (L ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 P -p -p -p -p -p -p -p -p @ =x =x =x =x =x =x =x =x > > > > > > > >` ? ? ? ? ? ? ? ? p -p -p -p -p -p -p -p -p` -p -p -p -p -p -p -p -p ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,00 > > > > > > > >` > > > > > > > > 0 ? ? ? ? ? ? ? ?D0 l . . . . . . . .@ , . . . . . . . . @ ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0
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PDP-10 FPGA Clone Chip Layout Description
This is a description of the design and layout of the FPGA PDP-10 clone
microprocessor.
Basics of How to Read this Diagram
Shown is an compile for an XCV300 chip which consists of an
2*48 x 2*32 element array of LUTs. These are
numbered at top and left as numbers 0..47 (column) or 0..31 (row) and
subnumbered L/R (left and right) or F/G. This is how Xilinx numbers them,
due to the way the FPGA chip is wired internally. It consists of 48 x 32
CLBs (configurable logic blocks) of each 2x2 LUTs. Every
F and G pair of LUTs is called a slice (L and R being the
2 slices of the CLB). Slices are officially numbered 0 and 1 with 1=left
and 0=right, which is why all the R slices got used.
Basics of This Chip Design
The PDP-10 is an 36bit processor. For each of these data bits an
near identical processing data path is required,
so that they can all be processed at the same time, so it requires
36 identical repeated sets of logic functions.
The actual Data Path Elements
These are described ordered by function and so by column.
nextPC = oldPC+1
and a
multiplexer for selecting the adder ("normal": use
next instruction and "skip" 2 times next instruction) or the MA
register ("jump": use address in instruction). This remained the
same as in the 2nd milestone
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