http://neil.franklin.ch/Projects/PDP-10/pdp10.sld
  - design of processor state logic diagram
automatically grep-ed from pdp10.java, last generation 2001.12.29

central part of processor state logic diagram
in state insget (Instruction Get)
  MAM-Mux=PC
  IR.OP-Mux=IR.AC-Mux=IR.I-Mux=IR.X-Mux=MA-Mux=MD
  ClkE-IR+MA=1
  PC-Mux=PC+1
  ClkE-PC=1
  state=insexec
in state insexec (Instruction Execute)
  if IR.X
    MAM-Mux=IR.X
    IR.OP-Mux=IR.AC-Mux=IR.I-Mux=IR
    IR.X-Mux=0
    MA-Mux=MA+MD
    ClkE-IR+MA=1
    state=insexec
  elseif IR.I
    MAM-Mux=MA
    IR.OP-Mux=IR.AC-Mux=IR
    IR.I-Mux=IR.X-Mux=MA-Mux=MD
    ClkE-IR+MA=1
    state=insexec
  elseif ... insdecode (Instruction Decode)
    see the instruction unit sections for elseif continuations
  else
    unimplemented opcode, not tested for, FSM simply hangs
    in the end all opcodes will be accounted for, until then avoid
arithmethic testing unit extension of processor state logic diagram
in state insexec (Instruction Execute), continued from Irma insexec
  elseif IR.OP=011000mmm atestcai (Atest Comp AC Immed)
    MAM-Mux=IR.AC               # 1st operand C(AC)
    Imm-Mux=E                   # 2nd operand 0,,E
    PC-Mux=PC+1                 # skip
    if doit                     # apply t:sub and test
      ClkE-PC=1
    state=insget                # we are done
  elseif IR.OP=011001mmm atestcam (Atest Comp AC Mem)
    MAM-Mux=MA                  # 2nd operand C(MA)
    ClkE-AR=1                   # store to AR
    state=atestcam2             # get second operand and test
  elseif IR.OP=01101tmmm atestjump (Jump if AC)
    MAM-Mux=IR.AC               # 1st operand C(AC)
    PC-Mux=MA                   # jump to 0,,E
    if doit                     # apply t:sub-zero and test
      ClkE-PC=1
    state=insget                # we are done
  elseif IR.OP=01101tmmm atestskip (Skip if Memory)
    MAM-Mux=MA                  # 1st operand C(MA)
    PC-Mux=PC+1                 # skip
    if doit                     # apply t:sub-zero and test
      ClkE-PC=1
    if IR.AC                    # if write C(E) to C(AC)
      ClkE-atestAR=1              # store to atestAR
      state=atestwracc          # we are done
    else
      state=insget              # we are done
  elseif IR.OP=0111t0mmm atestasoj (Atest Add or Sub One a Jump)
    MAM-Mux=IR.AC               # 1st operand C(AC)
    PC-Mux=MA                   # jump to 0,,E
    if doit                     # apply t:add-one/sub-one and test
      ClkE-PC=1
    ClkE-atestAR=1                # store to atestAR
    state=atestwracc
  elseif IR.OP=0111t1mmm atestasos (Atest Add or Sub One a Skip)
    MAM-Mux=MA                  # 1nd operand C(MA)
    PC-Mux=PC+1                 # skip
    if doit                     # apply t:add/sub-one and test
      ClkE-PC=1
    ClkE-atestAR=1                # store to atestAR
    state=atestwrmem
in state atestcam2 (Atest Compare Acc Mem second fetch)
  MAM-Mux=IR.AC                 # 1st operand C(AC)
  Imm-Mux=AR                    # 2nd operand from AR
  PC-Mux=PC+1                   # skip
  if doit                       # apply t:sub and test
    ClkE-PC=1
  state=insget                  # we are done
in state atestwracc (Atest Write Result to Accumulator)
  MAM-Mux=IR.AC
  MD-Mux=atest
  ClkE-Mem=1
  state=insget                  # we are done
in state atestwrmem (Atest Write Result to Memory)
  MAM-Mux=IR.MA
  MD-Mux=atest
  ClkE-Mem=1
  if IR.AC                      # also write C(E) to C(AC)
    state=atestwracc
  else
    state=insget                # we are done
boolean logic unit extension of processor state logic diagram
in state insexec (Instruction Execute), continued from Irma insexec
  elseif IR.OP=100ffff01 logimmed (Logic Immediate)
    MAM-Mux=IR.AC               # 1st operand C(AC)
    Imm-Mux=E                   # 2nd operand 0,,E
    ClkE-logAR=1                # apply ffff, store to logAR
    state=logstoac              # store logAR to C(AC)
  elseif IR.OP=100ffffmm lognonimm (Logic non-Immedate)
    MAM-Mux=MA                  # 2nd operand C(MA)
    ClkE-AR=1                   # store to AR
    state=lognon2               # get second operand and operate
in state lognon2 (Logic non-Immedate second fetch)
  MAM-Mux=IR.AC                 # 1st operand C(AC)
  Imm-Mux=AR                    # 2nd operand from AR
  ClkE-logAR=1                  # apply ffff, store to logAR
  if IR.OP=100ffff10            # memory mode
    state=logstomem             # store logAR to C(MA)
  else
    state=logstoac              # store logAR to C(AC)
in state logstoac (Logic Store to Accumulator)
  MAM-Mux=IR.AC
  MD-Mux=log
  ClkE-Mem=1
  if IR.OP=100ffff11            # both mode
    state=logmem                # store logAR also to C(MA)
  else
    state=insget                # we are done
in state logstomem (Logic Store to Memory)
  MAM-Mux=MA
  MD-Mux=log
  ClkE-Mem=1
  state=insget                  # we are done
half word unit extension of processor state logic diagram
in state insexec (Instruction Execute), continued from Irma insexec
  implement after separate memory and registers, to avoid re-doing
bit testing unit extension of processor state logic diagram
in state insexec (Instruction Execute), continued from Irma insexec
  implement after separate memory and registers, to avoid re-doing