http://neil.franklin.ch/Projects/PDP-10/Time-States
  - control circuit design, what to do in what states
author Neil Franklin, last modification 2001.05.06

finished designed are so far:
memory (32 words) and its address and write data mux
program counter and instruction fetch
instruction register and memory address register load
E calculation in MA using up IR.X and IR.I
instruction group 100ffffmm (boolean logic)


------ logic flow diagram

Label	Do			Uses		Clock
insget	MAM=C(PC)		addrbus		1
	IR=C(MD.0-17)		databus.high	1
	MA=C(MD.18-35)		databus.low	1
	PC=C(PC)+1		internal	1

- from here on assuming index and indirect, then no index
insidx	MAM=C(IR.X)		addrbus		2
	MA=C(MD)+C(MA)		databus.low	2
	IR.X=0			internal	2

insind	MAM=C(MA)		addrbus		3
	IR.IX=C(MD.13-17)	databus.high	3
	MA=C(MD.18-35)		databus.low	3
	state=insidx		control		3

- from here on assuming bitwise logical AND, from E and AC, to AC, 100000100
logand	MAM=C(MA)		addrbus		4
	AR=C(MD)		databus		4
	MAM=C(IR.AC)		addrbus		5
	AR=C(AR)<AND>C(MD)	databus		5
	MAM=C(MA)		addrbus		6
	MD=C(AR)		databus		6
	state=insget		control		6


------ state diagram

State	Does
insget	MAM-Mux=PC
	IR.OP-Mux=MD
	IR.AC-Mux=MD
	IR.I-Mux=MD
	IR.X-Mux=MD
	MA-Mux=MD
	ClkE-IR+MA=1
	PC-Mux=PC+1
	ClkE-PC=1
	state=insexec
insexec
	if (IR.X)
		MAM-Mux=IR.X
		IR.OP-Mux=IR
		IR.AC-Mux=IR
		IR.I-Mux=IR
		IR.X-Mux=0
		MA-Mux=MA+MD
		ClkE-IR+MA=1
		state=insexec
	elseif (IR.I)
		MAM-Mux=MA
		IR.OP-Mux=IR
		IR.AC-Mux=IR
        	IR.I-Mux=MD
        	IR.X-Mux=MD
		MA-Mux=MD
        	ClkE-IR+MA=1
		state=insexec
	elseif (IR.OP=100ffff01)
		AR-Mux=MA
		ClkE-AR=1
		state=log2nd
	elseif (IR.OP=100ffffmm)
		MAM-Mux=MA
		AR-Mux=MD
		ClkE-AR=1
		state=log2nd
	else
		unimplemented opcode
log2nd	MAM-Mux=IR.AC
	(log1in=AR)
	(log2in=MD)
	AR-Mux=logout
	ClkE-AR=1
	if (IR.OP=100ffff10)
		state=logmem
	else
		state=logac
logmem	MAM-Mux=MA
	(MD-Mux=AR)
	ClkE-Mem=1
	state=insget
logac	MAM-Mux=IR.AC
	(MD-Mux=AR)
	ClkE-Mem=1
	if (IR.OP=100ffff11)
		state=logmem
	else
		state=insget