Tektronix LT-ACS Model DP84 - Power and RS232 Wiring and Adaptor author Neil Franklin, last modification 2007.10.24 This page is the result of my making an adaptor for the non-standard D-Sub DA15 male connector at the top left (marked with "Terminal"), so that I can use the LT-ACS as an compact general purpose RS232 terminal. History ======= I found this device in the flea market section of an historical computing event (VCFe 8 (Vintage Computing Festival europe 8) in 2007), and originaly just bought it for the externally visible parts (good quality portable QWERTY keyboard, 80x24/25 LCD). After opening it up I found out to my delight that despite being fairly new (1989) it still consisted entirely of known standard 1970s/early-80s 74HC(T) series TTL and MOS parts, allowing me to analyse its function. Not one opaque ASIC in sight. Looking at the chips present (8085 NMOS CPU, 3 CMOS EPROMs, some CMOS SRAMs, 6845 video timing generator, 65SC51 ACIA serial interface, and each 2 1488 and 1489 RS232 chips directly next to the connector), and the lack of any power circuits or connectors, I assumed the LT-ACS to be an terminal with both power and connection via the custom "Terminal" connector. And that just this non-standard connector stood in the way of using it as an compact terminal for testing/debugging random RS232 based microcontroller projects. I assumed the LT-ACS to be most likely an portable device for Tektronix service engineers. A Google search later showed it to be actually the permanent controller for an Credence ACS (Automatic Calibrating System). I assume the name LT-ACS simply stands for "LCD Terminal for the ACS". Photos ====== I have made photos of it, placed at: http://neil.franklin.ch/Computers/LT-ACS/ Analysis 1: Power ================= Pin 13 has on the bottom side of the board an cleary visible wide trace running to the middle pin of the 2position/3pin switch at the left, marked with "OFF/ON" on the case. The end pin in "ON" position is connected via the power plane (the board is 4-layer with an foil 5th "auxillary" layer on the top side) to the +5V/VCC pins of all 5V parts. Pin 7 is connected via the ground plane to the 0V/GND pins of all parts. The +/-12V pins of the 2 1488 chips (and 2 large and 2 small caps) come from pins 7 (+12V) and 14 (-12V) of the blue DC/DC converter (marked with "E.I&S. D2A05") at space U80, which is also fed with +5V. Its -12V also feeds the LCD contrast potentiometer. It also feeds +9V and -9V to the 18pin modem chip (not populated on this board, as are all other modem parts, and the connector hole is blanked off). So we only need to provide an single 5V supply. So a normal spare AC or pulsed DC "wall wart" power supply with rectifier/capacitor/7805 combo will suffice. Someone has actually scratched the text "13+" into the connector, just above pin 13, and the text "7" just above pin 7. I assume this to be the previous owner, who seems to have tried to do what I have done, and then given up and sold the device. Analysis 2: RS232 ================= The RS232 interface starts with an 6551 ACIA (Async Comm Interface Adapter) chip. This offers 3 outputs (TxD, /RTS, and /DTR) and 4 inputs (RxD, /CTS, DCD and /DSR). Of these 3+4 signals it turned out, that only 2+2 are actually used (TxD, /RTS, RxD and /DSR). The rest are simply not connected, at least to the RS232 connector (DCD is actually connected via an AND to the modem chip (U102.2), the AND controlled via the same bit as the modem RxD MUX). RxC is also empty. XTLO/XTLI have an standard 1.8432Mhz Quarz. The rest are power and CPU bus pins, and so not relevant to the RS232 wiring. G65SC51 ACIA, and wiring as U113 .---------. power VSS=GND -- 1 o| `-' |o 28 <- R/W bus bus CS0 -> 2 o| |o 27 <- PHI2 bus bus /CS1 -> 3 o| |o 26 -> /IRQ bus bus /RES -> 4 o| |o 25 <> D7 bus n.c. RxC <> 5 o| |o 24 <> D6 bus quarz XTLI -> 6 o| |o 23 <> D5 bus quarz XTLO <- 7 o| |o 22 <> D4 bus *used* /RTS <- 8 o| |o 21 <> D3 bus n.c. /CTS -> 9 o| |o 20 <> D2 bus *used* TxD <- 10 o| |o 19 <> D1 bus n.c. /DTR <- 11 o| |o 18 <> D0 bus *used* RxD -> 12 o| |o 17 <- /DSR *used* bus RS0 -> 13 o| |o 16 <- /DCD n.c. bus RS1 -> 14 o| |o 15 -- VDD=+5V power `---------' The other end of the RS232 interface is provided by the DA15 connector and 2 1488 (each 4 RS232 output buffers) and 2 1489 (each 4 RS232 input buffers). Obviously one chip of each type would have sufficed for the full 3+4 ACIA pins, so there must be more going on than just the basics. This became even more obvious after it turned out that only 2+2 pins of the ACIA are used. Measuring from the 1488 outputs (pins 3/6/8/11) and the 1489 inputs (pins 1/4/10/13) to the DA15 connector showed 5 signals per direction to be in use, justifying an pair of chips for each direction. In addition 1 output buffer turned out to be cleverly (mis-)used to drive the internal piezo beeper. 1488 RS232 output buffer .-----. -12V -- 1 o| `-' |o 14 -- +12V 1A -> 2 o| |o 13 <- 4B 1Y <- 3 o| |o 12 <- 4A 2A -> 4 o| |o 11 -> 4Y 2B -> 5 o| |o 10 <- 3B 2Y <- 6 o| |o 9 <- 3A GND -- 7 o| |o 8 -> 3Y `-----' out function *Y wiring as U109 *Y wiring as U99 1Y = NOT(1A) to DA15 pin 4 n.c. 2Y = NAND(2A,2B) to DA15 pin 2 n.c. 3Y = NAND(3A,3B) to DA15 pin 9 to DA15 pin 8 4Y = NAND(4A,4B) to DA15 pin 12 to piezo beeper all *A,+B allways common (exept beep) so all NAND(*A,*B) become NOT(*A) 1489 RS232 input buffer .-----. 1A -> 1 o| `-' |o 14 -- +5V 1C -> 2 o| |o 13 <- 4A 1Y <- 3 o| |o 12 <- 4C 2A -> 4 o| |o 11 -> 4Y 2C -> 5 o| |o 10 <- 3A 2Y <- 6 o| |o 9 <- 3C GND -- 7 o| |o 8 -> 3Y `-----' out function *A wiring as U118 *A wiring as U108 1Y = NOT(1A), 1C control from DA15 pin 6 from DA15 pin 10 2Y = NOT(2A), 2C control n.c. from DA15 pin 3 3Y = NOT(3A), 3C control n.c. from DA15 pin 11 4Y = NOT(4A), 4C control n.c. from DA15 pin 5 all *C are left n.c. After subtracting these 10 signals and the 2 power lines, 3 of the 15 pins on the DA15 connector (1,14,15) are unused (too few to go for an smaller DE9 connector). Resulting wiring of the connector is: D-Sub DA15 male, 1-8 top pin row, 9-15 bottom (should be drawn 1/2 line up): .-. left | | --------| |---. 8 o | | | 7 o o 15 | | | 6 o o 14 | | | front 5 o o 13 | | | back inside 4 o o 12 | | | outside cable comes/goes to/from here case 3 o o 11 | | | case 2 o o 10 | | | 1 o o 9 | | | --------| |---' right | | `-' Wiring of the DA15: pin wired buffer wired source/target chain 8 <- U99.8 3Y<-3A+3B U99.9+10 <- "out-MUX" <- "OR" || U113.10 (ACIA TxD) 7 -- 0V/GND/ground plane 6 -> U118.1 1A->1Y U118.3 -> "AND" -> U113.17 (ACIA /DSR) 5 -> U108.13 4A->4Y U108.11 -> "in-MUX" -> U86.5+9 (8085 SID+RST5.5) 4 <- U109.3 1Y<-1A U109.2 <- U113.8 (ACIA /RTS) 3 -> U108.4 2A->2Y U108.6 -> "3STATE" -> U113.12 (ACIA RxD) 2 <- U109.6 2Y<-2A+2B U109.4+5 <- "out-MUX" <- U113.10 (ACIA TxD) || 1 1 xx n.c. 15 xx n.c. 14 xx n.c. 13 -- +5V/power plane 12 <- U109.11 4Y<-4A+4B U109.12+13 <- U56.13 (FF, = RTS?) 11 -> U108.10 3A->3Y U108.8 -> "3STATE" -> U113.12 (ACIA RxD) 10 -> U108.1 1A->1Y U108.3 -> "in-MUX" -> U86.5+9 (8085 SID+RST5.5) 9 <- U109.8 3Y<-3A+3B U109.9+10 <- 0/0V/GND/ground plane (= DTR) Of course 5+5 signals is more than 3+4 from the ACIA, and even far more than the actual 2+2 used. So the story between the ACIA and the buffers is quite a bit more complicated than just direct lines: - One of the outputs (pin 4) is directly connected to the ACIA /RTS. This is the only direct ACIA->1488 output (and there are no direct 1489->ACIA inputs at all!). - One of the outputs (pin 9) is connected to an constant 12V. Its 1488 buffer has its inputs permanently connected to 0/0V/GND, so it will output 12V as long as the LT-ACS is powered up. This gives actually an DTR signal, despite the ACIA /DTR pin not being connected. This saved no actual parts, just an single board trace :-). - One of the inputs (pin 6) is connected via an 7408 AND gate (U88.10 in, ANDed with U88.9, out U88.8) to the ACIA /DSR. Such an AND can force a signal to 0, and so set /DSR active, pretending that an device is connected. The AND gets its control U88.9 from an 74574 FF (U66.13 out, clk U66.11, /enable 0, in U66.8, data bus D6). What clocks U66.11 I have not yet looked at. I assume some IO address decoder. - Two(!) of the inputs (pins 3 and 11) are each connected via an 74126 3STATE gate (U98.5 in, control by U98.4, out U98.6 and U98.9 in, control by U98.10, out U98.8) acting as an multiplexer to the ACIA RxD. A third 3STATE gate (U98.2 in, control by U98.1, out 98.3) also allows RxD to get data from the not populated modem chip (U102.4). The first 3STATE gets its control U98.4 via an 74257 MUX (U89.12 out, select U89.1, in1 U89.14, in U89.13 (set to 0)) which acts as an "U89.1 select sets to zero" from an 74574 FF (U66.19 out, clk U66.11, /enable 0, in U66.2, data bus D0). The second 3STATE gets its control U98.10 from an 74574 FF (U66.18 out, clk U66.11, /enable 0, in U66.3, data bus D1). This is the same bit that drives above 74257, producing with the 2 3STATES an 2:1 MUX. The third (modem) 3STATE gets its control U98.1 from an 7404 NOT (U69.10 out, in U69.11) which gets it from an 7432 OR (U79.11 out, in U79.12 and U79.13), which get its 2 inputs from the 2 other 3STATE controls, so forming an 3:1MUX. - The remaining two inputs (pins 5 and 10) are each connected via an 7408 AND gate (U88.13 in, ANDed with U88.12, out U88.11 and U88.1 in, ANDed with U88.2, out U88.3) and then selected via an 74257 MUX (U89.11 in0 and U89.10 in1, select U89.1, out U89.9) and further via an 7404 NOT (U69.9 in, out U69.8) to both the 8085 Processors SID (Serial Input Data) and RST5.5 (Restart 5.5 interrupt). The ANDs can force a signal to 0, and so set NOT(SID+RST5.5) active, pretending that there is an signal, and possibly generating an interrupt. The first AND gets its control U88.12 from the same 574 pin (U66.13) as the DSR AND. The second AND gets its control U88.2 from an 74574 FF (U66.14 out, clk U66.11, /enable 0, in U66.7, data bus D5). The MUX gets its select U89.1 from an 74574 FF (U66.18 out, clk U66.11, /enable 0, in U66.3, data bus D1). This is the same bit that above selects the 2nd 3:1MUX RxD input. What clocks U66.11 is also the same as above. As we already have 2 RxD and 1 DSR inputs, I assume that these are providing 2 CTS inputs, and that they are run to NOT(SID+RST5.5) instead of ACIA /CTS so that separate interrupt vectors are used. - Two of the outputs (pins 2 and 8) are each connected to an 74257 MUX (U89.4 out, select U89.1, in0 U89.2, in2 U98.3 and U89.7 out, same select, in0 U89.5, in1 U89.6). Both pin2 in0 and pin8 in1 are connected to the ACIA TxD. Only pin2 in1 is connected to 1/+5V, producing an frame break, while pin8 in0 is connected via an 7432 OR (U83.9 in, ORed with U83.10, out 83.8) to RxD, which allows the OR to select between passing through RxD to TxD or producing an frame break. This is the same 74257 as in the RxD and CTS inputs above, so its U89.1 uses the same 74574 FF. The ACIA TxD also drives directly the not populated modem chip (U102.10). The RxD passthrough OR gets its control U83.10 from an 74574 FF (U56.15 out, clk U56.11, /enable 0, in U56.6, data bus D3). What clocks U56.1 I have not yet looked at either. - The remaining output (pin 12) is connected to an 74574 FF (U56.13 out, clk U56.11, /enable 0, in U56.8, data bus D1). What clocks U56.11 is the same as above. As we already have 2 TxD, 1 RTS and 1 DTR output, I assume that this is providing an second RTS output. This looks like the LT-ACS, with each 2 TxD, CTS, RxD and RTS signals and with RxD->TxD "passthrough" is intended to be an "double terminal", with 2 RS232 connections to 2 different devices inside the ACS, and with the ability to send the output of one of then as input to the other. I assumed for a while that one of these devices is an "controller" whose output can go to the second which is an "executor". But grouping suggests something different. Generally U66 has 4 bits to set up interface selection. While U56 has 2 bits to make the 2nd RTS and switch between passthrough and frame break. Grouping the pins into 2 interfaces gives: - RxD, TxD and assumed CTS is easy, due to shared selection bits. Setting U66.18 (D1) to 0 allows RxD from pin 3 (so long U66.19 (D0) is also set, clearing that sets RxD to modem) and sends TxD to pin 2 (setting pin 8 to possible RxD passthrough) and takes CTS from pin 5. While setting U66.18 to 1 allows RxD from pin 11 (no modem possible) and sends TxD to pin 8 (setting pin 2 to frame break) and takes CTS from pin 10. - Grouping the fitting RTS is not possible by select bits, as both are separately driven (why?). But as the "real" ACIA RTS pin 4 is together with pins 2 3 and 5, while the U56.13 (D1) RTS pin 12 is together with pins 8 10 and 11, this one looks obvious. - Interestingly DSR pin 6 is specifically associated, via the "AND simulate active" control bit U66.13 (D6), with the pin 5 CTS. While pin 10 CTS has its own U66.14 (D5) control bit. - It looks like the set or pins 2-6 are the primary interface, as it has DSR and can drive passthrough. 8+10-12 seems to be an auxillary interface. The "controller" and "executor" pair seems to be more an "device" and "logger or terminal printer" pair. So the custom connector is power supply and 2 RS232 lines all in one 15pin. Adaptor Board Wiring ==================== Power is simple: An separate (= reusable) 7805 based AC->5VDC converter is connected via an 2pin power connector. Its 5V is wired to DA15 pin 13, its 0V/GND to pin 7. RS232 I have opted to only wire one system, to save parts and space, as I have no need for "double terminal" operation. DTR and DSR are obvious: DA15 pin 9 to DB25 pin 20, DA15 pin 6 from DB25 pin 6. RxD, TxD, CTS I am taking the ones that are associated with DSR: DA15 pin 3 from DB25 pin 3, DA15 pin 2 to DB25 pin 2, DA15 pin 5 from DB25 pin 5. RTS I am taking the "obvious" one: DA15 pin 4 to DB25 pin 4. In pins 2-7 we see an system: 1:1 correspondance of TxD, RxD, RTS, CTS, DSR and GND. That also explains the empty pin 1. The next pin 8 would be DCD which is not implemented. That gives an good feeling about the grouping. DTR moved from its nonexisting pin 20 to 9. The 2nd interface gets 8 and 10-12. Power gets 13, 14+15 are left over. The only "loose end" is: why did DTR not get 8 and the second interface 9-12, or the second interface 9-13 with power on 14? I have double-checked the wiring of pins 8 and 9, it is correct as above. Adapter Board Layout and Assembly ================================= For the LT-ACS side: 1 DA15 female. For the other side: 1 2pin Power and 1 DB25 male (RS232 DTE). Stripboard 2.54mm (100mil) raster, 27x10 holes, strips in the "10" direction, all strips are cut *between* 2 holes into 4+2+4 sections (connected holes 1-4, 5-6, 7-10). Or use a stripboard that is pre-cut/pre-etched into 5 "2" long sections (of which 3-4, 5-6, 7-8 are then used). The DB25 and DA15 are inserted so that the "top" (come further in) pins end in holes 5 and 6 (the "2" long section in the middle of the 4+2+4 sections), and the "bottom" pins end in hole rows 4 and 7 (the 2 "4" sections), where also the mounting screws get ther big holes drilled. RS232 DTE DB25 male 13/25 14/1 Power .--------------. 2pin .-------------------. .--. .`-------------------'-| |. | () ||||||||||||| () | || | () |||||||| () `--'| `-----.--------------.-----' Board `--------------' `--------' 8/15 9/1 LT-ACS DA15 female Connecting of the DB25 <-> DA15 pins 2-7 goes directly via board traces (the "2" sections). For this to work the pins 2-7 of the 2 "tops" need to be alligned, which is why the DB25 points out to the left, and the power connector is on the right, for symmetry or the board. Do *NOT* wire pins 8, as this will short the RS232 DCD (from modem) and LT-ACS 2nd TxD (from LT-ACS) which are both outputs! The DB25 pin 20 <-> DA15 pin 9 are connected by wire, from holes 1-4 to 7-10. The Power <-> DA15 pins 7 and 13 are also connected by 2 wires. Testing ======= After making the adaptor and plugging the LT-ACS in, I got no picture on the LCD. Also a RS232 tester shown no signals coming from the device. An ampere meter shows the device taking a few 100mA current, so it seems to be doing something. Further measurements showed no +12V and -12V on the DC/DC converter. This part seems to be broken. Unfortunately it ist exactly the *only* non-standard part on the entire board. So now I need to find an small (DIP14) DC/DC converter to continue reviving the LT-ACS. At least I do not need to generate the +9V/-9V, as I habe no on-board modem.