http://neil.franklin.ch/Projects/FPGA-PC/Logfile - things done and to do author Neil Franklin, last modification see last entry near bottom 1981.11.xx my first use of a computer, Z80 microprocessor based, Pascal and Assembler http://neil.franklin.ch/Computers/index.html http://neil.franklin.ch/Projects/index.html mid to late 198x.xx.xx designed data path for an 32bit Forth CPU using 74LSxx(x) TTL logic failled at control circuits due to not knowing enough about logic design did not even know about finite state machines in those days later 198x.xx.xx read about PALs in magazines, MMI 16R8/20R8, AMD 22V10 plans to do an CPU in an PAL, but even MMI 64R32 was too small, too few FFs did not know bitslice technique in those days, nor idea of external registers was too taken in from the idea of a single chip CPU, microprocessor later 198x.xx.xx recieved Jargon File on floppy, read about TMRC/MIT-AI hacker culture read about PDP-1, PDP-6 and PDP-10, impact in hackers, ITS development 1990.01.xx saw first time Xilinx chips in magazines, looked like a great thing but could not afford the $5000 development tools as just ex-student 1991.09.xx saw Algotronix CAL1024 PC/AT card, but had just got new non-PC (NeXT) computer so I went a different career in programming, Unix, sysadmining digital electronics, particularly processors, staid an hobby interest mid 199x.xx.xx one session on Usenet at local university, discovered alt.folklore.computers 1997.11.xx got onto Usenet from my home Internet connection 1997.12.10 Wed subscribed to alt.folklore.computers, as 2nd newsgroup, oldest still going 1997.12.17 Wed thread on PDP-10s Daniel A. Seagraves muses on emulating an 10 http://neil.franklin.ch/Usenet/alt.folklore.computers/19971208_Curious_about_10s G. Herrmannsfeldt mentions a FPGA project that turns out to be an -8 also has a discussion about DECtape file system format and claim that someone still has an KA-10/KI-10 TOPS-10 that fits one DECtape 1999.07.02 Fri Communa/Lisard mentions putting Forth into hardware, simple enough for FPGAs http://neil.franklin.ch/Usenet/alt.folklore.computers/19990630_CPU_s_directly_executing_HLL_s Paul Wallich mentiones Alto only 1600 gates, would go in an FPGA 1999.07.07 Wed Jan Gray carries on speculations of implementing Xerox Alto in an FPGA http://neil.franklin.ch/Usenet/alt.folklore.computers/19990707_Alto_in_an_FPGA 2000.08.19 Sat D G Conroy announces PDP-8/X implemented in an XCS10 FPGA http://neil.franklin.ch/Usenet/alt.sys.pdp8/20000819_something_for_everyone_s_amusement Actual website is http://surfin.spies.com/~dgc/pdp8x/ Ben Franchuk mentiones above project http://neil.franklin.ch/Usenet/alt.folklore.computers/20000819_Naked_computers discussion that Blinkenlights are really neccessary my interest in doing an CPU myself with programmable logic rewoke 2000.08.21 Mon J Gray pointer to www.fpgcpu.org, many pages on techniques http://neil.franklin.ch/Usenet/alt.sys.pdp8/20000820_pdp8x_fpga_code_and_front_panels stuff on his XR16 CPU and SoC designs http://www.fpgacpu.org/xsoc/index.html 2000.09.09 Sat looked at boards used by J Gray for XR16 XS40-010E+ (XC4010E) http://www.xess.com/prod018.html also XSV (XCV50-800) http://www.xess.com/prod014.html start looking at CPLD and FPGA vendor data sheets 2000.09.09 Xilinx, 2000.09.13 Altera, 2000.09.27 Atmel, 2000.10.22 Cypress Lucent too complicated, Gatefield&Quicklogic no data sheets Actel&Lattice websites fail (A wants JavaScript&Flash, L tons of my data) 2000.09.23 Sat subscribe to comp.arch.fpga 2000.10.01 Sun my first alt.sys.pdp10 thread discussing implementing an 10 in an FPGA http://neil.franklin.ch/Usenet/alt.sys.pdp10/20001001_PDP_10_in_an_FPGA_chip B Franchuk does FPGAs, uses Altera but claims OTP (?, Actel?) links on his website show he uses BurchED boards with Altera chips http://www.jetnet.ab.ca/users/bfranchuk/luna/right6.html BurchED http://www.jetnet.ab.ca/users/bfranchuk/luna/right2.html Altera 2000.10.07 Sat Guccione List of FPGA-based Computing Machines, XKL/Toad-1 is 2 * XC4010E-3 http://www.io.com/~guccione/HW_list.html 2000.10.17 Tue Discusion about using FPGAs for cloning old CPUs http://neil.franklin.ch/Usenet/alt.folklore.computers/20001017_FPGAs_for_old_CPUs I ask about programming languages VHDL vs Verilog http://neil.franklin.ch/Usenet/comp.arch.fpga/20001017_VHDL_vs_Verilog from reading courseware on a web site I don't like either of them possibly try cnets or PamDC, both C++ based instantiation of FPGA elements 2000.10.18 Wed L Brinkhoff pdp10.nocrew.org PDP-10 processor features comparison http://neil.franklin.ch/Usenet/alt.sys.pdp10/20001016_PDP_10_processor_features also discusses his plans to port gcc, binutils, Linux to PDP-10 also source for ITS (kernel only) and links to other ITS page also list of PDP-10 emulators, all unfinished and not available 2000.10.22 Sun APS http://www.associatedpro.com/ look at Virtex boards V240 (XCV50-800) http://www.associatedpro.com/v240.html VCC http://www.vcc.com/ fairly expensive XCV but with BGA, many pins Virtual Workbench http://www.vcc.com/vw.html 2000.10.24 Tue BurchED http://www.burched.com.au/ very cheap XC4010 board BED-XILINX-4000+ http://www.burched.com.au/bedxilinx4000.html 2000.11.01 Wed L Brinkhoff announces he is porting gcc to TOPS-20, is getting payed by XKL http://neil.franklin.ch/Usenet/alt.sys.pdp10/20001101_Planned_gcc_gdb_gas_port_to_PDP_10 question about JBits, I visit JBits site, is pure Java tool also works on instantiation of FPGA elements, will it work on Linux? http://neil.franklin.ch/Usenet/comp.arch.fpga/20001101_JBits http://www.xilinx.com/products/software/jbits/index.htm 2000.11.12 Sun sketched XC40-010E pinout, to see what pins are free, this last update http://neil.franklin.ch/Projects/PDP-10/XC40-010E-Pinout looks like there are too few pins on PLCC84 ask Xilinx if JBits will work on Linux, yes it does, is used, but no support so that decides tool (JBits) and chip family (Virtex/Spartan-II) Virtex data sheet http://www.xilinx.com/partinfo/ds003.pdf weaknesses seem to be: array wide, not high (XC4020 56x28 vs XCV50 32x48) TBUFs/BUFTs only 2 out 1 in per 4 LUTs, not 4 and 4, can be circumvented Spartan-II are architecturally Virtex, same bit stream, same tools http://neil.franklin.ch/Usenet/comp.arch.fpga/20000829_Spartan_II_vs_Virtex 2000.11.26 Sun sketched XSV and APS-V240 pinouts, to see what pins are free this date is actually last update, not recorded first date http://neil.franklin.ch/Projects/PDP-10/APS-V240-Pinout more free, ZBT RAM 18bit, better http://neil.franklin.ch/Projects/PDP-10/XSV-Pinout right RAM unusable, left only 16bit 2000.12.19 Tue BurchED announce of BED-SPARTAN2+ and BED-FPGA-CPU-IO http://neil.franklin.ch/Usenet/comp.arch.fpga/20001219_FPGA_and_Board_for_Microprocessor_Design BED-SPARTAN2+ http://www.burched.com.au/bedspartan2.html BED-FPGA-CPU-IO http://www.burched.com.au/bedfpgacpuio.html Uses XC2S200, is 2/3 XCV300, but 1/6 price of APS V240-XCV200 board 2000.12.24 Sun BED-SPARTAN2+ only place for DIP8 config PROM (17xx?), I want EEPROM, Atmel? but their AT17C020 is also PLCC22, do own socket, use Xilinx XC18V02 PLCC44 2MBit - XC2S200 1.33MBit = >20.5kword*36 for EUUO and boot code 2000.12.30 Sat alt.sys.pdp10 "implement 10 in FPGA" question post, second in 3 months I will reply to it, but first get my docs up to standards needed while thinking over it in bed, decision to go direct for 10, no 8 or 11 first 11 complex instruction set and no real use (got Supnik simulator for Unix) 8 no real use (got no software for it and no real stepping stone for 10) go directly for an 10, historic good and extended is usable as daily system will make it as an full open source project, all code and docu life on line should start by documenting what has been done, as log+todo file 2000.12.31 Sun unsubscribed alt.sys.pdp8|11 as interest is going direction of cloning an 10 opened up URL for PDP-10 project http://neil.franklin.ch/Projects/PDP-10/ start this log file, retroactively log all the done stuff searching for first PDP-8/X post, found in a.f.c 2000.05.03 emulator tread http://neil.franklin.ch/Usenet/alt.folklore.computers/20000503_PDP_10_Emulator posted announce of this project, as followup to 2000.12.30 question http://neil.franklin.ch/Usenet/alt.sys.pdp10/20001231_PDP_10_in_an_FPGA_chip_starting 2001.02.18 Sun made braindump of hardware ideas http://neil.franklin.ch/Projects/PDP-10/Hardware (now moved to http://neil.franklin.ch/Projects/FPGA-PC/Hardware) 2001.05.24 Thu updated PDP-10/OOREADME, PDP-10/OFAQ and PDP-10/Hardware files 2001.08.15 Wed officially opened subproject to make an "chip photo" viewing tool named this tool VirtexView, command vv created VirtexView project directory and started logfile http://neil.franklin.ch/Projects/VirtexView/Logfile will implement it after reaching PDP-10 2nd milestone 2001.09.03 Mon khtsoi@pc90026.cse.cuhk.edu.hk published Linux parallel port download program http://neil.franklin.ch/Usenet/comp.arch.fpga/20010903_Linux_download_bitstream_w_source 2001.09.16 Sun Added DRAM plus SRAM config and floppy for DECtape to Hardware ideas 2001.10.15 Mon comp.arch.fpga Discussion pointed to an JTAG downloader for Linux http://www.cse.cuhk.edu.hk/~khtsoi/project/Xilinux/ 2001.10.19 Fri read about FlexATX board format, smaller that MicroATX format searched Intel Website for board format specifications, found format site http://www.formfactors.org/developer/motherboard.htm updated hardware ideas to reflect possible use of this format 2001.11.01 Thu added ISA plus PC/104 variant to hardware ideas, also that without proto area 2001.11.05 Mon D G Conroy announces finished PDP-4/X clone and soon PDP-1/X, in XC4010 may be continuing than with an PDP-10 http://neil.franklin.ch/Usenet/alt.sys.pdp10/20011105_Another_DEC_computer_in_an_FPGA later this thread runs into discussion of hardware/boards for FPGA clones 2001.11.27 Tue discussion about connecting modern IO to an FPGA 10 http://neil.franklin.ch/Usenet/alt.sys.pdp10/20011127_Like_to_see_more_action 2001.12.08 Sat discussion about implementing front pannels, desired user experience http://neil.franklin.ch/Usenet/alt.sys.pdp10/20011208_Wants_needs_was_Re_Another_DEC_computer_in_an_FPGA 2001.12.09 Sun went through Hardware file noting implementation details for different IO ports read up on details some PC IO devices and of AT and SCSI buses added ideas about using an 8051 for configuring, ev also use it as FEP 2001.12.23 Sun XKL is reopening PDP-10 TOAD-1 production, doing new XKL-2 processor http://neil.franklin.ch/Usenet/alt.sys.pdp10/20011223_XKL_2 also intention to after make an single board CPU/Mem/Net/Disk system 2001.12.28 Fri in Hardware file updated ideas about configuring per 8051 for use as FEP added sharing RS232, keyboard and floppy connectors 2002.01.12 Sat further additions to Hardware file, result of musing on pin count limitations better generic IO ports and adapters, or possibly use BGA or second IO FPGA also wide 72pin memory is out, even 36bit may need multiplexed addr/data so any high color video is out, unless (F)BGA cases are used 2002.01.13 Sun Hardware file added possibility of using PAL to program FPGA 2002.01.19 Sat merged VirtexView sister project with up to now unpublished libvirtex project named merged project as VirtexTools, VirtexView is now just one tool in it http://neil.franklin.ch/Projects/VirtexTools/Logfile at some time in the future this PDP-10 project will be recoded using them 2002.05.06 Mon after mail discussion about using microcontroller for booting/configuring Rolie Baldock says that 8051 is primitive, so change to no specific type revisited Hardware file to make text more flexible, no specific type named reworked entire config loading options section, text now better blocks microcontroller also without Flash, using shared floppy/HD/PCMCIA/CF split IO devices into 3 sections user IO, storage, expansion connectors reworked expansion section, now better blocks of similar options first generic pins (non-bus) based ones, then bus based ones 2002.05.31 Fri mentioned looking for an microcontroller to colleagues I want direct compressed bitream and decompressor in microcontrollers Flash told them about possible selections at the moment, they suggest Atmel AVR 2002.06.03 Mon went looking at microcontrollers for FPGA loading Zilog Z80/Z180 I know the instruction set, but no microcontrollers with it only Zilog microcontroller is Z8 which is different instr set, and mask ROM Z280/eZ80 webserver has all peripherals, but only mask ROM no flash Intel 8051 totally primitive, no space for bitstreams, best is 8751 EPROM external flash can not be addressed directly, only via special instr and uses up the few IO pins real fast, no left for FPGA, RS232, Floppy, IDE Motorola 68HC11 website ist unusable, can not even find data sheets Atmel AVR is a real processor, megaAVR large Flash versions up to 128kByte is actually an Harvard architecture RISC with 64k*16bit program space 2002.06.11 Tue after Mail from Harry Reed re-checked eZ80, has no mask ROM, no ROM at all eZ80 Webserver Developer's Kit has 1M Flash, but that is a multi-chip system I really do want an single chip solution, or I will prefer to use an SEEPROM 2002.06.14 Fri am presently contemplating change from Linux to NetBSD problem may be connecting FPGA programming circuits looked into how they are accessed under Linux: iopl() set to 3 opens ports or alternative ioperm(from, num, on) for sections instead of all then process can simply outb() and inb() direct to/from IO addresses so accessing hardware is as easy as under DOS, exactly the same methods BTW: the iopl() system call was added for XFree to access video card regs 2002.06.15 Sat found it for NetBSD, the equivalent of iopl() is called i386_iopl() also have i386_get_ioperm(32x32bitmap), for sections, up to 1023, else iopl() also there is an /dev/io, that when opened sets the IOPL register 2002.06.16 Sun mail from Hubert Feyrer from NetBSD, points to i386_iopl() equvalent of inb() and outb(), is bus_space_*(), abstracted from bus type so connecting an FPGA programmer is as easy as under Linux or even DOS 2002.06.17 Mon also mail from Ken Stailey FreeBSD uses /dev/io, no iopl() but i386_set_ioperm(), name as in NetBSD but usage as in Linux an actual data transfers with outb() and inb(), same as in Linux 2002.07.14 Sun went looking for Linux tools for programming microcontrollers found assemblers (ava, avra) and download tools (avrprog, uisp) for AVR one C compiler and simulator (sdcc and sdcc-usim) for 8051/AVR/Z80 simulator (gpsim, sumulpic), assemb (gputils, picasm) download (picp) for PIC of above I have looked at 8051 and AVR; so also went and looked at PIC PIC16Cxx are too small, PIC18Cxx large enough, but seems messy like 8051 2002.09.10 Tue while doing VirtexTools and looking for Virtex-II config info saw documentation for SystemACE TQFP144 device for config from CF card added this to Hardware file as boot option 2002.11.10 Sun extended mail discussions with Andrew Grillet about his new prototype board uses 4 large connectors (nice in Trenz), but all on front (nice in BurchED) he is interested in PDP-8/10/11 cloning and wants to offer front panels! looked at various issues, such as connectors and system layout front panel (rows of LEDs for what data, and width), memory vs IO buses updated home page "Auxillary" section, boards list with all the prototype boards I have considered, and comments on them 2002.11.13 Wed home page further additions in boards section and corrections in history 2002.11.14 Thu with Andrew Grillet started exchange on flexible FPGA boot option which allow storing multiple designs and chosing at boot time which to load load from floppy/EEPROM/CF/IDE/SCSI, run by CPLD/small-FPGA/uC(8051/AVR/Z80) 2002.11.18 Mon with Andrew Grillet started exchange on possible ATX format board possibly with large chip than 200 size, ideal for KL compatible machine discussion about including an PC "legacy IO" chip for PS2-key/PS2-mouse/serial/parallel/floppy/ISA interfaces 2002.11.25 Mon re-read PDP/8 data book section on Omnibus, it complex, and very PDP-8 specific no use for my PDP-10, not even as base to widen up to 36bit looks like I will need to design own IO bus/slots, or SCSI for everything 2002.11.28 Thu got news about Xilinxes XC2S400E and 600E chips, large, many BRAMs and cheap with this Spartan-IIE (and so Virtex-E) becomes interesting for me E series chips are not supported by JBits, so they will require recoding this will require me to get on with VirtexTools to do this 2002.12.03 Tue mail from Andrew Grillet that he wants to use the XC2S600E for his ATX board his target project is to run ESAs Leon Sparc clone on the board but is interested in making board PDP-10 usable, so long no design conflict he will be using largest chip, because overhead is more than chip cost anyway this seems to be XC2S600E-FG676, with 514 user IO lines, IO galore! 2002.12.08 Sun decided that an underused large board for KA-10 and then expanded design is cheaper than first small board for KA-10 and then large one for expanded and it saves the time making RAM and IO modules for small/prototype board so better to get Andrew up to optimal speed for the large board this means I will have to convert to E capable tools for first chip running so switch to standard Webpack tools and vas coding as fast as possible started file Boardspec with spec for Andrews XC2S600E board basically take my Hardware file and run it through Andrews constraints these are: good for ESAs Leon Sparc clone, ATX format, PCI connectors (this file evolved into todays BoyrdSpec600E.html file, in FPGA-PC project) 2002.12.09 Mon further with Boardspec, looked at ATM/MicroATX docs, is 7/4 slots, not 8or6/3 also added FlexATX, with 3 slots and less depth, we have only few components convert to boardspec.html, so I can insert links to background info pages convert layout format to full text, add links to background, add comments generally extended stuff, added a few more options, re-added PCMCIA/CF 2002.12.10 Tue further with boardspec.html, ATA/PCMCIA/CF refer to ISA, possibly add ISA slots reorganised dual ATA and/or SCSI busses, separte pins just for independancy losts of details worked over, better texting, missed details separated out "unlikely" user IO devises into an separate "thrown out" list also added such an list for storage devices section 2002.12.11 Wed further with boardspec.html, a bit of tidying up stuff 2002.12.14 Sat further with boardspec.html, added RTC/CMOS and FEP being able to use Ethernet gone looking for DIMM meory parts and slots specs found out that 64/72bit also have an compatible 80bit variant 144 (no 128) does not allow this, so is inferiour in addition to seldom DDR 64/72 do not either offer this, so we will need to use the slower chips 256/??? DIMMs I did not even find any docu, despite being the JEDEC website update massively the entire Memory section, to reflext this subtitles here and in all the other sections convert devices
structures to subtitles 2 RS232 make separate section like for 2nd VGA mentioned that it is not important, today with PS/2 mice and ISDN/ADSL/CATV Ethernet added the growing importance with ISDN/ADSL/CATV PCI mention no 64bit or 66MHz, ISA mention no EISA or VLB ISA bus expanded coverage, and added possible PC/104 to it 2002.12.15 Sun further with boardspec.html, improving configuring options section a bit more of touching up on all parts, memory cache reason for no assync asked a few IRC friends for critics and improvement suggestions Attila suggests less built in IO stuff, take out sound and Ethernet and USB or better make these facultative, for Andrew to decide it he wants them remarks about PCI load capacitance limits, need buffers to separate ISA off also possible problem with resistor DAC for 8bit and >100MHz signals decided to put in an custom direct expansion connector, basically an set of pins like on prototyping boards, for user made expansion without using bus with an PCI connector (different colour) worst case use this as 2nd "bus" 2002.12.16 Mon further with boardspec.html, decided that 256/288/329bit memory is out we simply do not have enough IO pins for that, despite FG676 case with 514 so go for 160bit (paired DIMMs) memory, but perhaps 2 independant 80bit update and simplify cache stuff to only calculate for 160bit, add tag stuff tidy up VGA section, detail out the possible colour resolution trade offs also put in comments on memory bandwidth for fetching pixel data tidy up sound section, make it more likely that it could go in put more details into PCI/ISA/ATA/SCSI busses sharing FPGA pins PC/104 remark that no PC/104+ (PCI), same for PCMCIA no Cardbus (PCI) split digital and analog joysticks into 2 parts, for easier reading discussions in IRC show that sound is wanted, so put it back in, 2 or 3 jacks 2002.12.17 Tue Mails from Hans B Pufal commenting on board spec, interest in doing GE635 supports switches instead of jumpers suggests having connectors for selecting by an other computer puts in an vote for Ethernet being in, as universal external device connect possibly even using real old devices, with an small Ether/micro/controller discussion shows that I should drop PHY based Ether and go for an full chip also suggest using backplane based hardware, but that has serious drawbacks 2002.12.18 Wed updated boardspec.html in light of the Pufal suggestions 2002.12.19 Thu further with boardspec.html, tidied up a few details in expansion bus and the entire dual VGA and RS232 stuff, noted preferences there decided that 2nd VGA should definitely not be on board also that 2 RS232 are desirable, if place allows, drop joystick for them config decided that best share PCI/ISA/ATA/SCSI/PCMCIA/CF pins with FPGA removed config loading from Ethernet, if wanted use an PCI or ISA card rearranged FEP section, split into uP based FEP and FPGA based FEF 2002.12.20 Fri further with boardspec.html, tidied up a few details everywhere 2002.12.21 Sat further with boardspec.html, reorganising all the bus variants and interaction config section further ideas, add EEPROM socket as cheap if not used and allows operation without disk or flash which cost more sketch out "small board" which may be QST0201 based or standallone memory only 36/40bit wide SRAM (in pin emergency 18/20/24), no cache FlexATX or better PC/104 or both, remarks about PC/104 small board as FEF bus only ISA and PS/104 no PCI, no custom direct expansion connector cut down user IO, max one 3*4 bit VGA, no sound, Ethernet, joystick, USB disk IO only one set of ATA/SCSI, shares ISA, only one ATA connector config only remote/developer and EEPROM, no uC/uP, no FEP, no FEF name small board BoardSpec150.html, rename large to BoardSpec600E.html mentioned the small board in intro section of large board spec added using the small board as plug-on FEF to FEF section 2002.12.22 Sun further with BoardSpec150.html, tidying up memory and bus stuff 2002.12.26 Thu further with BoardSpec150.html, tidying up memory stuff, most likely only 18bit improves local config/selection writing, same also in 600E also add remark about FPGA conf mode pins M0-2 on DIP switches, like clock 0 further with BoardSpec600E.html, improving config stuff, non-FEP uC is enough FEP stuff then introduce uP, rename FEF to FPGA FEP, no new term needed move all pluggable hard or FPGA based FEP stuff into separate section 2002.12.27 Fri further with BoardSpec600E.html, update USB section as it may be usefull get rid of "marginal" section, put in normal with caveats mentioned (USB) added reference to USB in uC configuring, before Ethernet configuring or in rejected with caveats for that (joystick) tidied up SCSI external and terminator issues reorganised fixed 8bit vs fixed FPGA vs pluggable FEP stuff improved details on using the small board for this further with BoardSpec150.html, replacing PC/104 with general small industrial this may be PC/104, 3.5" disk or 160x100mm euro card format 2003.01.01 Wed further with BoardSpec600E.html, more details and variants in VGA DAC stuff dropped the XAPP154 DAC referrences, as not likely to be of any use with Attila long RL discussion about board features, he wants board definitely comments memory layout (160bit) and cache size (2-4M) as "typical mainframer" also thinks that there exist no AGP prototyping cards, likes "2nd PCI" idea thinks that an 200MHz capable adding amplifier for VGA out is out of range suggests instead only "virtual consoles" with KVM style video switch, Maxim for mixed display run small FPGAs output via large fpga, there "digitiser" likes printer port power switch idea, but suggests anti-shorting resistors 2003.01.02 Thu further with BoardSpec600E.html and BoardSpec150.html printer port added remarks about anti-shorting safety resistors and stuff about switched power pins, amount, volts, discussion GND vs IO also tidied up PC LEDs&switches part, is also universal 6bit IO and while there put in definitely 2 PS/2, as saving 2 IOs not worth only 1 further with BoardSpec600E.html, tidied up uC based config options more details on uC configuring FPGA, use tri-state onto devel par port stuff put in "facultative" for USB and even more so Ethernet variants tidied up FEP display options, to what is realiatically possible in particular no mixed video, just switchable, or digitiser, like BT848 moved clock 0 config and M0-2 in together with FPGA config and clock 3 stuff all 4 shoudl be possible from development system, and between FPGA boards moved pluggable FEP stuff between hardwird and FPGA FEP sections rejected storage mentioned any specialised tape or cassette interfaces Attila looked at spec files, suggests over/under voltage and ESD protection sensibly these and anti-shorting on all user accessible FPGA pins on PS/2, VGA, RS232, LPT, LEDs&switches, PC speaker, leave RS232, sound Lukas adds that at least PS/2 should be hot pluggable missed remarks on 150 having 2 suggested board shapes, FlexATX and PC/104... improve text to make this more visible, that there are variants went looking at Maxim voltage protection and video switch parts went looking at PC/104 web site, got PDFs of standards documents 2003.01.03 Fri 2nd Mail from Hans B Pufal commenting on board spec questions parity/ECC, supports separate PCI connector, wants 2 RS232 likes switchable LPT power a lot but suggests jumpers, supports USB2 suggests SATA should go in, questions floppy updated BoardSpec600E.html in light of the Pufal suggestions ECC was put in at alt.sys.pdp10 readers request but decided that ECC is speed cost, so using 128bit as 3*36 should go and the DDR speed doubling should still save the day, so perhaps better rework quite a bit of memory and cache stuff to fit new ideas on this put in that 2nd ATA/SCSI may have to share pins with separate non-bus PCI or even just non-bus PCI with 2nd ATA/SCSI as an plug in card for that gives choice 2nd ATA/SCSI, or 2nd+3rd VGA, or 2nd PCI bus, or 4th PCI slot put in that 2 RS232 are wanted, remarks about historic systems use put in comment on LPT switchable power being an good thing that users want also added RS232 and LPT remarks to BoardSpec150.html put in USB2 unless it is too expensive (very unlikely to be so put in SATA too fast, 8*150=1200MBit/s > 625MBit/s of Virtex-E IOs because of new faster RAMs redone video bandwidth calculations even full 1600x1200@70HT&24bit/pixel is only 25% of 128bit SDR PC133 and it falls to 12.5% for 128bit DDR PC2100 (2*266MHz*8), so 2nd VGA OK after this calculation even possible, if on non-bus PCI, to do tripple VGA further with BoardSpec600E.html put in remark that 128/144/160bit SDRAM+cache better than 2*64/72/80bit for separate frontside SDRAM and backside L2 cache 2003.01.04 Sat further with BoardSpec600E.html, in ECC also 4*36 and separate ECC word added frequency range for programmable clock 0 30-200MHz, w margin 20-300MHz put in remark about interleaved wiring of D bits of 2*64/72/80bit SDRAMs config add cheap keyboard input but only LEDs output variant 2003.01.05 Sun further with BoardSpec600E.html and BoardSpec150.html rework entire configuration section for better legibility, and modularity in EEPROM switchable loading from 2nd socket, also added LEDs for done/error added IDCs for using PC Reset/Turbo switches and Power/Turbo LEDs for this move clock 0 frequency setting DIP socketed DIP switches to here, with M0-2 first all EEPROM and select/switch stuff then all device load and removeable/default selection stuff then all deliberate selection interface and FEP stuff in pluggable small board FEP also add that main->FEP config can be used with standard cable, as 2nd main system printer or universal IO, with power ATA 2*2 on 1 bus and 2*2*2 with 2 busses, not just 2*2 2003.01.14 Tue VirtexTools project got an offer for contributions so will switch to working on both at same time, not block switching 2003.01.15 Wed board spec since over 1 week no changes in ideas, seem to be quite stable before going into detailled pin count planning, ask Andrew for feedback BoardSpec150.html, a few modifications to make it more interesting own expansion fixed edit error ("prototyping cards" gone missing) added/improved remarks about that being possibly good for Andrews "Minibus" LPT added remarks that this is exactly 17 IOs like an QST0201 IDC40 onto stripboard, so good alternative for Minibus and with advantage that it is same on large board, to share peripherals move RTC/CMOS into rejected interfaces, is too unlikely for this boards uses Ethernet and USB added PHY interface on printer port variant move SRAM fast speed remarks down to cache section user IO connectors put separate ATX and IDC details printer port mention possible 2/3 LPT designs BoardSpec600E.html, USB PHY added remark about 10% of XCV800 for controller Ethernet added remark that definitely no gigabit, use PCI card for this. redone power converters part, comments on 1.8V from the 5V rail because more power there (about half) and more stable (regulator input) 3.3V no converter, direct from power supply, good enough for that move SDRAM slow speed remarks down to cache section memory dual address bus also note less signal load re-ordered board size stuff, put in FlexATX that it may not fit FEP sound better put in 2nd printer port, and plug-on sound module decided to use sould ATX connector space for VGA and still 2 RS232 and use 2nd printer port in where joystick/MIDI connector would be printer port put 2 ports in main section, mention possible 3/4/6 LPT designs done an run through correcting errors and improving, before sending off 2003.01.19 Sun BoardSpec600E.html tidy up remarks about number and position of printer ports 6 is not possible (3*57mm>155mm), but up to 4 goes, commented variants for the 4 printer version put in with VGA, at cost of Ether/USB changed may references to "printer port" to "printer/user" or just "user" 2 RS232 and 2 VGA does not go, 2 RS232 and VGA and sound also not so put in that 1 VGA plus 2 VGA on expansion is preferred variant in RS 232 put in remark that 2 RS232 preferred, so sacrifice sound for VGA VGA added blue HD15 connector, RS232 corrected to turquoise/cyan connectors tidied up hardwired FEP user IO and sharing stuff also tidied up a bit in FPGA FEP stuff, more chapters, improved QST0201 part EEPROM config section put in remark about possibly FPGA self reconfig trigger 2003.01.20 Mon need more Info on hardware details, go reading OSRC as I intended for long time http://www.nondot.org/sabre/os/articles got many IO standards docs, just missing ISA and decent PCI now keyboard ist 2 bidirectional lines, so no key/mouse combined clock BoardSpec600E.html put in acronym CDEC for custom direct expansion connector BoardSpec150.html, noted that with stacked PC/104 and single-ISA FlexATX there is only one slot, so no need to have "single slot" IRQ signals rewrote all the slot and CDEC stuff 2003.01.22 Wed BoardSpec150.html and BoardSpec600E.html move all PCI36 and ISA18 stuff into "Own Expansion Slots", add XT12 and ISA12 switch ISA18 and XT12 to use borrowed IRQ lines not address lines, because buffers there are unidirectional put in remarks about SCSI SE/DE/LVDS variants, which goes in or multi mode? on small board most likely no SCSI at all, also large perhaps CDEC or PCI perhaps no SCSI in standard (just PCI/ISA-sharing ATA for workstations) and then full dual SCSI on CDEC expansion for full power servers 2003.01.23 Thu BoardSpec150.html and BoardSpec600E.html if 2 EEPROM sockets make 1st not writable, or at least write protectable 2003.01.26 Sat - 2003.02.01 Sat was on holiday skiing, offline, only a few notes for BoardSpecs 2003.02.02 Sun BoardSpec600E.html only 2*2 DIMM slots, no need 3*2, not even servers do that remark that BRAMs would even fit for an model B KL-10s 2kx86bit microcode both boards moved all power stuff from FPGA section to form/case section rewrote that section to be more cleared about priorities both massively expanded description of how front panel should work both SCSI tidied up stuff about variants and questions what to do BoardSpec150.html cache remark that even 4k internal ist twice KS-10 size decided to definitely have no 5*8bit or 2*18bit wide SRAMs in this system fixed bug that only 1 ISA slot on FlexATX, as there can be 3, ITX is max 1 done various XAPP reading on reconfiguration, requires stopping device is this still sensible to use in an FPGA-PC, stopping the processor blank doing it from the FEP is implicit in loading stuff, no special support from the FPGA it stops it, so no chance to recover, only full reconfig goes so this will require telling the FEP to do it, only modules, not swapping this is better anyway, as it gives continuous state to the extensions also had a look at the Virtex-E LVDS stuff, instead of external LVDS drivers may be good for SCSI but will double pin usage, with this SCSI only on CDEC 2003.02.05 Wed BoardSpec150.html and BoardSpec600E.html text tidy up BoardSpec600E.html definitely separate tag data bits put in better view on FlexATX, CDEC possibly ISA plugs sharing with AGP 2003.02.09 Sun Attila further set of BoardSpec critics, process them BoardSpec600E.html claimed video bandwidth calculation wrong is actually right number, but badly written, missing steps (scan back) improved text to show full calculation done also RTC outdated and Y2K bug, so put in more open specification also possibly time-only and separate larger battery backed CMOS SRAM FPGA FEP put in remark about lot of work to "get going" so this should be delivered with an pre-loaded disk-less OS design in it BoardSpec150.html main problem is design is too costly (small stuff adds up) perhaps drop programmable clock, just 2 DIPs on clocks 0+1, 2+3 external memory reduce cost, just 1..3 8bit or 1..2 18bit, soldered, no sockets also same video bandwidth calculation improvement as in large board 2nd RS232 added remark that perhaps better save cost, can use printer port in addition to 2nd LPT (instead of 2 RS232) also possible 3rd (VGA + PS/2) make it more clear that this is intended as "small brother" to large board 2003.02.12 Wed Hans B Pufal sent URL to Xilinxes VIIpro proto board that can run Linux not ATX format, only 32bit DDR SDRAM and no need for the PPC or the 4 gigabit fiber Ethernets but interesting to see how they design an full power universal board but both IIC and SPI are patent encumbered, so we can not use them 2003.02.17 Mon do style finishing off work on both BoardSpecxxx.html and while at it put more questions and remarks to Andrew into text better introduction section, what the boards aim at being usable for BoardSpec150.html better organising of format variants, all 5 in the