At present no detailed pinouts or pin counts have been investigated. Dito no checks if all the desired functions will fit the available pins. Or any decisions about some functions sharing pins.
Form Factor, Case and Power
Expansion and Bus
User IO Devices
Configuring the FPGA
This board is intended to be an small, lowest cost, alternative to the larger and so more expensive board, for users that do not want to pay for its large feature set, or use its powerful but more complicated memory. Small memory address range and external data width/throughput are the main differences to the large board. Smaller FPGA and reduced IO selection and less configuration options are the other differences. This board would complement the large one, making them into an series of boards.
This is NOT an project by Andrew Grillet, unless he adopts it when I tell him about it. In the mean time I have asked him and it seems unlikely (not enough sales volume, better concentrate on one board).
This functionality could also be implemented using Andrews Quickstart QST0201 board and making the rest here as an board onto which it gets plugged (QST0201 was designed for such plug-on usage).
[Andrew: One of my users thinks this second board is not worth it. Less than 1/2 features (1/3 LUTs, 1/4 BRAMS, 1/4 IOs, a bit less periphery) for over 1/2 cost (board size, periphery components, handling cost). Dropping the FEP section from the 600E board design reduces that ones cost (so less saving here), and got rid of using this board for pluggable FEP. Dropping L2 cache from the 600E board reduces the saving even more. OTOH this board still allows lower cost entry into FPGA PCs, but if the 600E board needs to drop to an 300E even this differentiation reduces itsself. And there is the possibly of 2 different formats (large as FlexATX, this as industrial), but this adds problems of market fragmentation, designs need adapting]
Top of range, according to the Xilinx data sheet, is the XC2S200 part (with 2*28x2*42 LUTs and 2x7 BRAMs) largest QFP in an QFP208 case (gives 140 user IOs + 4 CLKs) using 1'335'840 (= 2M PROM) config bits. This choice of chip is also given if using an QST0201 as base.
But that just misses fitting in an cheaper 1M PROM such as XC18V01, so for quite a bit of lowered cost use the XC2S150 part (with 2*24x2*36 LUTs and 2x6 BRAMs) using 1'040'096 (= 1M PROM) config bits. This is also the only QST0201 variant which has EEPROM support, if that is used as base.
Using such an relatively low pinout device and QFP case will fit an cheap 4-layer board, so all other parts need to fit this also. If making an base board with an QST0201 plugged on it, the base board should even fit in 2 layers if possible, so only use simple parts that will fit that.
For 8/12/16/18/20/24bit systems max 24bit memory is enough. If small 32/36bit systems are to be made (for low cost educational and experimental RISC users), split their data bus into 2*16/18bit (which is completely acceptable for such uses).
Parity is unlikely to be wanted. If wanted any designs under the maximal width can do it anyway with the remaining bits for wider designs. This will require entire-word writes, which is acceptable for those few users.
ECC is way over the top for these sizes of designs.
Appart from the smaller/cheaper FPGA this is the main difference of this board from the 600E board. If only making the 600E, then make sure it has either its L2 cache or an large CMOS RAM, so that it can run small designs without needing (S)DRAM DIMMs.
There exist multiple variants:
3 chips allow all intended widths up to 24bit (and also 16+8bit), 2 chips force 18/20/24bit to multiplex but rest goes, minimal 1 chip forces 12/16/18/20/24bit to multiplex but is the cheapest (slightly).
Possibly socketed memories and user selectable width/price (8/16/24bit) trade off, so that users can put the in the memory width that their design requires, 1 chip for 8bit, 2 for 12/16bit, 3 for 18/20/24/16+8bit. But sockets also cost (so killing part/all(?) of the savings), and they require the larger (and more expensive?) socketable DIP cases. So better not socketing.
Better than socketing offer trade off by soldering in 2 chips and just put in space/wiring/pads for user adding an 3rd chip if over 16bit is wanted. This looks cheaper than sockets. But is the saving relative to all 3 chips worth the >16bit users hassle? And the 3rd chip can also be used for an larger 786kx16bit memory, or for 512kx16bit main plus 512kx8bit video memory with shared address bus.
Socketing would also have allowed size (32k/128k/512k) selection. But this requires additional jumpers/switches (more cost and space) to direct the power pin, because of different chip lenghts (2 pins more per *4 size). So better only support one size, best 512k as this is the largest, like in using the largest FPGA
One single chip is already wide enough for 8/12/16/18bit designs, so saving space. But this fails 20/24bit designs. 2 chips gives 512kx18, same width just longer, the same 1024kByte as SRAM 512kx(2..3)*8, useful for 16/18bit with MMUs (max for 8086/88) and small 32/36bit (max mem for an KA-10).
These are TQFP cases, need soldering in, no socketable user selectable width or length trade off possible. But also trade off less neccessary, as one single chip is very likely cheaper than 3 sockets with even the minimal 1 chip inserted. OTOH 1 chip soldered and 2nd to user-solder is more difficult. And these are larger pin count and case size than 8bit.
SyncSRAMs or ZBT SRAMs are also more difficult to use (but how much?), due to their synchronous interfaces. Their extra speed (how much, 143MHz = 7ns, async exist at that speed) is not needed here, but it may partially offset 2*16/18bit access cost for 32/36bit designs
If one wants to cache, the XC2S150 has 12 BRAMs (= 6kByte), usable for internal (L1) cache, data and tags, so that will allow max 4kByte size (so long no other use of BRAMs is intended). This is 2 times the 512*36 of cache in the KS-10, and we have here SRAM memory that is 30 times as fast as the core memory used there.
These formats should be capable of fitting either an QST0201 (15.24x10.16cm) huckepack (IO components can go underneath the QST0201), as also be implementable as an standallone board.
Far better alternative would be to not use ATX (which the large board uses) and go for an even smaller industrial format board:
These formats require the board to be an standallone design, not an QST0201 huckepack board, as such formats are smaller/same/similar size as the QST0201 itself, and connectors at edge collide with QST0201s connectors.
An further alternative is to make such an industrial format embeddable, with all of its IOs/power/config on IDC connectors (like QST0201), so one can cable to remote connectors on a case (fairly common practise in industrial stuff anyway), or use this board as an plug-in component anywhere else (like the QST0201 is). With euro card format this variant could even be be done using QST0201 as the IDCs can be positioned anywhere, inside the board, not just at the edges.
One possibility would be to offer both ATX and industrial formats, but this costs double in layouting work/time. Layout cost could be reduced by putting an exact replica of the industrial format layout on an ATX board, with just the IO and power connectors running out to the ATX PC style connectors. Even better for dual usage, would be to offer only the all-IDC embeddable format, and an separate cheap (2-layer) ATX format "connector driveout" board for ATX PC style connectors, into which the embeddable format board is plugged in.
[Andrew: I prefer the industrial variants, and within them euro card format. For lab or control stuff (and that includes hobbyist experiment and educational labs) any of these smaller formats is preferable. For FEP usage (plug-on or separate) they are even needed, to fit as second board inside an ATX case. Also these formats differentiate better from the large board. One of my users also commented that this board should not be bigger than QST0201, that also goes against any one of the ATX/ITX variants. For FEP the embeddable variant would be the best (direct plug on), but else the normal industrial one is the best (no IDC to other connector conversion needed)]
Voltage usage is same, apart from VCCINT (FPGA core) being 2.5V instead of 1.8V.
The board does not need to be capable of controlling an ATX power supply. But this is allowed if not too expensive.
ISA is the obvious choice for small ATX form factors, PC/104 is the sensible bus for industrial form factors. From here on the term "ISA bus" always applies to both ISA or PC/104 connector versions, unless specially noted.
32bit ISA variants such as EISA and Vesa VLB are too wide, like PCI, and less useful than PCI is, so do not support them.
Possibly no bus at all. Have ATA share address/data pins with memory. Save pins for 2nd LPT/userport and still having full other IO stuff.
ISA use is identical to PCI use, just replace 32bit with 16bit.
To save IOs leave A16..A23 unimplemented. Are only used for addressing on board extended memory (none here) by ISA DMA (seldom used, Adaptec AHA154x and PAS16 sound, that is about it), or slot card extended memory by the processor (no need here). Also lack of IO pins may require running A and D from the same shared FPGA pins, this requires latching A into external registers in A bus drivers.
For 18bit ISA cards can be used, simply wasting 2 bits of the IO data bus, like the original KS-10 which used 16bit Unibus PDP-11 cards. Put an 8*18 to 9*16 converter in to the DMA circuits in the FPGA. For 12bit designs use XT (bit) devices, wasting 4 bits.
It should be possible to use direct FPGA connections, no bus drivers. But possibly put in bus drivers to decouple the slow ISA bus from the faster ATA accesses (is this needed?), at least on the subset of shared pins.
ISA has no "reserved" lines, so (miss-)use 2 of the IRQ lines for 16bit to 18bit extension for an true 18bit "ISA-18" bus. For 12bit cut down full ISA to an "ISA-12" bus.
VGA video out of the FPGA comes from main memory, so it is an UMA (unified memory architecture) system. But memory bandwidth is no problem. Even 1024x768@70Hz (which with 8bit/pixel is 3/4 of 1024k RAM size!) requires only (1024*5/4)*(768+32)*70 = 71.68MHz pixels. At maximal possible 8bit/pixel from minimal 16 bit/cycle this gives max 71.68*8/16 = 35.84MHz memory. That is max only 25.06% of 143MHz (= 7ns SRAM). Reducing resolution to 800x600@60Hz and 4bit/pixel requires only 37.92MHz pixels and 9.48MHz memory, which is 6.62% of 143MHz, so no problem at all. This should stay under 50% (if L1 cache) or 10% (if no cache) of memory bandwidth, to not kill off processor power. And designs without cache are most likely not speed critical, so slowing them down does not matter.
Is an 2nd RS232 useful? This small board is more likely to use SLIP/PPP connecton to larger computer as no Ethernet on this board, so more usefull. All other reasons remain identical. [Andrew: One of my users thinks 2nd RS232 is not worth the parts cost, to better differentiate on price, I prefer it with 2nd RS232, unless running very low on pins]
This may also be an pin count problem, 17 (= 1/8 of all) pins for something many may not use. So perhaps use an separate analog board on the printer ports IDC connector (in ATX variant put in an IDC parallel to the DB25) or make the FPGA pins switchable between the 2 uses if that does not cost too much. Even if enough pins possibly make this separate board or switchable, to get 2 printer/user ports without losing the built-in 2*RS232 and VGA.
SCSI is necessary (including full selectable SE/LVD modes!) for FEP usage, to access the shared SCSI disks. But that can also (and should) be done by sharing the main boards driver circuits. Missuse this boards ISA or PC/104 bus connector for accessing to them, and all other main board IO buses and drives (ATA, SCSI, USB, perhaps even floppy).
If multiple configuration only cheapest socket variant, no 2 sockets or switching stuff.
Either use an minimal 1MBit (= 128kByte) flash chip. Or possibly put in an larger 4MBit (= 512kByte) flash chip, and offer space for 4 configurations with only one flash chip (and the uC).
If there is battery backed main memory on this board, possibly battery back this SRAM also. This also allows the alternative flash-less design, with only SRAM for 4 configs. This will fit in one 4MBit (= 512kx8) chip, and it saves having Flash+SRAM, just one chip for both jobs.
If 256kx18 chips were used for main memory, then possibly use one here, if reducing part list size saves cost. Use this one definitely in 9 bit wide wiring to save uC pins, as only 8bit data are used anyway.
This page is by Neil Franklin, last modification 2003.06.18