Home | Projects | FPGA-PC | Board Spec XC2S150

(Differential) Spec for an XC2S150 based small ATX size or Eurocard FPGA-PC Board

This is an preliminary spec, only for discussing of the feature set

At present no detailed pinouts or pin counts have been investigated. Dito no checks if all the desired functions will fit the available pins. Or any decisions about some functions sharing pins.

FPGA Section
Form Factor, Case and Power
Expansion and Bus
User IO Devices
Storage Devices
Configuring the FPGA



Identical to the large XC2S600E based FPGA-PC board spec.

Newer Development

While designing the large systems (= 32/36/64bit) XC2S600E based FPGA-PC board, I had a few thoughts on an small systems (= 8/12/16/18/20/24bit) board. Assumed uses for this board are: This board is not assumed to be used for daily PC style work. Though it should be usable for small specialty types of jobs.

This board is intended to be an small, lowest cost, alternative to the larger and so more expensive board, for users that do not want to pay for its large feature set, or use its powerful but more complicated memory. Small memory address range and external data width/throughput are the main differences to the large board. Smaller FPGA and reduced IO selection and less configuration options are the other differences. This board would complement the large one, making them into an series of boards.

This is NOT an project by Andrew Grillet, unless he adopts it when I tell him about it. In the mean time I have asked him and it seems unlikely (not enough sales volume, better concentrate on one board).

This functionality could also be implemented using Andrews Quickstart QST0201 board and making the rest here as an board onto which it gets plugged (QST0201 was designed for such plug-on usage).

[Andrew: One of my users thinks this second board is not worth it. Less than 1/2 features (1/3 LUTs, 1/4 BRAMS, 1/4 IOs, a bit less periphery) for over 1/2 cost (board size, periphery components, handling cost). Dropping the FEP section from the 600E board design reduces that ones cost (so less saving here), and got rid of using this board for pluggable FEP. Dropping L2 cache from the 600E board reduces the saving even more. OTOH this board still allows lower cost entry into FPGA PCs, but if the 600E board needs to drop to an 300E even this differentiation reduces itsself. And there is the possibly of 2 different formats (large as FlexATX, this as industrial), but this adds problems of market fragmentation, designs need adapting]

File Layout

Originally this file was an independant description, copying much text from the large board file. This makes it difficult to work (double edits) and also to compare them, as it is neccessary to read both files and pick out the differences. So I have changed this spec to be just an differential description, relative to the large board spec.

FPGA Section

Chip Selection

The plan ist to use an Xilinx Spartan-II chip, as it has quite a bit of space at very low cost. The board will use an QFP part, because BGA is too expensive for it. Within that restriction it will use the top of range part.

Top of range, according to the Xilinx data sheet, is the XC2S200 part (with 2*28x2*42 LUTs and 2x7 BRAMs) largest QFP in an QFP208 case (gives 140 user IOs + 4 CLKs) using 1'335'840 (= 2M PROM) config bits. This choice of chip is also given if using an QST0201 as base.

But that just misses fitting in an cheaper 1M PROM such as XC18V01, so for quite a bit of lowered cost use the XC2S150 part (with 2*24x2*36 LUTs and 2x6 BRAMs) using 1'040'096 (= 1M PROM) config bits. This is also the only QST0201 variant which has EEPROM support, if that is used as base.

Using such an relatively low pinout device and QFP case will fit an cheap 4-layer board, so all other parts need to fit this also. If making an base board with an QST0201 plugged on it, the base board should even fit in 2 layers if possible, so only use simple parts that will fit that.

Clocking Circuits

The Spartan-II can take up to 4 global clocks. The board should offer the use of all 4 of these, for maximal flexibility. This does not cost any of the 140 user IOs. Drive them by the identical sources as the large board. [Andrew: One user remarks that he regards this amount of clock options as too expensive for the small board. Perhaps just put in 2 DIPs for clock 0+1 and have 2+3 from LPT. But 2 clocks on LPT makes this board not wiring compatible with the large one, so perhaps simply put in 3 DIPs. But that may not save much relative to the better full thing]


This should be no problem in such an small FPGA. If it is, an set of cooling fins should be enough. These should be facultative. To save cost no pre-done mounting stuff. In worst case clock the design slower.


Memory Word Width

Memory architecture is the main difference to the large board.

For 8/12/16/18/20/24bit systems max 24bit memory is enough. If small 32/36bit systems are to be made (for low cost educational and experimental RISC users), split their data bus into 2*16/18bit (which is completely acceptable for such uses).

Parity is unlikely to be wanted. If wanted any designs under the maximal width can do it anyway with the remaining bits for wider designs. This will require entire-word writes, which is acceptable for those few users.

ECC is way over the top for these sizes of designs.

Memory Line Width

Single data bus wide memory, is definitely enough here. No dual/etc data bus wide memory which requires multiplexing in the FPGA and more IO pins of the small chip case. That gives half data bus wide for 32/36bit.

Appart from the smaller/cheaper FPGA this is the main difference of this board from the 600E board. If only making the 600E, then make sure it has either its L2 cache or an large CMOS RAM, so that it can run small designs without needing (S)DRAM DIMMs.

Memory Chips

As this is intended for small processors, with small address space and small memories, no (S)DRAM is needed here. So use simple SRAMs, which are not just cheaper and use less space, but also easier for beginners to use.

There exist multiple variants:

Async SRAM is simpler to use and goes up to the full 24bit. SyncSRAM or ZBT SRAM are more involved to use. So it looks like SRAM is better for this board. [Andrew: I prefer the full 3*8bit. OTOH one of my users says I should forget >16bit, as most users will be doing 16bit, and 2*8bit is cheapest for them. So go for either 3*8bit, or 2*8bit with 3rd 8bit solder space, if that really saves relevant amounts of cost]

Memory Cache

SRAM is fast to access, so it does not require any caching. It can deliver 18bit data at least at 100MHz (10ns SRAMs) and up to 143MHz (7ns SyncSRAM or ZBT SRAM). If memory is SyncSRAM or ZBT SRAM, it is L2 cache memory anyway. So no gain by having an L2 cache. Also most small designs are not expected to be speed critical anyway.

If one wants to cache, the XC2S150 has 12 BRAMs (= 6kByte), usable for internal (L1) cache, data and tags, so that will allow max 4kByte size (so long no other use of BRAMs is intended). This is 2 times the 512*36 of cache in the KS-10, and we have here SRAM memory that is 30 times as fast as the core memory used there.

Form Factor, Case and Power

Board Type

Apart from FPGA and memory, this is the 3rd place where this board can differ from the large one. There are multiple possible board formats, some ATX based:

These formats should be capable of fitting either an QST0201 (15.24x10.16cm) huckepack (IO components can go underneath the QST0201), as also be implementable as an standallone board.

Far better alternative would be to not use ATX (which the large board uses) and go for an even smaller industrial format board:

These formats require the board to be an standallone design, not an QST0201 huckepack board, as such formats are smaller/same/similar size as the QST0201 itself, and connectors at edge collide with QST0201s connectors.

An further alternative is to make such an industrial format embeddable, with all of its IOs/power/config on IDC connectors (like QST0201), so one can cable to remote connectors on a case (fairly common practise in industrial stuff anyway), or use this board as an plug-in component anywhere else (like the QST0201 is). With euro card format this variant could even be be done using QST0201 as the IDCs can be positioned anywhere, inside the board, not just at the edges.

One possibility would be to offer both ATX and industrial formats, but this costs double in layouting work/time. Layout cost could be reduced by putting an exact replica of the industrial format layout on an ATX board, with just the IO and power connectors running out to the ATX PC style connectors. Even better for dual usage, would be to offer only the all-IDC embeddable format, and an separate cheap (2-layer) ATX format "connector driveout" board for ATX PC style connectors, into which the embeddable format board is plugged in.

[Andrew: I prefer the industrial variants, and within them euro card format. For lab or control stuff (and that includes hobbyist experiment and educational labs) any of these smaller formats is preferable. For FEP usage (plug-on or separate) they are even needed, to fit as second board inside an ATX case. Also these formats differentiate better from the large board. One of my users also commented that this board should not be bigger than QST0201, that also goes against any one of the ATX/ITX variants. For FEP the embeddable variant would be the best (direct plug on), but else the normal industrial one is the best (no IDC to other connector conversion needed)]

Power Supply

If ATX format, identical supplies as large board. Industrial supplies for PC/104 often use an AMP connector and only have 5V and 12V, and lack 3.3V altogether. This is no problem, as on ATX 3.3V power should be avoided anyway. So this design should require only 12/5V parts.

Voltage usage is same, apart from VCCINT (FPGA core) being 2.5V instead of 1.8V.

The board does not need to be capable of controlling an ATX power supply. But this is allowed if not too expensive.

Front Pannels

Identical with the large board. Same plug-no device.

Expansion and Bus

Industry Standard Architecture (ISA) Bus Slots

PCI slots are 32bit and so too wide for the intended 8/12/16/18bit designs. Same applies even more to 64bit or 66MHz PCI or AGP. So go for an smaller and simpler bus. Or possibly no bus at all, just LPT/userport connectors.

ISA is the obvious choice for small ATX form factors, PC/104 is the sensible bus for industrial form factors. From here on the term "ISA bus" always applies to both ISA or PC/104 connector versions, unless specially noted.

32bit ISA variants such as EISA and Vesa VLB are too wide, like PCI, and less useful than PCI is, so do not support them.

Possibly no bus at all. Have ATA share address/data pins with memory. Save pins for 2nd LPT/userport and still having full other IO stuff.

ISA use is identical to PCI use, just replace 32bit with 16bit.

To save IOs leave A16..A23 unimplemented. Are only used for addressing on board extended memory (none here) by ISA DMA (seldom used, Adaptec AHA154x and PAS16 sound, that is about it), or slot card extended memory by the processor (no need here). Also lack of IO pins may require running A and D from the same shared FPGA pins, this requires latching A into external registers in A bus drivers.

For 18bit ISA cards can be used, simply wasting 2 bits of the IO data bus, like the original KS-10 which used 16bit Unibus PDP-11 cards. Put an 8*18 to 9*16 converter in to the DMA circuits in the FPGA. For 12bit designs use XT (bit) devices, wasting 4 bits.

It should be possible to use direct FPGA connections, no bus drivers. But possibly put in bus drivers to decouple the slow ISA bus from the faster ATA accesses (is this needed?), at least on the subset of shared pins.

Custom Expansion Bus Slots

Identical. Just replace "PCI and ISA" with "ISA and PC/104".

ISA has no "reserved" lines, so (miss-)use 2 of the IRQ lines for 16bit to 18bit extension for an true 18bit "ISA-18" bus. For 12bit cut down full ISA to an "ISA-12" bus.

Custom Direct Expansion Connector

With QFP208 and only 140 pins there is not enough space for an custom direct expansion connector (CDEC) separate from the ISA bus on this board. OTOH there will most likely only be one bus connector, so no collision problems. So one can missuse the subset of direct wired ISA or PC/104 pins, that are not shared with ATA and so need no buffers to shield them.

User IO Devices

Basics here are identical to large board. But less pins and cost reduction place tighter limits on what can to be included.

PC case LEDs (Power/Turbo/HDD) & Switches (Turbo/Reset/Keylock)


PS/2 connectors

Identical. If industrial with normal connectors, use horizontal connectors, as "vertically stacked" makes board unneccessary high. If embedded industrial with IDC connectors not decided yet.

VGA connector

Identical, appart from changes due to less pins and memory. If embedded industrial with IDC connector not decided yet. Reduced colour depth: Use buffers-and-bunch-of-resistors DACs, as these will work up to 4bit and under 100MHz. So don't use any premade Video-DACs (which bring supply problems and most likely cost more) or even worse an RAMDAC chip (which in addition also costs pins and circuits, for programming the colour table).

VGA video out of the FPGA comes from main memory, so it is an UMA (unified memory architecture) system. But memory bandwidth is no problem. Even 1024x768@70Hz (which with 8bit/pixel is 3/4 of 1024k RAM size!) requires only (1024*5/4)*(768+32)*70 = 71.68MHz pixels. At maximal possible 8bit/pixel from minimal 16 bit/cycle this gives max 71.68*8/16 = 35.84MHz memory. That is max only 25.06% of 143MHz (= 7ns SRAM). Reducing resolution to 800x600@60Hz and 4bit/pixel requires only 37.92MHz pixels and 9.48MHz memory, which is 6.62% of 143MHz, so no problem at all. This should stay under 50% (if L1 cache) or 10% (if no cache) of memory bandwidth, to not kill off processor power. And designs without cache are most likely not speed critical, so slowing them down does not matter.

PC Beep Speaker


RS232 Serial Interface(s)

Identical. If embedded industrial with IDC connectors use the 10pin cable-to-slot connector used on pre-ATX PCs with on-board RS232.

Is an 2nd RS232 useful? This small board is more likely to use SLIP/PPP connecton to larger computer as no Ethernet on this board, so more usefull. All other reasons remain identical. [Andrew: One of my users thinks 2nd RS232 is not worth the parts cost, to better differentiate on price, I prefer it with 2nd RS232, unless running very low on pins]

LPT/Printer Port/General User Port

Identical. If embedded industrial with IDC connectors use the 26pin cable-to-slot connector used on pre-ATX PCs with on-board LPT.

Additional LPT/Printer Port/General User Ports

Identical reasons/placing as large board. Just details in implementation: [Andrew: So the 2 user port version here also seems to be the best]

Real Time Clock (RTC)

This is not much use in simple systems. In worst case it can be added via ISA. So only add it if next to no cost (unlikely with battery holder + quarz + chip needed).

Battery backed CMOS RAM

This is also not much use here. If battery backing anything, then the main SRAM memory, giving the system "constant memory". That can be used for disk-less operation (some SRAM as simulated ROM), or as simulated CMOS, or as RAM disk (or simulated ROM disk) for non-drive operation.


Not in this small board. Use an printer/user port module or an ISA card if user wants it. 2nd printer/user port is worth even more here, due to the limited pin count.


Not in this small board. Use RS232 with SLIP/PPP. If more than that is needed, use an ISA Ethernet card or PHY chip on user port.

Universal Serial Bus (USB)

Not in this small board. Use RS232 or printer port based peripherals. Or use an ISA USB card (if they exist!), or an PHY chip on an printer/user port. OTOH USB is less likely to exist for ISA, and could be useful for "flash plugs" instead of an ATA flash disk, or even for an USB floppy instead of on board, so perhaps put it in.

Rejected Interfaces

All the "rejected" stuff from the large board applies here also, even more.

Storage Devices

Basics here are identical to large board. But less pins and cost reduction place limits on what is to be included.

Floppy connector


This may also be an pin count problem, 17 (= 1/8 of all) pins for something many may not use. So perhaps use an separate analog board on the printer ports IDC connector (in ATX variant put in an IDC parallel to the DB25) or make the FPGA pins switchable between the 2 uses if that does not cost too much. Even if enough pins possibly make this separate board or switchable, to get 2 printer/user ports without losing the built-in 2*RS232 and VGA.

40pin ATA connector

Identical. Only 1 ATA connector, enough for 2 drives, no more needed, save 2nd connector.

68pin SCSI-W connector

SCSI is not sensible on this small/cheap board. It is most likely over the top for small/experimental system usage. If it is wanted get an ISA or PC/104 based SCSI card of the right type. Or put some SCSI drivers on an prototyping card.

SCSI is necessary (including full selectable SE/LVD modes!) for FEP usage, to access the shared SCSI disks. But that can also (and should) be done by sharing the main boards driver circuits. Missuse this boards ISA or PC/104 bus connector for accessing to them, and all other main board IO buses and drives (ATA, SCSI, USB, perhaps even floppy).

2nd independant ATA and/or SCSI-W buses(s)

Not in this small board, as this is no server board. ATA is not even 2 connectors on the first bus, and SCSI is out anyway. Save the pins for other IO. If more are wanted, then use an ISA or PC/104 card.

Rejected Interfaces

All the "rejected" stuff from the large board applies here also, even more.

Configuring the FPGA

External Configuring from Development System


Internal Configuring from EEPROM

Identical. For XC2S150 the 1MBit XC18V01 is the right part. This is the main reason against XCS200, it requires the double size/cost XC18V02.

If multiple configuration only cheapest socket variant, no 2 sockets or switching stuff.

Internal Configuring from Flash by Microcontroller


Either use an minimal 1MBit (= 128kByte) flash chip. Or possibly put in an larger 4MBit (= 512kByte) flash chip, and offer space for 4 configurations with only one flash chip (and the uC).

Internal Configuring from Devices via the FPGA by Microcontroller


If there is battery backed main memory on this board, possibly battery back this SRAM also. This also allows the alternative flash-less design, with only SRAM for 4 configs. This will fit in one 4MBit (= 512kx8) chip, and it saves having Flash+SRAM, just one chip for both jobs.

If 256kx18 chips were used for main memory, then possibly use one here, if reducing part list size saves cost. Use this one definitely in 9 bit wide wiring to save uC pins, as only 8bit data are used anyway.

Partial Reconfigurability

[Andrew: All complex or even FEP config stuff is totally off here. OTOH this board can be used as FEP, if this is still desired]
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This page is by Neil Franklin, last modification 2003.06.18