Microchip PIC16F5x (12bit "base-line" family) Instruction Set author Neil Franklin, last modification 2014.05.15 Sources for this data: ---------------------- 1. Official Datasheet PDF from Microchip Website http://ww1.microchip.com/downloads/en/DeviceDoc/41213C.pdf Very unlikely to contain errors. Of course errors of my own are to be expected. Processor Registers: -------------------- (in order: data, address, pc, flags, auxillary) W 8bit Working Register (Accumulator) (standalone) FSR [578]bit File Select Register (Indirect Address) (SFR 04) INDF 8bit INDirect File (Data from/to Indirect Addr) (SFR 00) PC [9/11]bit Program Counter (PCL 8bit SFR 02) STATUS 8bit Status Register (= flags + program page select) (SFR 03) IO Device Registers: -------------------- TMR0 8bit Timer 0 (SFR 01) OPTION 8bit Timer 0 and Prescaler Setup (OPTION (= TRIS02)) PORTA 4bit Port A0..3 (SFR 05) TRISA 4bit Tristate Register Port A (TRIS05) PORTB 8bit Port B0..7 (SFR 06) TRISB 8bit Tristate Register Port B (TRIS06) [PORTC] 8bit Port C0..7 (SFR 07) [TRISC] 8bit Tristate Register Port C (TRIS07) [PORTD] 8bit Port D0..7 (SFR 08) [TRISD] 8bit Tristate Register Port D (TRIS08) [PORTE] 8bit Port E4..7 (SFR 09) [TRISE] 4bit Tristate Register Port E (TRIS09) Status Register, Flags: ----------------------- (in order: from MSB/7 to LSB/0) bit 76543210 flag -AATPZDC PA2 reserved PA1 Page Address 1 (PC10 for GOTO/CALL instructions) PA0 " 0 (PC9 for GOTO/CALL instructions) /TO Time-out (0 = restart after WDT timed out) /PD Power-down (0 = wakeup after SLEEP instruction executed Z Zero (result all bits cleared) DC Digit Carry/Borrow (arithmetic result carry bit3->bit4) C Carry/Borrow (arithmetic result carry bit7->"bit8") Memory: ------- Program memory 512*12bit or paged 2048*12bit (9bit or 11bit address space) Data memory 16*8bit (5bit address space, 00..0F section) 5*8bit (00..04) of these are SFRs [2..5]*8bit (05..0[679]) of these are IO ports Data memory paged [148]*16*8bit (5bit address space, 10..1F section) Addressing Modes, in Assembler Syntax: -------------------------------------- (in order: reg, immediate, address, reg indirect, pc) W working register k literal8 (= immediate8) f register file address f,d register file address and destination (W or f) f,b register file bit address INDF FSR indirect (INDF is label for address 0) k absolute-address8 (only CALL instr) k absolute-address9 (only GOTO instr) Instruction Formats, in Machine Code Words: ------------------------------------------- (in order: simple, immediate, memory, bit, jump) ooo opcode12 okk opcode4+immediate8 oof opcode7+address5 obf opcode4+bitindex3+address5 okk opcode4+progmem-address8 (only CALL instr) okk opcode3+progmem-address9 (only GOTO instr) Instruction Bit Patterns and Operations: ---------------------------------------- (in order: functional grouping: arithmetic, data transfer, jumps, auxillary) arithmetic/logic ooooood fffff oooooo. ..... opcode operation 000010. ..... SUBWF d = f - W; FlagsCDZ "SUBtract W from f" (= reverse of normal subtract) 000100. ..... IORWF d = W bitwise-OR f; FlagsZ "Inclusive OR W with F" 000101. ..... ANDWF d = W bitwise-AND f; FlagsZ "AND W with F" 000110. ..... XORWF d = W bitwise-excl-OR f; FlagsZ "eXclusiv OR W with F" 000111. ..... ADDWF d = W + f; FlagsCDZ "ADD W and F" ......d ..... destination ......0 ..... store in W ......1 ..... store in file register f ....... fffff register file address ooookkk kkkkk oooo... ..... opcode operation 1101... ..... IORLW W = W bitwise-OR k; FlagsZ "Incl OR Literal with W" 1110... ..... ANDLW W = W bitwise-AND k; FlagsZ "AND Literal with W" 1111... ..... XORLW W = W bitwise-excl-OR k; FlagsZ "eXcl OR Lit with W" ....kkk kkkkk literal8 (= immediate8) increment/decrement ooooood fffff oooooo. ..... opcode operation 000011. ..... DECF d = f - 1; FlagsZ "DECrement F" 001010. ..... INCF d = f + 1; FlagsZ "INCrement F" ......d ..... destination ......0 ..... store in W ......1 ..... store in file register f ....... fffff register file address shift/rotate/swap ooooood fffff oooooo. ..... opcode operation 001100. ..... RRF d,FlagC = FlagC,f; FlagsC "Ro Right F through carry F" 001101. ..... RLF FlagC,d = f,FlagC; FlagsC "Rot Left F through carry F" 001110. ..... SWAPF d = f(bit3..0,7..4) "SWAP nibbles in F" ......d ..... destination ......0 ..... store in W ......1 ..... store in file register f ....... fffff register file address bit manipulation oooobbb fffff oooo... ..... opcode operation 0100bbb fffff BCF f = f bitwise-AND NOT 2^bit "Bit Clear F" 0101bbb fffff BSF f = f bitwise-OR 2^bit "Bit Set F" ....bbb ..... bit (0..7) ....... fffff register file address other specialised arithmetic ooooood fffff ooooooo ..... opcode operation 0000010 ..... CLRW W = 0; FlagsZ (Z=1) "CLeaR W" 0000011 ..... CLRF f = 0; FlagsZ (Z=1) "CLeaR F" 001001. ..... COMF d = bitwise-NOT f; FlagsZ "COMplement F" ......d ..... destination ......0 ..... store in W (only for CLRW and COMF) ......1 ..... store in file register f (only for CLRF and COMF) ....... fffff register file address (only 00000 for CLRW) load/store ooooood fffff ooooooo ..... opcode operation 0000001 ..... MOVWF f = W "MOVe W to F" (= store w to f) 001000. ..... MOVF d = f; FlagsZ "MOVe F" (= load from f) ......d ..... destination ......0 ..... store in W (only for MOVF) ......1 ..... store in file register f ....... fffff register file address ooookkk kkkkk oooo... ..... opcode operation 1100... ..... MOVLW W = k "MOVe Literal to W" ....kkk kkkkk literal8 (= immediate8) other specialised data transfer ooooooo ooooo opcode operation 0000000 00010 OPTION OPTION = W "load OPTION register" 0000000 00fff TRIS f TRISf = W "load TRIS register" jumps/subroutines and reset/interrupts ooooooo ooooo opcode operation 0000000 00000 NOP do nothing "No OPeration" 0000000 00011 SLEEP WDT = 0; WDT.pre = 0; /TO = 1; /PD = 0 "go into standby (SLEEP) mode" 0000000 00100 CLRWDT WDT = 0; WDT.pre = 0; /TO = 1; /PD = 1 "CLeaR WatchDog Timer" ooookkk kkkkk oooo... ..... opcode operation 1000... ..... RETLW W = k; PC = TOS "RETurn, place Literal in W" 1001... ..... CALL TOS = PC + 1; PC = status(PA),0,k "subroutine CALL" 101k... ..... GOTO PC = status(PA),k "unconditional branch (jump, GOTO)" ...kkkk kkkkk absolute-address8or9 (CALL 8 and GOTO 9) --- pin /MCLR TRIS = FF; OPTION = FF; PCL = FF; STATUS = 1F "MPU CLeaR" branches/conditionals ooooood fffff ooooooo ..... opcode operation 001011d fffff DECFSZ d = f - 1; if d = 0 then PC = PC + 1 "DECrement F, Skip if Zero" 001111d fffff INCFSZ d = f + 1; if d = 0 then PC = PC + 1 "INCrement F, Skip if Zero" ......d ..... destination ......0 ..... store in W ......1 ..... store in file register f ....... fffff register file address oooobbb fffff oooo... ..... opcode operation 0110bbb fffff BTFSC if (f bitwise-AND 2^bit) = 0 then PC = PC + 1 "Bit Test F, Skip if Clear" 0111bbb fffff BTFSS if (f bitwise-AND 2^bit) = 1 then PC = PC + 1 "Bit Test F, Skip if Set" ....bbb ..... bit (0..7) ....... fffff register file address Instruction Code List: ---------------------- (machine code word high 7 bits, in order: opcode number) 00o op 10f IORWF f,0 20f MOVF f,0 30f RRF f,0 02f MOVWF f 12f IORWF f,1 22f MOVF f,1 32f RRF f,1 040 CLRW 14f ANDWF f,0 24f COMF f,0 34f RLF f,0 06f CLRF f 16f ANDWF f,1 26f COMF f,1 36f RLF f,1 08f SUBWF f,0 18f XORWF f,0 28f INCF f,0 38f SWAPF f,0 0Af SUBWF f,1 1Af XORWF f,1 2Af INCF f,1 3Af SWAPF f,1 0Cf DECF f,0 1Cf ADDWF f,0 2Cf DECFSZ f,0 3Cf INCFSZ f,0 0Ef DECF f,1 1Ef ADDWF f,1 2Ef DECFSZ f,1 3Ef INCFSZ f,1 00o: o:op = 0:NOP 2:OPTION 3:SLEEP 4:CLRWDT 5...:TRIS 40f BCF f,0 50f BSF f,0 60f BTFSC f,0 70f BTFSS f,0 42f BCF f,1 52f BSF f,1 62f BTFSC f,1 72f BTFSS f,1 44f BCF f,2 54f BSF f,2 64f BTFSC f,2 74f BTFSS f,2 46f BCF f,3 56f BSF f,3 66f BTFSC f,3 76f BTFSS f,3 48f BCF f,4 58f BSF f,4 68f BTFSC f,4 78f BTFSS f,4 4Af BCF f,5 5Af BSF f,5 6Af BTFSC f,5 7Af BTFSS f,5 4Cf BCF f,6 5Cf BSF f,6 6Cf BTFSC f,6 7Cf BTFSS f,6 4Ef BCF f,7 5Ef BSF f,7 6Ef BTFSC f,7 7Ef BTFSS f,7 80k RETLW 0k 90k CALL 0k A0k GOTO 00k B0k GOTO 10k 82k RETLW 2k 92k CALL 2k A2k GOTO 02k B2k GOTO 12k 84k RETLW 4k 94k CALL 4k A4k GOTO 04k B4k GOTO 14k 86k RETLW 6k 96k CALL 6k A6k GOTO 06k B6k GOTO 16k 88k RETLW 8k 98k CALL 8k A8k GOTO 08k B8k GOTO 18k 8Ak RETLW Ak 9Ak CALL Ak AAk GOTO 0Ak BAk GOTO 1Ak 8Ck RETLW Ck 9Ck CALL Ck ACk GOTO 0Ck BCk GOTO 1Ck 8Ek RETLW Ek 9Ek CALL Ek AEk GOTO 0Ek BEk GOTO 1Ek C0k MOVLW 0k D0k IORLW 0k E0k ANDLW 0k F0k XORLW 0k C2k MOVLW 2k D2k IORLW 2k E2k ANDLW 2k F2k XORLW 2k C4k MOVLW 4k D4k IORLW 4k E4k ANDLW 4k F4k XORLW 4k C6k MOVLW 6k D6k IORLW 6k E6k ANDLW 6k F6k XORLW 6k C8k MOVLW 8k D8k IORLW 8k E8k ANDLW 8k F8k XORLW 8k CAk MOVLW Ak DAk IORLW Ak EAk ANDLW Ak FAk XORLW Ak CCk MOVLW Ck DCk IORLW Ck ECk ANDLW Ck FCk XORLW Ck CEk MOVLW Ek DEk IORLW Ek EEk ANDLW Ek FEk XORLW Ek Instruction Code Table: ----------------------- (only opcodes, in order: ver: bit11..8, hor: bit7..5, ignore: bit4..0) + 00x 02x 04x 06x 08x 0Ax 0Cx 0Dx 00 op MOVWF CLRW CLRF SUBWF ,0 SUBWF ,1 DECF ,0 DECF ,1 10 IORWF ,0 IORWF ,1 ANDWF ,0 ANDWF ,1 XORWF ,0 XORWF ,1 ADDWF ,0 ADDWF ,1 20 MOVF ,0 MOVF ,1 COMF ,0 COMF ,1 INCF ,0 INCF ,1 DECFSZ ,0DECFSZ ,1 30 RRF ,0 RRF ,1 RLF ,0 RLF ,1 SWAPF ,0 SWAPF ,1 INCFSZ ,0INCFSZ ,1 40 BCF ,0 BCF ,1 BCF ,2 BCF ,3 BCF ,4 BCF ,5 BCF ,6 BCF ,7 50 BSF ,0 BSF ,1 BSF ,2 BSF ,3 BSF ,4 BSF ,5 BSF ,6 BSF ,7 60 BTFSC ,0 BTFSC ,1 BTFSC ,2 BTFSC ,3 BTFSC ,4 BTFSC ,5 BTFSC ,6 BTFSC ,7 70 BTFSS ,0 BTFSS ,1 BTFSS ,2 BTFSS ,3 BTFSS ,4 BTFSS ,5 BTFSS ,6 BTFSS ,7 80 RETLW 0k RETLW 2k RETLW 4k RETLW 6k RETLW 8k RETLW Ak RETLW Ck RETLW Ek 90 CALL 0k CALL 2k CALL 4k CALL 6k CALL 8k CALL Ak CALL Ck CALL Ek A0 GOTO 00k GOTO 02k GOTO 04k GOTO 06k GOTO 08k GOTO 0Ak GOTO 0Ck GOTO 0Ek B0 GOTO 10k GOTO 12k GOTO 14k GOTO 16k GOTO 18k GOTO 1Ak GOTO 1Ck GOTO 1Ek C0 MOVLW 0k MOVLW 2k MOVLW 4k MOVLW 6k MOVLW 8k MOVLW Ak MOVLW Ck MOVLW Ek D0 IORLW 0k IORLW 2k IORLW 4k IORLW 6k IORLW 8k IORLW Ak IORLW Ck IORLW Ek E0 ANDLW 0k ANDLW 2k ANDLW 4k ANDLW 6k ANDLW 8k ANDLW Ak ANDLW Ck ANDLW Ek F0 XORLW 0k ANDLW 2k ANDLW 4k ANDLW 6k ANDLW 8k ANDLW Ak ANDLW Ck ANDLW Ek Instruction Code Tree: ---------------------- (full machine code words, in order: opcode number) 0000 0000 0000 NOP 0000 0000 0010 OPTION 0000 0000 0011 SLEEP 0000 0000 0100 CLRWDT 0000 0000 0fff TRIS f 0000 001f ffff MOVWF f 0000 0100 0000 CLRW 0000 011f ffff CLRF f 0000 10df ffff SUBWF f,d 0000 11df ffff DECF f,d 0001 00df ffff IORWF f,d 0001 01df ffff ANDWF f,d 0001 10df ffff XORWF f,d 0001 11df ffff ADDWF f,d 0010 00df ffff MOVF f,d 0010 01df ffff COMF f,d 0010 10df ffff INCF f,d 0010 11df ffff DECFSZ f,d 0011 00df ffff RRF f,d 0011 01df ffff RLF f,d 0011 10df ffff SWAPF f,d 0011 11df ffff INCFSZ f,d 0100 bbbf ffff BCF f,b 0101 bbbf ffff BSF f,b 0110 bbbf ffff BTFSC f,b 0111 bbbf ffff BTFSS f,b 1000 kkkk kkkk RETLW k 1001 kkkk kkkk CALL k 101k kkkk kkkk GOTO k 1100 kkkk kkkk MOVLW k 1101 kkkk kkkk IORLW k 1110 kkkk kkkk ANDLW k 1111 kkkk kkkk XORLW k