PIC18 (16bit "enhanced" family) Instruction Set author Neil Franklin, last modification 2008.04.30 Basics: ------- All numbers and bit patterns in this file are usually given in hex, seldom in binary, never in decimal or octal. Sources for this data: ---------------------- 1. Official Family Reference Manual PDF from Microchip Website http://ww1.microchip.com/downloads/en/DeviceDoc/39500a.pdf . Very unlikely to contain errors. Of course errors of my own are to be expected. Processor Registers: -------------------- (in order: data, address, pc, flags, auxillary) WREG 8bit Working Register (Accumulator) (SFR FE8) PRODH PRODL 8bit Multiplication Product Result 8+8bit (SFR FF4+FF3) BSR 4bit Bank Select Register (SFR FE0) FSR0 4+8bit File Select Register (Indir Addr) FSR0H+FSR0L (SFR FEA+FE9) INDF0 8bit INDirect File (Data from/to Indirect Addr) (SFR FEF..FEB) also as POSTINC0,POSTDEC0,PREINC0,PLUSW0 for addressing modes FSR1 12bit File Select Register (Indir Addr) FSR1H+FSR1L (SFR FE2+FE1) INDF1 8bit INDirect File (Data from/to Indirect Addr) (SFR FE7..FE3) also as POSTINC1,POSTDEC1,PREINC1,PLUSW1 for addressing modes FSR2 12bit File Select Register (Indir Addr) FSR2H+FSR2L (SFR FDA+FD9) INDF2 8bit INDirect File (Data from/to Indirect Addr) (SFR FDF..FDB) also as POSTINC2,POSTDEC2,PREINC2,PLUSW2 for addressing modes TOS 5+8+8bit Top Of Stack TOSU+TOSH+TOSL (SFR FFF+FFE+FFD) STKPTR 5bit Return Stack Pointer (SFR FFC) PC 20bit Program Counter (PCL 8bit SFR FF9) PCLAT 5+8bit GOTO/CALL exten PCLATU+PCLATH when writing PCL (SFR FFB+FFA) TBLPTR 5+8+8bit Table Pointer TBLPTRU+TBLPTRH+TBLPTRL (SFR FF8+FF7+FF6) TABLAT 8bit Table Latch (SFR FF5) STATUS 8bit Status Register (= flags) (SFR FD8) RCON 8bit Reset Control Register (SFR FD3..FD0) IO Device Registers: -------------------- INTCON* 8bit Interrupt Control (SFR FF2..FF0) PIE* PIR* IPR* 8bit Periphery Interrupt Enable/Flag/Priority (SFR FA2..F9D) TRIS* 8bit Tristate Register Port * (SFR F9C..F92) LAT* 8bit Port *0..7 Latch (SFR F91..F89) PORT* 8bit Port *0..7 (SFR F88..F80) many other peripherals registers Status Register, Flags: ----------------------- (in order: from MSB/7 to LSB/0) - unimplemented - unimplemented - unimplemented N Negative (result bit7 set) OV Overflow (arithmetic result carry bit6->bit7) Z Zero Flag (result all bits cleared) DC Digit Carry/Borrow Flag (arithmetic result carry bit3->bit4) C Carry/Borrow Flag (arithmetic result carry bit7->"bit8") Reset Control Register: ----------------------- (in order: from MSB/7 to LSB/0) IPEN Interrupt Priority Enable (0 = disable priority levels) LWRT Long Write Enable (0 = diable Table Writes to intern prog mem) (can only be set, clear only by /MCLR reset) 0 unimplemented /RI Reset Instruction Flag (0 = RESET instruction was executed) /TO Time-out (0 = restart after WDT timed out) /PD Power-down (0 = wakeup after SLEEP instruction executed /POR Power-on Reset (0 = start power-on has occured) (set to 1 in software to be valid) /BOR Brown-out Reset (0 = restart brown-out has occured) Memory: ------- Program memory 1024k*16bit (20bit address space) when used as table 2048k*8bit (21bit address space) Data memory access bank 128*8bit (7bit address space, 000..07F section) paged access 14*256*8bit (12bit address space, 080..F7F section) Special Function Registers (SFRs) paged 128*8bit (7bit address space, F80..FFF section) EEPROM memory (miss-)use of program memory (TBLRD and TBLWT instr) Addressing Modes, in Assembler Syntax: -------------------------------------- (in order: reg, immediate, address, reg indirect, pc) WREG working register k literal8 (= immediate8) f,a register file address and access bank f,d,a register file address and destination (WREG or f) and access bank f,b,a register file bit address and access bank fs,fd source and destination full register file address (only MOVFF instr) *FSRn FSRn indirect *FSRn++ FSRn indirect with post-increment *FSRn-- FSRn indirect with post-decrement *(--FSRn) FSRn indirect with pre-decrement *(FSRn+W) FSRn indirect with W offset * TBLPTR indirect *+ TBLPTR indirect post-increment *- TBLPTR indirect post-decrement +* TBLPTR indirect pre-decrement k absolute-address20 (only GOTO/CALL instr) Instruction Formats, in Machine Code Words: ------------------------------------------- (in order: simple, immediate, memory, bit, jump) oooo opcode16 oook opcode12+immediate4 (only MOVB instr) ookk opcode8+immediate8 ooff opcode8+address8 offfnfff opcode4+1regfile-addr12 nop-opcode4+2reg-file-addr12 (only MOVFF) oofknokk opcode10+fsr-addr2+addr-high4 nop-opcode4+op4+addr-low8 (only LFSR) obff opcode5+bitindex3+address8 (only bit instr) ookknkkk opcode8+progmem-addr-high8 nop4+progmem-addr-low12 (only GOTO/CALL) onnn opcode5+offset11 (only BRA/RCALL instr) oonn opcode8+offset8 (only Bcc instr) Instruction Bit Patterns and Operations: ---------------------------------------- (in order: functional grouping: arithmetic, data transfer, jumps, auxillary) arithmetic/logic ooooooda ffffffff ooooooo. ........ opcode operation 0000001. ........ MULWF PRODH,PRODL = W * f "MULtiply W with F" 000100.. ........ IORWF d = W bitwise-OR f; FlagsZN "Inclus OR W with F" 000101.. ........ ANDWF d = W bitwise-AND f; FlagsZN "AND W with F" 000110.. ........ XORWF d = W bitwise-excl-OR f; FlagsZN "eXclus OR W w F" 001000.. ........ ADDWFC d = W + f + FlagC; FlagsCDZON "ADD W F w Carry" 001001.. ........ ADDWF d = W + f; FlagsCDZON "ADD W and F" 010101.. ........ SUBFWB d = W - f - FlagC; FlagsCDZON "SUBtract F from W with Borrow" (= normal subtract) 010110.. ........ SUBWFB d = f - W - FlagC; FlagsCDZON "SUBtract W from F with Borrow" (= reverse of normal subtract) 010111.. ........ SUBWF d = f - W; FlagsCDZON "SUBtract W from F" (= reverse of normal subtract) ......d. ........ destination (irrelevant for MULWF, special storing) ......0. ........ store in W ......1. ........ store in file register f .......a ........ access .......0 ........ use access bank 0,00..0,7F/F,80..F,FF .......1 ........ use specified bank BSR,00..BSR,FF ........ ffffffff register file address oooooooo kkkkkkkk oooooooo ........ opcode operation 00001000 ........ SUBLW W = k - W; FlagsCDZON "SUBtract W from Lit" (= reverse of normal subtract) 00001001 ........ IORLW W = W bitwise-OR k; FlagsZN "Inclus OR Lit w W" 00001010 ........ XORLW W = W bitwise-excl-OR k; FlagsZN "eXc OR Lit w W" 00001011 ........ ANDLW W = W bitwise-AND k; FlagsZN "AND Lit with W" 00001101 ........ MULLW PRODH,PRODL = W * k "MULtiply Literal with W" 00001111 ........ ADDLW W = W + k; FlagsCDZON "ADD Literal and W" ........ kkkkkkkk literal8 (= immediate8) increment/decrement ooooooda ffffffff oooooo.. ........ opcode operation 000001.. ........ DECF d = f - 1; FlagsCDZON "DECrement F" 001010.. ........ INCF d = f + 1; FlagsCDZON "INCrement F" ......d. ........ destination ......0. ........ store in W ......1. ........ store in file register f .......a ........ access .......0 ........ use access bank 0,00..0,7F/F,80..F,FF .......1 ........ use specified bank BSR,00..BSR,FF ........ ffffffff register file address shift/rotate/swap ooooooda ffffffff oooooo.. ........ opcode operation 001100.. ........ RRCF d,FlagC = FlagC,f; FlagsCZN "Ro Right thr Carr F" 001101.. ........ RLCF FlagC,d = f,FlagC; FlagsCZN "Rot Left thr Carr F" 001110.. ........ SWAPF d = f(bit3..0,7..4) "SWAP nibbles in F" 010000.. ........ RRNCF d = f(bit0,7..1);FlagsZN "Rot Right (No Carry) F" 010001.. ........ RLNCF d = f(bit6..0,7);FlagsZN "Rot Left (No Carry) F" ......d. ........ destination ......0. ........ store in W ......1. ........ store in file register f .......a ........ access .......0 ........ use access bank 0,00..0,7F/F,80..F,FF .......1 ........ use specified bank BSR,00..BSR,FF ........ ffffffff register file address bit manipulation oooobbba ffffffff oooo.... ........ opcode operation 0111.... ........ BTG f = f bitwise-excl-OR 2^bit "Bit Toggle F" 1000.... ........ BSF f = f bitwise-OR 2^bit "Bit Set F" 1001.... ........ BCF f = f bitwise-AND NOT 2^bit "Bit Clear F" ....bbb. ........ bit (0..7) .......a ........ access .......0 ........ use access bank 0,00..0,7F/F,80..F,FF .......1 ........ use specified bank BSR,00..BSR,FF ........ ffffffff register file address other specialised arithmetic ooooooda ffffffff ooooooo. ........ opcode operation 000111.. ........ COMF d = bitwise-NOT f; FlagsZN "COMplement F" 0110100. ........ SETF f = FF "SET F" 0110101. ........ CLRF f = 0; FlagsZ (Z=1) "CLear F" 0110110. ........ NEGF f = -f; FlagsCDZON "NEGate F" ......d. ........ destination (only for COMF) ......0. ........ store in W ......1. ........ store in file register f .......a ........ access .......0 ........ use access bank 0,00..0,7F/F,80..F,FF .......1 ........ use specified bank BSR,00..BSR,FF ........ ffffffff register file address oooooooo oooooooo opcode operation 00000000 00000111 DAW if W(bit3..0) > 9 or FlagDC = 1 then W = W + 6; FlagC if W(bit7..4) > 9 or FlagC = 1 then W = W + 96; FlagC "Decimal Adjust Wreg" load/store ooooooda ffffffff ooooooo. ........ opcode operation 010100.. ........ MOVF d = f; FlagsZN "MOVe F" (= load from f) 0110111. ........ MOVWF f = W "MOVe W to F" (= store w to f) ......d. ........ destination ......0. ........ store in W (only for MOVF) ......1. ........ store in file register f .......a ........ access .......0 ........ use access bank 0,00..0,7F/F,80..F,FF .......1 ........ use specified bank BSR,00..BSR,FF ........ ffffffff register file address oooooooo kkkkkkkk oooooooo ........ opcode operation 00001100 ........ RETLW W = k; PC = TOS "RETurn with Literal in Wreg" 00001110 ........ MOVLW W = k "MOVe Literal to Wreg" ........ kkkkkkkk literal8 (= immediate8) other specialised data transfer oooooooo oooooomm oooooooo oooooo.. opcode operation 00000000 000010.. TBLRD "program memory TaBLe ReaD to tablat reg" 00000000 000011.. TBLWT "program memory TaBLe WriTe from tablat reg" ........ ......mm modify table pointer ........ ......00 * none ........ ......01 *+ post-increment ........ ......10 *- post-decrement ........ ......11 +* pre-increment oooooooo ooookkkk oooooooo oooo.... opcode operation 00000001 0000kkkk MOVLB BSR = k "MOVe Literal to BSR" ........ ....kkkk literal4 (= immediate4) ooooffff ffffffff 1111ffff ffffffff oooo.... ........ opcode operation 1100.... ........ MOVFF fd = fs "MOVe F source to F dest" ....ffff ffffffff source full 12bit file address 1111.... ........ second instruction word, NOP opcode ....ffff ffffffff destination full 12bit file address oooooooo ooffkkkk 11110000 kkkkkkkk oooooooo oo...... opcode operation 11101110 00...... LFSR FSR[ff] = k "move Literal to FSR" ........ ..ff.... FSR address 0..2 (3 reserved) ........ ....kkkk literal4 (= immediate4) (bits 11..8) 11110000 ........ second instruction word, NOP opcode ........ kkkkkkkk literal8 (= immediate8) (bits 7..0) jumps/subroutines and reset/interrupts oooooooo oooooooo opcode operation 00000000 00000000 NOP do nothing "No OPeration" 00000000 00000011 SLEEP WDT = 0; WDT.pre = 0; /TO = 1; /PD = 0 "go into standby (SLEEP) mode" 00000000 00000100 CLRWDT WDT = 0; WDT.pre = 0; /TO = 1; /PD = 1 "CLeaR WatchDog Timer" 00000000 00000101 PUSH TOS = PC "PUSH program counter onto stack" 00000000 00000110 POP delete TOS "POP (drop/discard) top of stack" 00000000 11111111 RESET same as /MCLR pin "software device RESET" 1111xxxx xxxxxxxx NOP do nothing (for 2-Word instr) "No OPeration" oooooooo ooooooos oooooooo ooooooo. opcode operation 00000000 0001000. RETFIE PC = TOS; * "RETurn from Interrupt and Enable" 00000000 0001001. RETURN PC = TOS "RETurn from subroutine" ........ .......s restore status ........ .......0 unchanged ........ .......1 WREG = WREGS; STATUS=STATUS; BSR = BSRS ooooonnn nnnnnnnn ooooo... ........ opcode operation 11010... ........ BRA PC = PC + 2 * n "BRAnch unconditional" 11011... ........ RCALL TOS = PC; PC = PC + 2 * n "Relative Call" .....nnn nnnnnnnn relative-address11 ooooooos kkkkkkkk 1111kkkk kkkkkkkk oooooooo ........ opcode operation 1110110. ........ CALL TOS = PC; PC = 2 * k "CALL subroutine" 11101111 ........ GOTO PC = 2 * k "GO TO address" .......s ........ save status (only for CALL) .......0 ........ do nothing .......1 ........ WREGS = WREG; STATUSS=STATU; BSRS = BSR ........ kkkkkkkk absolute-address8 (bits 20..13) 1111.... ........ second instruction word, NOP opcode ....kkkk kkkkkkkk absolute-address11 (bits 12..1) ---- pin /MCLR TOS = 0; STKPTR = 0; PC = 0; TBL* = 0; INTCON = 0; INTCON2 = F5; INTCON3 = C0; FSR = 0xx; BSR = 0; RCON = 1C; IPR* = 1; PI* = 0; TRIS = FF "MPU CLeaR" -- flags *IF GIE/GIEH/GIEL = 0; TOS = PC; PC = 0x8 (high prio) or 0x18 (low prio) "* Interrupt Flag" branches/conditionals ooooooda ffffffff ooooooo. ........ opcode operation 001011.. ........ DECFSZ d = f - 1; if d = 0 then PC = PC + 1 "DECrement F, Skip if Zero" 001111.. ........ INCFSZ d = f + 1; if d = 0 then PC = PC + 1 "INCrement F, SKip if Zero" 010010.. ........ INFSNZ d = f + 1; if d != 0 then PC = PC + 1 "INcrement F, Skip if Not Zero" 010011.. ........ DCFSNZ d = f - 1; if d != 0 then PC = PC + 1 "DeCrement F, Skip of Not Zero" 0110000. ........ CPFSLT if f < W then PC = PC + 1 "ComPare F with wreg, Skip Less Than" 0110001. ........ CPFSEQ if f = W then PC = PC + 1 "ComPare F with wreg, Skip Equal" 0110010. ........ CPFSGT if f > W then PC = PC + 1 "ComPare F with wreg, Skip Greater Than" 0110011. ........ TSTFSZ if f = 0 then PC = PC + 1 "TeST F, Skip if Zero" ......d. ........ destination (irrelevant for compare/test, no storing) ......0. ........ store in W ......1. ........ store in file register f .......a ........ access .......0 ........ use access bank 0,00..0,7F/F,80..F,FF .......1 ........ use specified bank BSR,00..BSR,FF ........ ffffffff register file address oooobbba ffffffff oooo.... ........ opcode operation 1010.... ........ BTFSS if (f bitwise-AND 2^bit) = 1 then PC = PC + 1 "Bit Test F, Skip if Set" 1011.... ........ BTFSC if (f bitwise-AND 2^bit) = 0 then PC = PC + 1 "Bit Test F, Skip if Clear" ....bbb. ........ bit (0..7) .......a ........ access .......0 ........ use access bank 0,00..0,7F/F,80..F,FF .......1 ........ use specified bank BSR,00..BSR,FF ........ ffffffff register file address oooooccc nnnnnnnn ooooo... ........ opcode operation 11100... ........ Bcc if condition then PC = PC + 2 * n "Branch if *" .....ccc ........ cc condition .....000 ........ Z Z = 1 "Zero" .....001 ........ NZ Z = 0 "Not Zero" .....010 ........ C C = 1 "Carry" .....011 ........ NC C = 0 "Not Carry" .....100 ........ OV OV = 1 "OVerflow" .....101 ........ NO OV = 0 "Not Overflow" .....110 ........ N N = 1 "Negative" .....111 ........ NN N = 0 "Not Negative" ........ nnnnnnnn relative-address8 Instruction Code List: ---------------------- (machine code word high bytes, in order: opcode number) 00oo op 10ff IORWF f,0,0 20ff ADDWFC f,0,0 30ff RRCF f,0,0 010k MOVLB k 11ff IORWF f,0,1 21ff ADDWFC f,0,1 31ff RRCF f,0,1 02ff MULWF f,0 12ff IORWF f,1,0 22ff ADDWFC f,1,0 32ff RRCF f,1,0 03ff MULWF f,1 13ff IORWF f,1,1 23ff ADDWFC f,1,1 33ff RRCF f,1,1 04ff DECF f,0,0 14ff ANDWF f,0,0 24ff ADDWF f,0,0 34ff RLCF f,0,0 05ff DECF f,0,1 15ff ANDWF f,0,1 25ff ADDWF f,0,1 35ff RLCF f,0,1 06ff DECF f,1,0 16ff ANDWF f,1,0 26ff ADDWF f,1,0 36ff RLCF f,1,0 07ff DECF f,1,1 17ff ANDWF f,1,1 27ff ADDWF f,1,1 37ff RLCF f,1,1 08kk SUBLW k 18ff XORWF f,0,0 28ff INCF f,0,0 38ff SWAPF f,0,0 09kk IORLW k 19ff XORWF f,0,1 29ff INCF f,0,1 39ff SWAPF f,0,1 0Akk XORLW k 1Aff XORWF f,1,0 2Aff INCF f,1,0 3Aff SWAPF f,1,0 0Bkk ANDLW k 1Bff XORWF f,1,1 2Bff INCF f,1,1 3Bff SWAPF f,1,1 0Ckk RETLW k 1Cff COMF f,0,0 2Cff DECFSZ f,0,0 3Cff INCFSZ f,0,0 0Dkk MULLW k 1Dff COMF f,0,1 2Dff DECFSZ f,0,1 3Dff INCFSZ f,0,1 0Ekk MOVLW k 1Eff COMF f,1,0 2Eff DECFSZ f,1,0 3Eff INCFSZ f,1,0 0Fkk ADDLW k 1Fff COMF f,1,1 2Fff DECFSZ f,1,1 3Fff INCFSZ f,1,1 00oo: o:op = 00:NOP 03:SLEEP 04:CLRWDT 05:PUSH 06:POP 07:DAW 08..0A:TBLRD 0C..0F:TBLWT 10|11:RETFIE 12|13:RETURN FF:RESET 40ff RRNCF f,0,0 50ff MOVF f,0,0 60ff CPFSLT f,0 70ff BTG f,0,0 41ff RRNCF f,0,1 51ff MOVF f,0,1 61ff CPFSLT f,1 71ff BTG f,0,1 42ff RRNCF f,1,0 52ff MOVF f,1,0 62ff CPFSEQ f,0 72ff BTG f,1,0 43ff RRNCF f,1,1 53ff MOVF f,1,1 63ff CPFSEQ f,1 73ff BTG f,1,1 44ff RLNCF f,0,0 54ff SUBFWB f,0,0 64ff CPFSGT f,0 74ff BTG f,2,0 45ff RLNCF f,0,1 55ff SUBFWB f,0,1 65ff CPFSGT f,1 75ff BTG f,2,1 46ff RLNCF f,1,0 56ff SUBFWB f,1,0 66ff TSTFSZ f,0 76ff BTG f,3,0 47ff RLNCF f,1,1 57ff SUBFWB f,1,1 67ff TSTFSZ f,1 77ff BTG f,3,1 48ff INFSNZ f,0,0 58ff SUBWFB f,0,0 68ff SETF f,0 78ff BTG f,4,0 49ff INFSNZ f,0,1 59ff SUBWFB f,0,1 69ff SETF f,1 79ff BTG f,4,1 4Aff INFSNZ f,1,0 5Aff SUBWFB f,1,0 6Aff CLRF f,0 7Aff BTG f,5,0 4Bff INFSNZ f,1,1 5Bff SUBWFB f,1,1 6Bff CLRF f,1 7Bff BTG f,5,1 4Cff DCFSNZ f,0,0 5Cff SUBWF f,0,0 6Cff NEGF f,0 7Cff BTG f,6,0 4Dff DCFSNZ f,0,1 5Dff SUBWF f,0,1 6Dff NEGF f,1 7Dff BTG f,6,1 4Eff DCFSNZ f,1,0 5Eff SUBWF f,1,0 6Eff MOVWF f,0 7Eff BTG f,7,0 4Fff DCFSNZ f,1,1 5Fff SUBWF f,1,1 6Fff MOVWF f,1 7Fff BTG f,7,1 80ff BSF f,0,0 90ff BCF f,0,0 A0ff BTFSS f,0,0 B0ff BTFSC f,0,0 81ff BSF f,0,1 91ff BCF f,0,1 A1ff BTFSS f,0,1 B1ff BTFSC f,0,1 82ff BSF f,1,0 92ff BCF f,1,0 A2ff BTFSS f,1,0 B2ff BTFSC f,1,0 83ff BSF f,1,1 93ff BCF f,1,1 A3ff BTFSS f,1,1 B3ff BTFSC f,1,1 84ff BSF f,2,0 94ff BCF f,2,0 A4ff BTFSS f,2,0 B4ff BTFSC f,2,0 85ff BSF f,2,1 95ff BCF f,2,1 A5ff BTFSS f,2,1 B5ff BTFSC f,2,1 86ff BSF f,3,0 96ff BCF f,3,0 A6ff BTFSS f,3,0 B6ff BTFSC f,3,0 87ff BSF f,3,1 97ff BCF f,3,1 A7ff BTFSS f,3,1 B7ff BTFSC f,3,1 88ff BSF f,4,0 98ff BCF f,4,0 A8ff BTFSS f,4,0 B8ff BTFSC f,4,0 89ff BSF f,4,1 99ff BCF f,4,1 A9ff BTFSS f,4,1 B9ff BTFSC f,4,1 8Aff BSF f,5,0 9Aff BCF f,5,0 AAff BTFSS f,5,0 BAff BTFSC f,5,0 8Bff BSF f,5,1 9Bff BCF f,5,1 ABff BTFSS f,5,1 BBff BTFSC f,5,1 8Cff BSF f,6,0 9Cff BCF f,6,0 ACff BTFSS f,6,0 BCff BTFSC f,6,0 8Dff BSF f,6,1 9Dff BCF f,6,1 ADff BTFSS f,6,1 BDff BTFSC f,6,1 8Eff BSF f,7,0 9Eff BCF f,7,0 AEff BTFSS f,7,0 BEff BTFSC f,7,0 8Fff BSF f,7,1 91Ff BCF f,7,1 AFff BTFSS f,7,1 BFff BTFSC f,7,1 C0ffF* MOVFF 0fs,fd D0nn BRA 0nn E0nn BZ nn F0xx NOP 0xx C1ffF* MOVFF 1fs,fd D1nn BRA 1nn E1nn BNZ nn F1xx NOP 1xx C2ffF* MOVFF 2fs,fd D2nn BRA 2nn E2nn BC nn F2xx NOP 2xx C3ffF* MOVFF 3fs,fd D3nn BRA 3nn E3nn BNC nn F3xx NOP 3xx C4ffF* MOVFF 4fs,fd D4nn BRA 4nn E4nn BOV nn F4xx NOP 4xx C5ffF* MOVFF 5fs,fd D5nn BRA 5nn E5nn BNO nn F5xx NOP 5xx C6ffF* MOVFF 6fs,fd D6nn BRA 6nn E6nn BN nn F6xx NOP 6xx C7ffF* MOVFF 7fs,fd D7nn BRA 7nn E7nn BNN nn F7xx NOP 7xx C8ffF* MOVFF 8fs,fd D8nn RCALL 0nn ---- - F8xx NOP 8xx C9ffF* MOVFF 9fs,fd D9nn RCALL 1nn ---- - F9xx NOP 9xx CAffF* MOVFF Afs,fd DAnn RCALL 2nn ---- - FAxx NOP Axx CBffF* MOVFF Bfs,fd DBnn RCALL 3nn ---- - FBxx NOP Bxx CCffF* MOVFF Cfs,fd DCnn RCALL 4nn ECkkF* CALL k,0 FCxx NOP Cxx CDffF* MOVFF Dfs,fd DDnn RCALL 5nn EDkkF* CALL k,1 FDxx NOP Dxx CEffF* MOVFF Efs,fd DEnn RCALL 6nn EEfkF* LFSR f,k FExx NOP Exx CFffF* MOVFF Ffs,fd DFnn RCALL 7nn EFkkF* GOTO k FFxx NOP Fxx C0..CF: F* = Ffff for ,fd EC|ED|EF: F* = Fkkk for together with E*kk 20bit progmem addr EE: F* = F0kk for together with EEfk 12bit constant Instruction Code Table: ----------------------- (only opcodes, in order: ver: bit15..14/13..11, hor: bit10..8, ignore: bit7..0) + 00xx 01xx 02xx 03xx 04xx 05xx 06xx 07xx 00 op MOVLB k MULWF ,0 MULWF ,1 DECF ,00 DECF ,01 DECF ,10 DECF ,11 08 SUBLW IORLW XORLW ANDLW RETLW MULLW MOVLW ADDLW 10 IORWF 00 IORWF 01 IORWF 10 IORWF 11 ANDWF 00 ANDWF 01 ANDWF 10 ANDWF 11 18 XORWF 00 XORWF 01 XORWF 10 XORWF 11 COMF ,00 COMF ,01 COMF ,10 COMF ,11 20 ADDWFC00 ADDWFC01 ADDWFC10 ADDWFC11 ADDWF 00 ADDWF 01 ADDWF 10 ADDWF 11 28 INCF ,00 INCF ,01 INCF ,10 INCF ,11 DECFSZ00 DECFSZ01 DECFSZ10 DECFSZ11 30 RRCF ,00 RRCF ,01 RRCF ,10 RRCF ,11 RLCF ,00 RLCF ,01 RLCF ,10 RLCF ,11 38 SWAPF 00 SWAPF 01 SWAPF 10 SWAPF 11 INCFSZ00 INCFSZ01 INCFSZ10 INCFSZ11 40 RRNCF 00 RRNCF 01 RRNCF 10 RRNCF 11 RLNCF 00 RLNCF 01 RLNCF 10 RLNCF 11 48 INFSNZ00 INFSNZ01 INFSNZ10 INFSNZ11 DCFSNZ00 DCFSNZ01 DCFSNZ10 DCFSNZ11 50 MOVF ,00 MOVF ,01 MOVF ,10 MOVF ,11 SUBFWB00 SUBFWB01 SUBFWB10 SUBFWB11 58 SUBWFB00 SUBWFB01 SUBWFB10 SUBWFB11 SUBWF 00 SUBWF 01 SUBWF 10 SUBWF 11 60 CPFSLT 0 CPFSLT 1 CPFSEQ 0 CPFSEQ 1 CPFSGT 0 CPFSGT 1 TSTFSZ 0 TSTFSZ 1 68 SETF ,0 SETF ,1 CLRF ,0 CLRF ,1 NEGF ,0 NEGF ,1 MOVWF ,0 MOVWF ,1 70 BTG ,0,0 BTG ,0,1 BTG ,1,0 BTG ,1,1 BTG ,2,0 BTG ,2,1 BTG ,3,0 BTG ,3,1 78 BTG ,4,0 BTG ,4,1 BTG ,5,0 BTG ,5,1 BTG ,6,0 BTG ,6,1 BTG ,7,0 BTG ,7,1 80 BSF ,0,0 BSF ,0,1 BSF ,1,0 BSF ,1,1 BSF ,2,0 BSF ,2,1 BSF ,3,0 BSF ,3,1 88 BSF ,4,0 BSF ,4,1 BSF ,5,0 BSF ,5,1 BSF ,6,0 BSF ,6,1 BSF ,7,0 BSF ,7,1 90 BCF ,0,0 BCF ,0,1 BCF ,1,0 BCF ,1,1 BCF ,2,0 BCF ,2,1 BCF ,3,0 BCF ,3,1 98 BCF ,4,0 BCF ,4,1 BCF ,5,0 BCF ,5,1 BCF ,6,0 BCF ,6,1 BCF ,7,0 BCF ,7,1 A0 BTFSS 00 BTFSS 01 BTFSS 10 BTFSS 11 BTFSS 20 BTFSS 21 BTFSS 30 BTFSS 31 A8 BTFSS 40 BTFSS 41 BTFSS 50 BTFSS 51 BTFSS 60 BTFSS 61 BTFSS 70 BTFSS 71 B0 BTFSC 00 BTFSC 01 BTFSC 10 BTFSC 11 BTFSC 20 BTFSC 21 BTFSC 30 BTFSC 31 B8 BTFSC 40 BTFSC 41 BTFSC 50 BTFSC 51 BTFSC 60 BTFSC 61 BTFSC 70 BTFSC 71 C0 MOVFF 0* MOVFF 1* MOVFF 2* MOVFF 3* MOVFF 4* MOVFF 5* MOVFF 6* MOVFF 7* C8 MOVFF 8* MOVFF 9* MOVFF A* MOVFF B* MOVFF C* MOVFF D* MOVFF E* MOVFF F* D0 BRA 0nn BRA 1nn BRA 2nn BRA 3nn BRA 4nn BRA 5nn BRA 6nn BRA 7nn D8 RCALL 0* RCALL 1* RCALL 2* RCALL 3* RCALL 4* RCALL 5* RCALL 6* RCALL 7* E0 BZ BNZ BC BNC BOV BNO BN BNN E8 - - - - CALL ,0 CALL ,1 LFSR GOTO F0 NOP 0xx NOP 1xx NOP 2xx NOP 3xx NOP 4xx NOP 5xx NOP 6xx NOP 7xx F8 NOP 8xx NOP 9xx NOP Axx NOP Bxx NOP Cxx NOP Dxx NOP Exx NOP Fxx Instruction Code Tree: ---------------------- (full machine code words, in order: opcode number) 0000 0000 0000 0000 NOP 0000 0000 0000 0011 SLEEP 0000 0000 0000 0100 CLRWDT 0000 0000 0000 0101 PUSH 0000 0000 0000 0110 POP 0000 0000 0000 0111 DAW 0000 0000 0000 10mm TBLRD m 0000 0000 0000 11mm TBLWT m 0000 0000 0001 000s RETFIE s 0000 0000 0001 001s RETURN s 0000 0000 1111 1111 RESET 0000 0001 0000 kkkk MOVLB k 0000 001a ffff ffff MULWF f,a 0000 01da ffff ffff DECF f,d,a 0000 1000 kkkk kkkk SUBLW k 0000 1001 kkkk kkkk IORLW k 0000 1010 kkkk kkkk XORLW k 0000 1011 kkkk kkkk ANDLW k 0000 1100 kkkk kkkk RETLW k 0000 1101 kkkk kkkk MULLW k 0000 1110 kkkk kkkk MOVLW k 0000 1111 kkkk kkkk ADDLW k 0001 00da ffff ffff IORWF f,d,a 0001 01da ffff ffff ANDWF f,d,a 0001 10da ffff ffff XORWF f,d,a 0001 11da ffff ffff COMF f,d,a 0010 00da ffff ffff ADDWFC f,d,a 0010 01da ffff ffff ADDWF f,d,a 0010 10da ffff ffff INCF f,d,a 0010 11da ffff ffff DECFSZ f,d,a 0011 00da ffff ffff RRCF f,d,a 0011 01da ffff ffff RLCF f,d,a 0011 10da ffff ffff SWAPF f,d,a 0011 11da ffff ffff INCFSZ f,d,a 0100 00da ffff ffff RRNCF f,d,a 0100 01da ffff ffff RLNCF f,d,a 0100 10da ffff ffff INFSNZ f,d,a 0100 11da ffff ffff DCFSNZ f,d,a 0101 00da ffff ffff MOVF f,d,a 0101 01da ffff ffff SUBFWB f,d,a 0101 10da ffff ffff SUBWFB f,d,a 0101 11da ffff ffff SUBWF f,d,a 0110 000a ffff ffff CPFSLT f,a 0110 001a ffff ffff CPFSEQ f,a 0110 010a ffff ffff CPFSGT f,a 0110 011a ffff ffff TSTFSZ f,a 0110 100a ffff ffff SETF f,a 0110 101a ffff ffff CLRF f,a 0110 110a ffff ffff NEGF f,a 0110 111a ffff ffff MOVWF f,a 0111 bbba ffff ffff BTG f,b,a 1000 bbba ffff ffff BSF f,b,a 1001 bbba ffff ffff BCF f,b,a 1010 bbba ffff ffff BTFSS f,b,a 1011 bbba ffff ffff BTFSC f,b,a 1100 ffff ffff ffff 1111 ffff ffff ffff MOVFF fs,fd 1101 0nnn nnnn nnnn BRA n 1101 1nnn nnnn nnnn RCALL n 1110 0000 nnnn nnnn BZ n 1110 0001 nnnn nnnn BNZ n 1110 0010 nnnn nnnn BC n 1110 0011 nnnn nnnn BNC n 1110 0100 nnnn nnnn BOV n 1110 0101 nnnn nnnn BNO n 1110 0110 nnnn nnnn BN n 1110 0111 nnnn nnnn BNN nw 1110 110s kkkk kkkk 1111 kkkk kkkk kkkk CALL k,s 1110 1110 00ff kkkk 1111 0000 kkkk kkkk LFSR f,k 1110 1111 kkkk kkkk 1111 kkkk kkkk kkkk GOTO k 1111 xxxx xxxx xxxx NOP