PIC16F8x (14bit "mid-range" family) Instruction Set author Neil Franklin, last modification 2008.04.30 Basics: ------- All numbers and bit patterns in this file are usually given in hex, seldom in binary, never in decimal or octal. Sources for this data: ---------------------- 1. Official Datasheet PDF from Microchip Website http://ww1.microchip.com/downloads/en/DeviceDoc/30430c.pdf . Very unlikely to contain errors. Of course errors of my own are to be expected. Processor Registers: -------------------- (in order: data, address, pc, flags, auxillary) W 8bit Working Register (Accumulator) (standalone) FSR [78]bit File Select Register (Indirect Address) (SFR 04/84) INDF 8bit INDirect File (Data from/to Indirect Addr) (SFR 00/80) PC 13bit Program Counter (PCL 8bit SFR 02/82) PCLATH 5bit GOTO/CALL extension 11->13bit, PCL ext 8->13bit (SFR 0A/8A) STATUS 8bit Status Register (= flags + register bank select) (SFR 03/83) EEDATA 8bit EEPROM Data (SFR 08) EEADR 6bit EEPROM Address (SFR 09) EECON1 5bit EEPROM Control 1 (SFR 88) EECON2 8bit EEPROM Control 2 (SFR 89) IO Device Registers: -------------------- INTCON 8bit Interrupt Control (SFR 0B/8B) TMR0 8bit Timer 0 (SFR 01) OPTION 8bit Timer 0 and Prescaler Setup (SFR 81) PORTA 8bit Port A0..7 (SFR 05) TRISA 8bit Tristate Register Port A (SFR 85) PORTB 8bit Port B0..7 (SFR 06) TRISB 8bit Tristate Register Port B (SFR 86) Status Register, Flags: ----------------------- (in order: from MSB/7 to LSB/0) IRP Indirect Register Bank (FSR8 extension of FSR7..0 register) RP1 Register Bank Select 1 (AD8 for direct access) RP0 " 0 (AD7 for direct access) /TO Time-out (0 = restart after WDT timed out) /PD Power-down (0 = wakeup after SLEEP instruction executed Z Zero (result all bits cleared) DC Digit Carry/Borrow (arithmetic result carry bit3->bit4) C Carry/Borrow (arithmetic result carry bit7->"bit8") Interrupt Control Register: --------------------------- (in order: from MSB/7 to LSB/0) GIE Global Interrupt Enable (1 = enabled) EEIE EE Write Complete I E (1 = enabled) T0IE TMR0 Overflow I Enable (1 = enabled) INTE RB0/INT Interrupt Enable (1 = enabled) RBIE RB Port Change I Enable (1 = enabled) T0IF TMR0 Overflow I Flag (1 = timer has overflowed) INTF RB0/INT Interrupt Flag (1 = RB0/INT pin was triggered) RBIF RB Port Change I Flag (1 = one of RB7..4 pins has changed) Memory: ------- Program memory 2k*14bit or paged 8k*14bit (11bit or 13bit address space) Data memory 16*8bit (7bit address space, 70..7F section) paged [14]*80*8bit (7bit address space, 20..6F section) Special Function Registers (SFRs) paged [24]*32*8bit (5bit address space, 00..2F section) EEPROM memory 64*8bit (6bit address space, EEADR, data to/from EEDATA) Addressing Modes, in Assembler Syntax: -------------------------------------- (in order: reg, immediate, address, reg indirect, pc) W working register k literal8 (= immediate8) f register file address f,d register file address and destination (W or f) f,b register file bit address INDF FSR indirect (INDF is label for address 0) k absolute-address11 (only GOTO/CALL instr) Instruction Formats, in Machine Code Words: ------------------------------------------- (in order: simple, immediate, memory, bit, jump) oooo opcode14 ookk opcode6+immediate8 ooff opcode7+address7 obff opcode4+bitindex3+address7 okkk opcode3+progmem-address11 (only CALL/GOTO instr) Instruction Bit Patterns and Operations: ---------------------------------------- (in order: functional grouping: arithmetic, data transfer, jumps, auxillary) arithmetic/logic ooooood fffffff oooooo. ....... opcode operation 000010. ....... SUBWF d = f - W; FlagsCDZ "SUBtract W from F" (= reverse of normal subtract) 000100. ....... IORWF d = W bitwise-OR f; FlagsZ "Inclusive OR W with F" 000101. ....... ANDWF d = W bitwise-AND f; FlagsZ "AND W with F" 000110. ....... XORWF d = W bitwise-excl-OR f; FlagsZ "eXclu OR W with F" 000111. ....... ADDWF d = W + f; FlagsCDZ "ADD W and F" ......d ....... destination ......0 ....... store in W ......1 ....... store in file register f ....... fffffff register file address ooooook kkkkkkk oooooo. ....... opcode operation 111000. ....... IORLW W = W bitwise-OR k; FlagsZ "Inclus OR Lit with W" 111001. ....... ANDLW W = W bitwise-AND k; FlagsZ "AND Literal with W" 111010. ....... XORLW W = W bitwise-excl-OR k; FlagsZ "eXclu OR L with W" 11110x. ....... SUBLW W = k - W; FlagsCDZ "SUBtract W from Literal" (= also reverse of normal) 11111x. ....... ADDLW W = W + k; FlagsCDZ "ADD Literal and W" ......k kkkkkkk literal8 (= immediate8) increment/decrement ooooood fffffff oooooo. ....... opcode operation 000011. ....... DECF d = f - 1; FlagsZ "DECrement F" 001010. ....... INCF d = f + 1; FlagsZ "INCrement F" ......d ....... destination ......0 ....... store in W ......1 ....... store in file register f ....... fffffff register file address shift/rotate/swap ooooood fffffff oooooo. ....... opcode operation 001100. ....... RRF d,FlagC = FlagC,f; FlagsC "Ro Right F throu carr F" 001101. ....... RLF FlagC,d = f,FlagC; FlagsC "Rot Left F throu carr F" 001110. ....... SWAPF d = f(bit3..0,7..4) "SWAP nibbles in F" ......d ....... destination ......0 ....... store in W ......1 ....... store in file register f ....... fffffff register file address bit manipulation oooobbb fffffff oooo... ....... opcode operation 0100... ....... BCF f = f bitwise-AND NOT 2^bit "Bit Clear F" 0101... ....... BSF f = f bitwise-OR 2^bit "Bit Set F" ....bbb ....... bit (0..7) ....... fffffff register file address other specialised arithmetic ooooood fffffff ooooooo ....... opcode operation 0000010 ....... CLRW W = 0; FlagsZ (Z=1) "CLeaR W" 0000011 ....... CLRF f = 0; FlagsZ (Z=1) "CLeaR F" 001001. ....... COMF d = bitwise-NOT f; FlagsZ "COMplement F" ......d ....... destination ......0 ....... store in W ......1 ....... store in file register f ....... fffffff register file address (is xxx xxxx (don't care) for CLRW) load/store ooooood fffffff ooooooo ....... opcode operation 0000001 ....... MOVWF f = W "MOVe W to F" (= store w to f) 001000. ....... MOVF d = f; FlagsZ "MOVe F" (= load from f) ......d ....... destination ......0 ....... store in W (only for MOVF) ......1 ....... store in file register f ....... fffffff register file address ooooook kkkkkkk oooooo. ....... opcode operation 1100xxk kkkkkkk MOVLW W = k "MOVe Literal to W" 1101xxk kkkkkkk RETLW W = k; PC = TOS "RETurn with Literal in W" ......k kkkkkkk literal8 (= immediate8) other specialised data transfer ooooooo ooooooo opcode operation 0000000 1100010 OPTION (do not use, only for 16F5x compat, use MOVWF) 0000000 1100fff TRIS (do not use, only for 16F5x compat, use MOVWF) jumps/subroutines and reset/interrupts ooooooo ooooooo opcode operation 0000000 xx00000 NOP do nothing "No OPeration" 0000000 0001000 RETURN PC = TOS "RETURN from subroutine" 0000000 0001001 RETFIE PC = TOS; GIE = 1 "RETurn From Interrupt and Enable" 0000000 1100011 SLEEP WDT = 0; WDT.pre = 0; /TO = 1; /PD = 0 "go into standby (SLEEP) mode" 0000000 1100100 CLRWDT WDT = 0; WDT.pre = 0; /TO = 1; /PD = 1 "CLeaR WatchDog Timer" oookkkk kkkkkkk ooo.... ....... opcode operation 100.... ....... CALL TOS = PC + 1; PC = PCLATH,k "CALL subroutine" 101.... ....... GOTO PC = PCLATH,k "GO TO address" ...kkkk kkkkkkk absolute-address11 --- pin /MCLR PCL = 0; STATUS = 1F; PCLATH = 0; INTCON = 0; OPTION = FF; TRIS* = FF; EE* = 0 "MPU CLeaR" - flags T0IF OR INTF OR RBIF OR EEIF GIE = 0; TOS = PC; PC = 4 "* Interrupt Flag" branches/conditionals ooooood fffffff ooooooo ....... opcode operation 001011d fffffff DECFSZ d = f - 1; if d = 0 then PC = PC + 1 "DECrement F, Skip if Zero" 001111d fffffff INCFSZ d = f + 1; if d = 0 then PC = PC + 1 "INCrement F, Skip if Zero" ......d ....... destination ......0 ....... store in W ......1 ....... store in file register f ....... fffffff register file address oooobbb fffffff oooo... ....... opcode operation 0110bbb fffffff BTFSC if (f bitwise-AND 2^bit) = 0 then PC = PC + 1 "Bit Test F, Skip if Clear" 0111bbb fffffff BTFSS if (f bitwise-AND 2^bit) = 1 then PC = PC + 1 "Bit Test F, Skip if Set" ....bbb ....... bit (0..7) ....... fffffff register file address Instruction Code List: ---------------------- (machine code word high 7 bits, in order: opcode number) 000o op 040f IORWF f,0 080f MOVF f,0 0C0f RRF f,0 008f MOVWF f 048f IORWF f,1 088f MOVF f,1 0C8f RRF f,1 010x CLRW 050f ANDWF f,0 090f COMF f,0 0D0f RLF f,0 018f CLRF f 058f ANDWF f,1 098f COMF f,1 0D8f RLF f,1 020f SUBWF f,0 060f XORWF f,0 0A0f INCF f,0 0E0f SWAPF f,0 028f SUBWF f,1 068f XORWF f,1 0A8f INCF f,1 0E8f SWAPF f,1 030f DECF f,0 070f ADDWF f,0 0B0f DECFSZ f,0 0F0f INCFSZ f,0 038f DECF f,1 078f ADDWF f,1 0B8f DECFSZ f,1 0F8f INCFSZ f,1 000o: o:op = 00:NOP 08:RETURN 09:RETFIE 62:OPTION 63:SLEEP 64:CLRWDT 65...:TRIS 100f BCF f,0 140f BSF f,0 180f BTFSC f,0 1C0f BTFSS f,0 108f BCF f,1 148f BSF f,1 188f BTFSC f,1 1C8f BTFSS f,1 110f BCF f,2 150f BSF f,2 190f BTFSC f,2 1D0f BTFSS f,2 118f BCF f,3 158f BSF f,3 198f BTFSC f,3 1D8f BTFSS f,3 120f BCF f,4 160f BSF f,4 1A0f BTFSC f,4 1E0f BTFSS f,4 128f BCF f,5 168f BSF f,5 1A8f BTFSC f,5 1E8f BTFSS f,5 130f BCF f,6 170f BSF f,6 1B0f BTFSC f,6 1F0f BTFSS f,6 138f BCF f,7 178f BSF f,7 1B8f BTFSC f,7 1F8f BTFSS f,7 200k CALL 00k 240k CALL 40k 280k GOTO 00k 2C0k GOTO 40k 208k CALL 08k 248k CALL 48k 288k GOTO 08k 2C8k GOTO 48k 210k CALL 10k 250k CALL 50k 290k GOTO 10k 2D0k GOTO 50k 218k CALL 18k 258k CALL 58k 298k GOTO 18k 2D8k GOTO 58k 220k CALL 20k 260k CALL 60k 2A0k GOTO 20k 2E0k GOTO 60k 228k CALL 28k 268k CALL 68k 2A8k GOTO 28k 2E8k GOTO 68k 230k CALL 30k 270k CALL 70k 2B0k GOTO 30k 2F0k GOTO 70k 238k CALL 38k 278k CALL 78k 2B8k GOTO 38k 2F8k GOTO 78k 300k MOVLW 0k 340k RETLW 0k 380k IORLW 0k 3C0k SUBLW 0k 308k MOVLW 8k 348k RETLW 8k 388k IORLW 8k 3C8k SUBLW 8k 310k MOVLW 0k 350k RETLW 0k 390k ANDLW 0k 3D0k SUBLW 0k 318k MOVLW 8k 358k RETLW 8k 398k ANDLW 8k 3D8k SUBLW 8k 320k MOVLW 0k 360k RETLW 0k 3A0k XORLW 0k 3E0k ADDLW 0k 328k MOVLW 8k 368k RETLW 8k 3A8k XORLW 8k 3E8k ADDLW 8k 330k MOVLW 0k 370k RETLW 0k ---- - 3F0k ADDLW 0k 338k MOVLW 8k 378k RETLW 8k ---- - 3F8k ADDLW 8k Instruction Code Table: ----------------------- (only opcodes, in order: ver: bit13..10, hor: bit9..7, ignore: bit6..0) + 000x 008x 010x 018x 020x 028x 030x 038x 00 op MOVWF CLRW CLRF SUBWF ,0 SUBWF ,1 DECF ,0 DECF ,1 04 IORWF ,0 IORWF ,1 ANDWF ,0 ANDWF ,1 XORWF ,0 XORWF ,1 ADDWF ,0 ADDWF ,1 08 MOVF ,0 MOVF ,1 COMF ,0 COMF ,1 INCF ,0 INCF ,1 DECFSZ ,0DECFSZ ,1 0C RRF ,0 RRF ,1 RLF ,0 RLF ,1 SWAPF ,0 SWAPF ,1 INCFSZ ,0INCFSZ ,1 10 BCF ,0 BCF ,1 BCF ,2 BCF ,3 BCF ,4 BCF ,5 BCF ,6 BCF ,7 14 BSF ,0 BSF ,1 BSF ,2 BSF ,3 BSF ,4 BSF ,5 BSF ,6 BSF ,7 18 BTFSC ,0 BTFSC ,1 BTFSC ,2 BTFSC ,3 BTFSC ,4 BTFSC ,5 BTFSC ,6 BTFSC ,7 1C BTFSS ,0 BTFSS ,1 BTFSS ,2 BTFSS ,3 BTFSS ,4 BTFSS ,5 BTFSS ,6 BTFSS ,7 20 CALL 00k CALL 08k CALL 10k CALL 18k CALL 20k CALL 28k CALL 30k CALL 38k 24 CALL 40k CALL 48k CALL 50k CALL 58k CALL 60k CALL 68k CALL 70k CALL 78k 28 GOTO 00k GOTO 08k GOTO 10k GOTO 18k GOTO 20k GOTO 28k GOTO 30k GOTO 38k 2C GOTO 40k GOTO 48k GOTO 50k GOTO 58k GOTO 60k GOTO 68k GOTO 70k GOTO 78k 30 MOVLW 0k MOVLW 8k MOVLW 0k MOVLW 8k MOVLW 0k MOVLW 8k MOVLW 0k MOVLW 8k 34 RETLW 0k RETLW 8k RETLW 0k RETLW 8k RETLW 0k RETLW 8k RETLW 0k RETLW 8k 38 IORLW 0k IORLW 8k ANDLW 0k ANDLW 8k XORLW 0k XORLW 8k - - 3C SUBLW 0k SUBLW 8k SUBLW 0k SUBLW 8k ADDLW 0k ADDLW 8k ADDLW 0k ADDLW 08k Instruction Code Tree: ---------------------- (full machine code words, in order: opcode number) 00 0000 0xx0 0000 NOP 00 0000 0000 1000 RETURN 00 0000 0000 1001 RETFIE 00 0000 0110 0010 OPTION (do not use, only for 16F5x compat, use MOVWF) 00 0000 0110 0011 SLEEP 00 0000 0110 0100 CLRWDT 00 0000 0110 0fff TRIS (do not use, only for 16F5x compat, use MOVWF) 00 0000 1fff ffff MOVWF f 00 0001 0xxx xxxx CLRW 00 0001 1fff ffff CLRF f 00 0010 dfff ffff SUBWF f,d 00 0011 dfff ffff DECF f,d 00 0100 dfff ffff IORWF f,d 00 0101 dfff ffff ANDWF f,d 00 0110 dfff ffff XORWF f,d 00 0111 dfff ffff ADDWF f,d 00 1000 dfff ffff MOVF f,d 00 1001 dfff ffff COMF f,d 00 1010 dfff ffff INCF f,d 00 1011 dfff ffff DECFSZ f,d 00 1100 dfff ffff RRF f,d 00 1101 dfff ffff RLF f,d 00 1110 dfff ffff SWAPF f,d 00 1111 dfff ffff INCFSZ f,d 01 00bb bfff ffff BCF f,b 01 01bb bfff ffff BSF f,b 01 10bb bfff ffff BTFSC f,b 01 11bb bfff ffff BTFSS f,b 10 0kkk kkkk kkkk CALL k 10 1kkk kkkk kkkk GOTO K 11 00xx kkkk kkkk MOVLW k 11 01xx kkkk kkkk RETLW k 11 1000 kkkk kkkk IORLW k 11 1001 kkkk kkkk ANDLW k 11 1010 kkkk kkkk XORLW k 11 110x kkkk kkkk SUBLW k 11 111x kkkk kkkk ADDLW k