AVR Instruction Set author Neil Franklin, last modification 2009.03.08 Basics: ------- All numbers and bit patterns in this file are usually given in hex, seldom in binary, never in decimal or octal. Sources for this data: ---------------------- 1. Official Instruction Set PDF from Atmel Website, at http://www.atmel.com/dyn/resources/prod_documents/DOC0856.PDF . Very unlikely to contain errors. 2. For example chip specific details ATmega48 PDF from Atmel Website, at http://www.atmel.com/dyn/resources/prod_documents/doc2545.pdf . Very unlikely to contain errors. Of course errors of my own are to be expected. Processor Registers: -------------------- (in order: data, address, pc, flags) R0 R1 .. R31 8bit General Purpose Registers (at 0x0000..001F of data memory) R1:R0 .. R31:R30 16bit Register Pairs RAMPD 8bit direct address extension for >64k*8bit LDS/STS (n.i.) RAMPX RAMPY 8bit indirect X and Y extension for >64k*8bit LD/ST (n.i.) RAMPZ 8bit indirect Z exten for >64k*8bit LD/ST/EPLM/SPM (IO 0x3B) SPH SPL 8+8bit Stack Pointer (IO 0x3E and 0x3D) (push post-decrement(!), pop pre-increment(!)) PC 22bit Program Counter EIND 8bit Z extension for >64k*16bit EIJMP/EICALL (IO 0x3C) SREG 8bit Status Register (= flags) (IO 0x3F) SMCR 4bit Sleep Mode Control Register (IO 0x33) PRR 8bit Power Reduction Register (IO 0x64) MCUSR 4bit MCU Status Register (reset source) (IO 0x35) MCUCR 3bit MCU Control Register (port pullup, int vector) (IO 0x36) EEARH EEARL 8+8bit EEPROM Address Register (IO 0x22 and 0x21) EEDR 8bit EEPROM Data Register (IO 0x20) EECR 6bit EEPROM Control Register (IO 0x1F) IO Device Registers: -------------------- WDTCSR 8bit Watchdog Timer Control Register (DataIO 0x60) *ICR* nbit * Interrupt Control Register * (IO 0x*) *IMSK* nbit * Interrupt MaSK Register * (IO 0x*) *IFR* nbit * Interrupt Flag Register * (IO 0x*) PORT* 8bit Port * Data Register (IO 0x*) DDR* 8bit Port * Data Direction Register (IO 0x*) PIN* 8bit Port * Input Pins Address (IO 0x*) many other peripherals registers Status Register, Flags: ----------------------- (in order: from MSB/7 to LSB/0) I Interrupt Enable Flag (1 enables interrupts) T Transfer Bit (for BLD and BST instructions) H Half Carry Flag (arithmetic result carry bit3->bit4) S Signed Flag (N Excl-OR V, for signed tests) V oVerflow Flag (result carry bit6->bit7) N Negative Flag (result bit7 set) Z Zero Flag (result all bits cleared) C Carry Flag (arithmetic result carry bit7->"bit8") MCU Status Register: ------------------- (in order: from MSB/3 to LSB/0) WDRF Watchdog System Reset Flag (1 = occured) BORF Brown-out Reset Flag (1 = occured) EXTRF External Reset Flag (1 = occured) PORF Power-on Reset Flag (1 = occured, user must write 0) Memory: ------- Program memory 64k*16bit or 4M*16bit (16bit or 22bit instr16 address space) 32k*2*8bit or 4M*2*8bit (15+1bit or 22+1bit const8 address space) Data memory 64k*8bit (16bit address space) 32*8bit (00..1F) of these are registers 32*8bit (20..3F) of these are bit addressable IO 64*8bit (20..5F) of these are short addressable IO EEPROM memory 64k*8bit (16bit address space, EEAR*, data to/from EEDR) Addressing Modes, in Assembler Syntax: -------------------------------------- (in order: reg, immediate, address, reg indirect, reg indexed, pc) R0 R1 .. R31 register (5 bits, immed + main multiply only 4 bits R16 .. R31, some multiply instr only 3 bits R16 .. R32) R1:R0 .. R31:R30 reg pairs (4 bits, ADIW/SBIW only 2 bits R25:R24 .. R31:R30) b register bit address (3 bits) s status register bit address (3 bits) K immediate6 (only ADIW/SBIW instr) K immediate8 A short-direct-address5 (only for bit adressed input/output) A short-direct-address6 (only for byte addressed input/output) k direct-address16 (only for data memory) X Y Z indirect address (only for data memory) (using reg pairs X = R27,R26 and Y = R29,R28 and Z = R31,R30) X+ Y+ Z+ indirect address with post-increment (only for data memory) -X -Y -Z indirect address with pre-decrement (only for data memory) Y+q Z+q indirect with displacement6 (only for data memory) Z program memory constant-address16 (only for program mem tables) Z+ program memory post-increment (only for prog mem arrays) k direct-program-memory-address22 (only JMP/CALL instr, not data) k PC + offset7 (-64..+63) (only for branches, not data) k PC + constant12 (-2048..+2047) (only for RJMP/RCALL, not data) Z indirect program memory address (only for IJMP/ICALL, not data) Instruction Formats, in Machine Code Words: ------------------------------------------- (in order: simple, register, immediate, memory, bit, in/out, jump) oooo opcode16 ooso opcode13+bitindex3 (only status bit instr) oodo opcode11+dest5 oKdK opcode4+dest4+immed8 oodK opcode8+dest2+immed6 (only ADIW/SBIW instr) oodr opcode6+dest5+reg5 oodr opcode8+dest4+reg4 (only MOVW/MULS instr) oodr opcode10+dest3+reg3 (only MULSU/FMUL* instr) oodokkkk opcode11+dest5 datamem-addr16 (only LDS/STS instr) oqdq opcode5+dest5+offset6 (only LDD/STD instr) oodb opcode8+dest/reg5+bitindex3 (only register bit instr) oAdA opcode5+dest5+in/out-addr6 ooAb opcode8+in/out-addr5+bitindex3 (only in-out bit instr) okkk opcode4+progmem-offset12 (only RJMP/RCALL instr) ookokkkk opcode10+progmem-addr-high6 progmem-addr-low16 (only JMP/CALL instr) okks opcode6+bitindex3+progmem-offset7 (only BRBS/BRBC instr) Instruction Bit Patterns and Operations: ---------------------------------------- (in order: functional grouping: arithmetic, data transfer, jumps, auxillary) arithmetic/logic 8bit oooooord ddddrrrr oooooo.. ........ opcode operation 000001.. ........ CPC FlagsHSVNZC = Rd - Rr - FlagC "ComPare w Carry" 000010.. ........ SBC Rd = Rd - Rr - FlagC; FlagsHSVNZC "SuBtr w Carry" 000011.. ........ ADD Rd = Rd + Rr; FlagsHSVNZC "ADD" = LSL is ADD with Rr = Rd "Logical Shift Left" 000101.. ........ CP FlagsHSVNZC = Rd - Rr "ComPare" 000110.. ........ SUB Rd = Rd - Rr; FlagsHSVNZC "SUBtract" 000111.. ........ ADC Rd = Rd + Rr + FlagC; FlagsHSVNZC "ADd w Carry" = ROL is ADC with Rr = Rd "ROtate Left" 001000.. ........ AND Rd = Rd bitwise-AND Rr; FlagsSVNZ V=0 "logic AND" = TST is AND with Rr = Rd "TeST" 001001.. ........ EOR Rd = Rd bitwise-excl-OR Rr; FlagsSVNZ V=0 "Exc OR" = CLR is EOR with Rr = Rd "CLear Register" 001010.. ........ OR Rd = Rd bitwise-OR Rr; FlagsSVNZ V=0 "logic OR" 100111.. ........ MUL R1:R0 = Rd * Rr; FlagsZC "MULtiply" .......d dddd.... destination register, 0..31 ......r. ....rrrr second register, 0..31 oooooooo ddddrrrr oooooooo ........ opcode operation 00000010 ........ MULS R1:R0 = Rd * Rr; FlagsZC "MULtiply Signed" ........ dddd.... destination register, 16..31 ........ ....rrrr second register, 16..31 oooooooo odddorrr oooooooo o...o... opcode operation 00000011 0...0... MULSU R1:R0 = Rd * Rr; FlagsZC "MULt Signed w Unsigned" 00000011 0...1... FMUL R1:R0 = Rd * Rr * 2; FlagsZC "Fractional MULtip" 00000011 1...0... FMULS R1:R0 = Rd * Rr * 2; FlagsZC "Fract MULt Signed" 00000011 1...1... FMULSU R1:R0 = Rd * Rr * 2; FlagsZC "Fract MULt S w U" ........ .ddd.... destination register, 16..23 ........ .....rrr second register, 16..23 ooooKKKK ddddKKKK oooo.... ........ opcode operation 0011.... ........ CPI FlagsHSVNZC = Rd - K "ComPare Immediate" 0100.... ........ SBCI Rd = Rd - K - FlagC; FlagsHSVNZC "SuBt w Car Imm" (no ADCI, use SBCI -K) 0101.... ........ SUBI Rd = Rd - k; FlagsHSVNZC "SuBtract Immediate" (no ADDI, use SUBI -K) 0110.... ........ ORI Rd = Rd bitwise-OR K; FlagsSVNZ V=0 "log OR w Imm" = SBR additional name for ORI "Set Bits in Register" 0111.... ........ ANDI Rd = Rd bitwise-AND K; FlagsSVNZ V=0 "log AND w I" = CBR is ANDI with bitwise-NOT K "Clear Bits in Reg" ........ dddd.... destination register, 16..31 ....KKKK ....KKKK immediate8 arithmetic 16bit oooooooo KKdd KKKK oooooooo ........ opcode operation 10010110 ........ ADIW Rd+1,Rd = Rd+1,Rd + K; FlagsSVNZC "ADd Immediate to Word (= register pair)" 10010111 ........ SBIW Rd+1,Rd = Rd+1,Rd - K; FlagsSVNZC "SuBtract Immediate fr Word (= reg pair)" ........ ..dd.... destination register pair, R25:R24 .. R31:R30 ........ KK..KKKK immediate6 increment/decrement oooooood ddddoooo ooooooo. ....oooo opcode operation 1001010. ....0011 INC Rd = Rd + 1; FlagsSVNZ "INCrement" 1001010. ....1010 DEC Rd = Rd - 1; FlagsSVNZ "DECrement" .......d dddd.... destination register, 0..31 shift/rotate/swap oooooood ddddoooo ooooooo. ....oooo opcode operation 1001010. ....0010 SWAP Rd = Rd(bit3..0,7..4) "SWAP nibbles" 1001010. ....0101 ASR Rd,FlagC = Rd(bit7),Rd; FlagsSVNZC "Arith Sh Rig" 1001010. ....0110 LSR Rd,FlagC = 0,Rd; FlagsSVNZC "Logical Shift Right" 1001010. ....0111 ROR Rd,FlagC = FlagC,Rd; FlagsSVNZC "Rotate Right" * LSL is ADD with Rr = Rd "Logical Shift Left" * ROL is ADC with Rr = Rd "ROtate Left" .......d dddd.... destination register, 0..31 other specialised arithmetic oooooood ddddoooo ooooooo. ....oooo opcode operation 1001010. ....0000 COM Rd = bitwise-NOT Rd; FlagsSVNZC V=0 C=1 "one's COMplement" 1001010. ....0001 NEG Rd = - Rd; FlagsHSVNZC "two's compl (= NEGate)" * CLR is EOR with Rr = Rd "CLear Register" * SER is LDI with K = 255 "SEt Register" .......d dddd.... destination register, 0..31 load/store/register 8bit oooooord ddddrrrr oooooo.. ........ opcode operation 001011.. ........ MOV Rd = Rr "MOVe register" .......d dddd.... destination register, 0..31 ......r. ....rrrr second register, 0..31 ooqoqqoq ddddoqqq oo.o..o. ....o... opcode operation 10.0..0. ....0... LDD ,Z+q Rd = mem[R31,R30+q] "LoaD indir w Deplacement" = LD ,Z is LDD ,Z+q with q=0 "LoaD indirect" 10.0..0. ....1... LDD ,Y+q Rd = mem[R29,R28+q] "LoaD indir w Deplacement" = LD ,Y is LDD ,Y+q with q=0 "LoaD indirect" 10.0..1. ....0... STD ,Z+q mem[R31,R30+q] = Rd "STore indir w Deplacement" = ST ,Z is STD ,Z+q with q=0 "STore indirect" 10.0..1. ....1... STD ,Y+q mem[R29,R28+q] = Rd "STore indir w Deplacement" = ST ,Y is STD ,Y+q with q=0 "STore indirect" .......d dddd.... destination register, 0..31 ..q.qq.. .....qqq displacement6 oooooood ddddoooo ooooooo. ....oooo opcode operation * LD ,Z is LDD ,Z+q with q=0 "LoaD indirect" 1001000. ....0001 LD ,Z+ Rd = mem[R31,R30++] "LoaD indir post-increm" 1001000. ....0010 LD ,-Z Rd = mem[--R31,R30] "LoaD indir pre-decrem" 1001000. ....0100 LPM ,Z Rd = progmem[R31,R30] "Load Program Memory" 1001000. ....0101 LPM ,Z+ Rd = progmem[R31,R30++] "L P M post-increm" 1001000. ....0110 ELPM ,Z Rd = progmem[RAMPZ,R31,R30] "Exten Load Prog M" 1001000. ....0111 ELPM ,Z+ Rd = progmem[RAMPZ,R31,R30++] "Ext L P M pos-in" * LD ,Y is LDD ,Y+q with q=0 "LoaD indirect" 1001000. ....1001 LD ,Y+ Rd = mem[R29,R28++] "LoaD indir post-increm" 1001000. ....1010 LD ,-Y Rd = mem[--R29,R28] "LoaD indir pre-decrem" 1001000. ....1100 LD ,X Rd = mem[R27,R26] "LoaD indirect" 1001000. ....1101 LD ,X+ Rd = mem[R27,R26++] "LoaD indir post-increm" 1001000. ....1110 LD ,-X Rd = mem[--R27,R26] "LoaD indir pre-decrem" * ST Z, is STD ,Z+q with q=0 "STore indirect" 1001001. ....0001 ST Z+, mem[R31,R30++] = Rd "STore indir post-increm" 1001001. ....0010 ST -Z, mem[--R31,R30] = Rd "STore indir pre-decrem" * ST Y, is STD ,Y+q with q=0 "STore indirect" 1001001. ....1001 ST Y+, mem[R29,R28++] = Rd "STore indir post-increm" 1001001. ....1010 ST -Y, mem[--R29,R28] = Rd "STore indir pre-decrem" 1001001. ....1100 ST X, mem[R27,R26] = Rd "STore indirect" 1001001. ....1101 ST X+, mem[R27,R26++] = Rd "STore indir post-increm" 1001001. ....1110 ST -X, mem[--R27,R26] = Rd "STore indir pre-decrem" .......d dddd.... LD destination or ST source register, 0..31 oooooood ddddoooo kkkkkkkk kkkkkkkk ooooooo. ....oooo opcode operation 1001000. ....0000 LDS Rd = mem[k] "LoaD direct from data Space" 1001001. ....0000 STS mem[k] = Rd "STore direct to data Space" .......d dddd.... LD destination or ST source register, 0..31 kkkkkkkk kkkkkkkk second instruction word, address16 ooooKKKK ddddKKKK oooo.... ........ opcode operation 1110.... ........ LDI Rd = K "LoaD Immediate" = SER is LDI with K = 255 "SEt Register" ........ dddd.... destination register, 16..31 ....KKKK ....KKKK immediate8 register 16bit oooooooo dddd rrrr oooooooo ........ opcode operation 00000001 ........ MOVW Rd+1,Rd = Rr+1,Rr "MOVe Word (= register pair)" ........ dddd.... destination register pair, R1:R0 .. R31:R30 ........ ....rrrr second register pair, R1:R0 .. R31:R30 stack push/pop oooooood ddddoooo ooooooo. ....oooo opcode operation 1001000. ....1111 POP Rd = mem[++SPH,SPL] "POP register from stack" 1001001. ....1111 PUSH mem[SPH,SPL--] = Rd "PUSH register on stack" .......d dddd.... destination register, 0..31 input and output oooooAAd ddddAAAA ooooo... ........ opcode operation 10110... ........ IN Rd = mem[A+32] "IN/load an i/o location to reg" 10111... ........ OUT mem[A+32] = Rd "OUT/store reg to i/o location" .......d dddd.... destination register, 0..31 .....AA. ....AAAA short-direct-address6, 0..63 oooooooo AAAAAbbb oooooooo ........ opcode operation 10011000 ........ CBI mem[A+32] = mem[A+32] bitwise-AND NOT 2^bit "Clear Bit in Io register" 10011010 ........ SBI mem[A+32] = mem[A+32] bitwise-OR 2^bit "Set Bit in Io register" ........ AAAAA... short-direct-address5, 0..31 ........ .....bbb bit (0..7) other specialised data transfer oooooooo oooooooo opcode operation 10010101 11001000 LPM R0 = progmem[R31,R30] "Load Program Memory" 10010101 11011000 ELPM R0 = progmem[RAMPZ,R31,R30] "Exten Load Prog Mem" 10010101 11101000 SPM progmem[RAMPZ,R31,R30] = R1,R0 "Store Prog Mem" oooooood ddddobbb ooooooo. ....o... opcode operation 1111100. ....0... BLD Rd bit bbb = FlagT "Bit LoaD from the t flag in sreg to a bit in register" 1111101. ....0... BST FlagT = Rd bit bbb "Bit STore from bit in register to t flag in sreg" .......d dddd.... destination register, 0..31 ........ .....bbb bit (0..7) jumps/subroutines and reset/interrupts oooooooo oooooooo opcode operation 00000000 00000000 NOP do nothing "No OPeration" 10010100 00001001 IJMP PC = R31,R30 "Indirect JuMP" 10010100 00011001 EIJMP PC = EIND,R31,R30 "Extended Indirect JuMP" 10010101 00001001 ICALL mem[SPH,SPL--] = PC; PC = R31,R30 "Indir CALL Sub" 10010101 00011001 EICALL mem[SPH,SPL--] = PC; PC = EIND,R31,R30 "Ext I C S" 10010101 00001000 RET PC = mem[++SPH,SPL] "subroutine RETurn" 10010101 00011000 RETI PC = mem[++SPH,SPL]; FlagI=1 "Return from Interr" 10010101 10001000 SLEEP set sleep mode from MCUCR "SLEEP" 10010101 10011000 BREAK stop for on-chip debug system "BREAK" 10010101 10101000 WDR reset watchdog timer "WatchDog Reset" oooooook kkkkoook kkkkkkkkkkkk kkkk ooooooo. ....000. opcode operation 1001010. ....110. JMP "JuMP" 1001010. ....111. CALL "CALL subroutine" .......k kkkk...k direct-program-memory-address6 (bits 21..16) kkkkkkkk kkkkkkkk second instruct word (bits 15..0) ooookkkk kkkkkkkk oooo.... ........ opcode operation 1100.... ........ RJMP PC = PC + k "Relative JuMP" 1101.... ........ RCALL mem[SPH,SPL--] = PC; PC = PC + k "Relat CALL Sub" ....kkkk kkkkkkkk constant12 ---- pin RESET PC = 0 or Boot Reset Addr "RESET" -- flags interrupt FlagI = 0; mem[SPH,SPL--] = PC; "* Interrupt Flag" PC = 0 or B R A + vector 1..n * size 1 or 2 branches/conditionals ooooookk kkkkksss ooooo... ........ opcode operation 11110... ........ BRss if status then PC = PC + k "BRanch if ss" .....s.. .....sss ss status/condition .....0.. .....sss BS s, s = 1 "Bit in sreg is Set" .....0.. .....000 CS C = 1 "Carry Set" = LO additional name for CS "LOwer (unsigned)" .....0.. .....001 EQ Z = 1 "Equal" .....0.. .....010 MI N = 1 "MInus" .....0.. .....011 VS V = 1 "oVerflow Set" .....0.. .....100 LT S = 1 "Less Than (signed)" .....0.. .....101 HS H = 1 "Half carry is Set" .....0.. .....110 TS T = 1 "the T flag is Set" .....0.. .....111 IE I = 1 "Interrupt is Enabled" .....1.. .....sss BC s, s = 0 "Bit in sreg is Cleared" .....1.. .....000 CC C = 0 "Carry Cleared" = SH additional name for CC "Same or Higher (unsign)" .....1.. .....001 NE Z = 0 "Not Equal" .....1.. .....010 PL N = 0 "PLus" .....1.. .....011 VC V = 0 "oVerflow Cleared" .....1.. .....100 GE S = 0 "Greater or Equal (signed)" .....1.. .....101 HC H = 0 "Half carry is Cleared" .....1.. .....110 TC T = 0 "the T flag is Cleared" .....1.. .....111 ID I = 0 "Interrupt is Disabled" ......kk kkkkk... offset7 oooooord ddddrrrr oooooo.. ........ opcode operation 000100.. ........ CPSE if Rd = Rr then PC = PC + 1 "ComPare Skip if Equ" .......d dddd.... destination register, 0..31 ......r. ....rrrr second register, 0..31 ooooooor rrrrobbb ooooooo. ....o... opcode operation 1111110. ....0... SBRC if (Rr bitwise-AND 2^bit) = 0 then PC = PC + 1 "Skip if Bit in Register is Cleared" 1111111. ....0... SBRS if (Rr bitwise-AND 2^bit) = 1 then PC = PC + 1 "Skip if Bit in Register is Set" .......r rrrr.... register, 0..31 ........ .....bbb bit (0..7) oooooooo AAAAAbbb oooooooo ........ opcode operation 10011001 ........ SBIC if (mem[A+32] bitwise-AND 2^bit) = 0 then PC = PC + 1 "Skip if Bit in Io register Cleared" 10011011 ........ SBIS if (mem[A+32] bitwise-AND 2^bit) = 1 then PC = PC + 1 "Skip if Bit in Io register Set" ........ AAAAA... short-direct-address5, 0..31 ........ .....bbb bit (0..7) flags oooooooo osssoooo oooooooo o...oooo opcode operation 10010100 0...1000 BSET s Flags = 1 "Bit SET s in sreg" SEs additional name for BSET "SEt s flag" 10010100 1...1000 BCLR s Flags = 0 "Bit CLeaR s in sreg" CLs additional name for BCLR "CLear s flag" ........ .sss.... s status/flag ........ .000.... C Carry ........ .001.... Z Zero ........ .010.... N Negative ........ .011.... V oVerflow ........ .100.... S Signed ........ .101.... H Half carry ........ .110.... T T ........ .111.... I global Interrupt Instruction Code List: ---------------------- (machine code word high bytes, in order: opcode number) 0000 NOP 10dr CPSE R0d,R0r 20dr AND R0d,R0r 30dK CPI R1d,0K 01dr MOVW Rd+1:Rd,11dr CPSE R1d,R0r 21dr AND R1d,R0r 31dK CPI R1d,1K 02dr MULS Rd,Rr 12dr CPSE R0d,R1r 22dr AND R0d,R1r 32dK CPI R1d,2K 03dr mulop Rd,Rr 13dr CPSE R1d,R1r 23dr AND R1d,R1r 33dK CPI R1d,3K 04dr CPC R0d,R0r 14dr CP R0d,R0r 24dr EOR R0d,R0r 34dK CPI R1d,4K 05dr CPC R1d,R0r 15dr CP R1d,R0r 25dr EOR R1d,R0r 35dK CPI R1d,5K 06dr CPC R0d,R1r 16dr CP R0d,R1r 26dr EOR R0d,R1r 36dK CPI R1d,6K 07dr CPC R1d,R1r 17dr CP R1d,R1r 27dr EOR R1d,R1r 37dK CPI R1d,7K 08dr SBC R0d,R0r 18dr SUB R0d,R0r 28dr OR R0d,R0r 38dK CPI R1d,8K 09dr SBC R1d,R0r 19dr SUB R1d,R0r 29dr OR R1d,R0r 39dK CPI R1d,9K 0Adr SBC R0d,R1r 1Adr SUB R0d,R1r 2Adr OR R0d,R1r 3AdK CPI R1d,AK 0Bdr SBC R1d,R1r 1Bdr SUB R1d,R1r 2Bdr OR R1d,R1r 3BdK CPI R1d,BK 0Cdr ADD R0d,R0r 1Cdr ADC R0d,R0r 2Cdr MOV R0d,R0r 3CdK CPI R1d,CK 0Ddr ADD R0d,R1r 1Ddr ADC R1d,R0r 2Ddr MOV R1d,R0r 3DdK CPI R1d,DK 0Edr ADD R0d,R1r 1Edr ADC R0d,R1r 2Edr MOV R0d,R1r 3EdK CPI R1d,EK 0Fdr ADD R1d,R1r 1Fdr ADC R1d,R1r 2Fdr MOV R1d,R1r 3FdK CPI R1d,FK 03dr: dr:mulop = [0..3][0..3]:MULSU, [0..3][4..7]:FMLU [4..7][0..3]:FMULS, [4..7][4..7]:FMLUSU 40dK SBCI R1d,0K 50dK SUBI R1d,0K 60dK ORI R1d,0K 70dK ANDI R1d,0K 41dK SBCI R1d,1K 51dK SUBI R1d,1K 61dK ORI R1d,1K 71dK ANDI R1d,1K 42dK SBCI R1d,2K 52dK SUBI R1d,2K 62dK ORI R1d,2K 72dK ANDI R1d,2K 43dK SBCI R1d,3K 53dK SUBI R1d,3K 63dK ORI R1d,3K 73dK ANDI R1d,3K 44dK SBCI R1d,4K 54dK SUBI R1d,4K 64dK ORI R1d,4K 74dK ANDI R1d,4K 45dK SBCI R1d,5K 55dK SUBI R1d,5K 65dK ORI R1d,5K 75dK ANDI R1d,5K 46dK SBCI R1d,6K 56dK SUBI R1d,6K 66dK ORI R1d,6K 76dK ANDI R1d,6K 47dK SBCI R1d,7K 57dK SUBI R1d,7K 67dK ORI R1d,7K 77dK ANDI R1d,7K 48dK SBCI R1d,8K 58dK SUBI R1d,8K 68dK ORI R1d,8K 78dK ANDI R1d,8K 49dK SBCI R1d,9K 59dK SUBI R1d,9K 69dK ORI R1d,9K 79dK ANDI R1d,9K 4AdK SBCI R1d,AK 5AdK SUBI R1d,AK 6AdK ORI R1d,AK 7AdK ANDI R1d,AK 4BdK SBCI R1d,BK 5BdK SUBI R1d,BK 6BdK ORI R1d,BK 7BdK ANDI R1d,BK 4CdK SBCI R1d,CK 5CdK SUBI R1d,CK 6CdK ORI R1d,CK 7CdK ANDI R1d,CK 4DdK SBCI R1d,DK 5DdK SUBI R1d,DK 6DdK ORI R1d,DK 7DdK ANDI R1d,DK 4EdK SBCI R1d,EK 5EdK SUBI R1d,EK 6EdK ORI R1d,EK 7EdK ANDI R1d,EK 4FdK SBCI R1d,FK 5FdK SUBI R1d,FK 6FdK ORI R1d,FK 7FdK ANDI R1d,FK 80dq LDD R0d,r+00 90do ldop R0d, A0dq LDD R0d,r+20 B0dA IN R0d,00 81dq LDD R1d,r+00 91do ldop R1d, A1dq LDD R1d,r+20 B1dA IN R1d,00 82dq STD R0d,r+00 92do stop R0d, A2dq STD R0d,r+20 B2dA IN R0d,10 83dq STD R1d,r+00 93do stop R1d, A3dq STD R1d,r+20 B3dA IN R1d,10 84dq LDD R0d,r+08 94do op R0d, A4dq LDD R0d,r+28 B4dA IN R0d,20 85dq LDD R1d,r+08 95do op R1d, A5dq LDD R1d,r+28 B5dA IN R1d,20 86dq STD R0d,r+08 96dK ADIW Rd+1:,K A6dq STD R0d,r+28 B6dA IN R0d,30 87dq STD R1d,r+08 97dK SBIW Rd+1:,K A7dq STD R1d,r+28 B7dA IN R1d,30 88dq LDD R0d,r+10 98Ab CBI A,b A8dq LDD R0d,r+28 B8dA OUT R0d,00 89dq LDD R1d,r+10 99Ab SBIC A,b A9dq LDD R1d,r+30 B9dA OUT R1d,00 8Adq STD R0d,r+10 9AAb SBI A,b AAdq STD R0d,r+30 BAdA OUT R0d,10 8Bdq STD R1d,r+10 9BAb SBIS A,b ABdq STD R1d,r+30 BBdA OUT R1d,10 8Cdq LDD R0d,r+18 9Cdr MUL R0d,R0r ACdq LDD R0d,r+38 BCdA OUT R0d,20 8Ddq LDD R1d,r+18 9Ddr MUL R1d,R0r ADdq LDD R1d,r+38 BDdA OUT R1d,20 8Edq STD R0d,r+18 9Edr MUL R0d,R1r AEdq STD R0d,r+38 BEdA OUT R0d,30 8Fdq STD R1d,r+18 9Fdr MUL R1d,R1r AFdq STD R1d,r+38 BFdA OUT R1d,30 80..8F|A0..AF: q:r = 0..7:Z, 8..F:Y 90|91: o:ldop = 0:LDS 1:LD,Z+ 2:LD,-Z 4:LPM,Z 5:LPM,Z+ 6:ELPM,Z 7:ELMP,Z+ 9:LD,Y+ A:LD,-Y C:LD,X D:LD,X+ E:LD,-X F:POP 92|93: o:stop = 0:STS 1:ST,Z+ 2:ST,-Z 9:ST,Y+ A:ST,-Y C:ST,X D:ST,X+ E:ST,-X F:PUSH 90|92: for ldop|stop = 0 = LDS|STS followed by 16bit address 94|95: o:op = 0:COM 1:NEG 2:SWAP 3:INC 5:ASR 6:LSR 7:ROR 8:BSET/CLR|RET...SPM 9:(E)IJMP|(E)ICALL A:DEC C|D:JMP E|F:CALL C0kk RJMP 0kk D0kk RCALL 0kk E0dK LDI R1d,0K F0ks BRBS s,00 C1kk RJMP 1kk D1kk RCALL 1kk E0dK LDI R1d,1K F0ks BRBS s,08 C2kk RJMP 2kk D2kk RCALL 2kk E0dK LDI R1d,2K F0ks BRBS s,10 C3kk RJMP 3kk D3kk RCALL 3kk E0dK LDI R1d,3K F0ks BRBS s,18 C4kk RJMP 4kk D4kk RCALL 4kk E0dK LDI R1d,4K F0ks BRBC s,00 C5kk RJMP 5kk D5kk RCALL 5kk E0dK LDI R1d,5K F0ks BRBC s,08 C6kk RJMP 6kk D6kk RCALL 6kk E0dK LDI R1d,6K F0ks BRBC s,10 C7kk RJMP 7kk D7kk RCALL 7kk E0dK LDI R1d,7K F0ks BRBC s,18 C8kk RJMP 8kk D8kk RCALL 8kk E0dK LDI R1d,8K F0db BLD R0d,b C9kk RJMP 9kk D9kk RCALL 9kk E0dK LDI R1d,9K F0db BLD R1d,b CAkk RJMP Akk DAkk RCALL Akk E0dK LDI R1d,AK F0db BST R0d,b CBkk RJMP Bkk DBkk RCALL Bkk E0dK LDI R1d,BK F0db BST R1d,b CCkk RJMP Ckk DCkk RCALL Ckk E0dK LDI R1d,CK F0rb SBRC R0r,b CDkk RJMP Dkk DDkk RCALL Dkk E0dK LDI R1d,DK F0rb SBRC R1r,b CEkk RJMP Ekk DEkk RCALL Ekk E0dK LDI R1d,EK F0rb SBRS R0r,b CFkk RJMP Fkk DFkk RCALL Fkk E0dK LDI R1d,FK F0rb SBRS R1r,b Instruction Code Table: ----------------------- (only opcodes, in order: ver: bit15..14/13..11, hor: bit10..8, ignore: bit7..0) + 00xx 01xx 02xx 03xx 04xx 05xx 06xx 07xx 00 NOP MOVW MULS mulop CPC 0d0r CPC 1d0r CPC 0d1r CPC 1d1r 08 SBC 0d0r SBC 1d0r SBC 0d1r SBC 1d1r ADD 0d0r ADD 1d0r ADD 0d1r ADD 1d1r 10 CPSE 0d0rCPSE 1d0rCPSE 0d1rCPSE 1d1rCP 0d0r CP 1d0r CP 0d1r CP 1d1r 18 SUB 0d0r SUB 1d0r SUB 0d1r SUB 1d1r ADC 0d0r ADC 1d0r ADC 0d1r ADC 1d1r 20 AND 0d0r AND 1d0r AND 0d1r AND 1d1r EOR 0d0r EOR 1d0r EOR 0d1r EOR 1d1r 28 OR 0d0r OR 1d0r OR 0d1r OR 1d1r MOV 0d0r MOV 1d0r MOV 0d1r MOV 1d1r 30 CPI ,0K CPI ,1K CPI ,2K CPI ,3K CPI ,4K CPI ,5K CPI ,6K CPI ,7K 38 CPI ,8K CPI ,9K CPI ,AK CPI ,BK CPI ,CK CPI ,DK CPI ,EK CPI ,FK 40 SBCI ,0K SBCI ,1K SBCI ,2K SBCI ,3K SBCI ,4K SBCI ,5K SBCI ,6K SBCI ,7K 48 SBCI ,8K SBCI ,9K SBCI ,AK SBCI ,BK SBCI ,CK SBCI ,DK SBCI ,EK SBCI ,FK 50 SUBI ,0K SUBI ,1K SUBI ,2K SUBI ,3K SUBI ,4K SUBI ,5K SUBI ,6K SUBI ,7K 58 SUBI ,8K SUBI ,9K SUBI ,AK SUBI ,BK SUBI ,CK SUBI ,DK SUBI ,EK SUBI ,FK 60 ORI ,0K ORI ,1K ORI ,2K ORI ,3K ORI ,4K ORI ,5K ORI ,6K ORI ,7K 68 ORI ,8K ORI ,9K ORI ,AK ORI ,BK ORI ,CK ORI ,DK ORI ,EK ORI ,FK 70 ANDI ,0K ANDI ,1K ANDI ,2K ANDI ,3K ANDI ,4K ANDI ,5K ANDI ,6K ANDI ,7K 78 ANDI ,8K ANDI ,9K ANDI ,AK ANDI ,BK ANDI ,CK ANDI ,DK ANDI ,EK ANDI ,FK 80 LDD 0d+00LDD 1d+00STD 0d+00STD 1d+00LDD 0d+08LDD 1d+08STD 0d+08STD 1d+08 88 LDD 0d+10LDD 1d+10STD 0d+10STD 1d+10LDD 0d+18LDD 1d+18STD 0d+18STD 1d+08 90 ldop 0d ldop 1d stop 0d stop 1d op 0d op 1d ADIW SBIW 98 CBI SBIC SBI SBIS MUL 0d0r MUL 1d0r MUL 0d1r MUL 1d1r A0 LDD 0d+20LDD 1d+20STD 0d+20STD 1d+20LDD 0d+28LDD 1d+28STD 0d+28STD 1d+28 A8 LDD 0d+30LDD 1d+30STD 0d+30STD 1d+30LDD 0d+38LDD 1d+38STD 0d+38STD 1d+38 B0 IN 0d,00 IN 1d,00 IN 0d,10 IN 1d,10 IN 0d,20 IN 1d,20 IN 0d,30 IN 1d,30 B8 OUT 0d,00OUT 1d,00OUT 0d,10OUT 1d,10OUT 0d,20OUT 1d,20OUT 0d,30OUT 1d,30 C0 RJMP 0kk RJMP 1kk RJMP 2kk RJMP 3kk RJMP 4kk RJMP 5kk RJMP 6kk RJMP 7kk C8 RJMP 8kk RJMP 9kk RJMP Akk RJMP Bkk RJMP Ckk RJMP Dkk RJMP Ekk RJMP Fkk D0 RCALL 0kkRCALL 1kkRCALL 2kkRCALL 3kkRCALL 4kkRCALL 5kkRCALL 6kkRCALL 7kk D8 RCALL 8kkRCALL 9kkRCALL AkkRCALL BkkRCALL CkkRCALL DkkRCALL EkkRCALL Fkk E0 LDI ,0K LDI ,1K LDI ,2K LDI ,3K LDI ,4K LDI ,5K LDI ,6K LDI ,7K E8 LDI ,8K LDI ,9K LDI ,AK LDI ,BK LDI ,CK LDI ,DK LDI ,EK LDI ,FK F0 BRBS ,00 BRBS ,10 BRBS ,20 BRBS ,30 BRBC ,00 BRBC ,10 BRBC ,20 BRBC ,30 F8 BLD 0d, BLD 1d, BST 0d, BST 1d, SBRC 0r, SBRC 1r, SBRS 0r, SBRS 1r, Instruction Code Tree: ---------------------- (full machine code words, in order: opcode number) 0000 0000 0000 0000 NOP 0000 0001 dddd rrrr MOVW Rd+1:Rd,Rr+1:Rr 0000 0010 dddd rrrr MULS Rd,Rr 0000 0011 0ddd 0rrr MULSU Rd,Rr 0000 0011 0ddd 1rrr FMUL Rd,Rr 0000 0011 1ddd 0rrr FMULS Rd,Rr 0000 0011 1ddd 1rrr FMULSU Rd,Rr 0000 01rd dddd rrrr CPC Rd,Rr 0000 10rd dddd rrrr SBC Rd,Rr 0000 11rd dddd rrrr ADD Rd,Rr (and with Rr=Rd: LSL Rd) 0001 00rd dddd rrrr CPSE Rd,Rr 0001 01rd dddd rrrr CP Rd,Rr 0001 10rd dddd rrrr SUB Rd,Rr 0001 11rd dddd rrrr ADC Rd,Rr (and with Rr=Rd: ROL Rd) 0010 00rd dddd rrrr AND Rd,Rr (and with Rr=Rd: TST Rd) 0010 01rd dddd rrrr EOR Rd,Rr (and with Rr=Rd: CLR Rd 0010 10rd dddd rrrr OR Rd,Rr 0010 11rd dddd rrrr MOV Rd,Rr 0011 KKKK dddd KKKK CPI Rd,K 0100 KKKK dddd KKKK SBCI Rd,K 0101 KKKK dddd KKKK SUBI Rd,K 0110 KKKK dddd KKKK ORI Rd,K (and with other name: SBR Rd,K) 0111 KKKK dddd KKKK ANDI Rd,K (and with !K other name: CBR Rd,K) 10q0 qq0d dddd 0qqq LDD Rd,Z+q (and with q=0 other name: LD Rd,Z) 10q0 qq0d dddd 1qqq LDD Rd,Y+q (and with q=0 other name: LD Rd,Y) 10q0 qq1d dddd 0qqq STD Rd,Z+q (and with q=0 other name: ST Rd,Z) 10q0 qq1d dddd 1qqq STD Rd,Y+q (and with q=0 other name: ST Rd,Y) 1001 000d dddd 0000 kkkk kkkk kkkk kkkk LDS Rd,k 1001 000d dddd 0001 LD Rd,Z+ 1001 000d dddd 0010 LD Rd,-Z 1001 000d dddd 0100 LPM Rd,Z 1001 000d dddd 0101 LPM Rd,Z+ 1001 000d dddd 0110 ELPM Rd,Z 1001 000d dddd 0111 ELPM Rd,Z+ 1001 000d dddd 1001 LD Rd,Y+ 1001 000d dddd 1010 LD Rd,-Y 1001 000d dddd 1100 LD Rd,X 1001 000d dddd 1101 LD Rd,X+ 1001 000d dddd 1110 LD Rd,-X 1001 000d dddd 1111 POP Rd 1001 001d dddd 0000 kkkk kkkk kkkk kkkk STS Rd,k 1001 001d dddd 0001 ST Rd,Z+ 1001 001d dddd 0010 ST Rd,-Z 1001 001d dddd 1001 ST Rd,Y+ 1001 001d dddd 1010 ST Rd,-Y 1001 001d dddd 1100 ST Rd,X 1001 001d dddd 1101 ST Rd,X+ 1001 001d dddd 1110 ST Rd,-X 1001 001d dddd 1111 PUSH Rd 1001 010d dddd 0000 COM Rd 1001 010d dddd 0001 NEG Rd 1001 010d dddd 0010 SWAP Rd 1001 010d dddd 0011 INC Rd 1001 010d dddd 0101 ASR Rd 1001 010d dddd 0110 LSR Rd 1001 010d dddd 0111 ROR Rd 1001 010d dddd 1010 DEC Rd 1001 0100 0sss 1000 BSET s (and with other name: SEs) 1001 0100 1sss 1000 BCLR s (and with other name: CLs) 1001 0100 0000 1001 IJMP 1001 0100 0001 1001 EIJMP 1001 0101 0000 1001 ICALL 1001 0101 0001 1001 EICALL 1001 0101 0000 1000 RET 1001 0101 0001 1000 RETI 1001 0101 1000 1000 SLEEP 1001 0101 1001 1000 BREAK 1001 0101 1010 1000 WDR 1001 0101 1100 1000 LPM 1001 0101 1101 1000 ELPM 1001 0101 1110 1000 SPM 1001 010k kkkk 110k kkkk kkkk kkkk kkkk JMP k 1001 010k kkkk 111k kkkk kkkk kkkk kkkk CALL k 1001 0110 KKdd KKKK ADIW Rd+1:Rd,K 1001 0111 KKdd KKKK SBIW Rd+1:Rd,K 1001 1000 AAAA Abbb CBI A,b 1001 1001 AAAA Abbb SBIC A,b 1001 1010 AAAA Abbb SBI A,b 1001 1011 AAAA Abbb SBIS A,b 1001 11rd dddd rrrr MUL Rd,Rr 1010 see 1000 1011 0AAd dddd AAAA IN Rd,A 1011 1AAd dddd AAAA OUT Rd,A 1100 kkkk kkkk kkkk RJMP k 1101 kkkk kkkk kkkk RCALL k 1110 KKKK dddd KKKK LDI Rd,K (and with K=0xFF other name: SER Rd) 1111 00kk kkkk ksss BRBS s,k 1111 01kk kkkk ksss BRBC s,k 1111 100d dddd 0bbb BLD Rd,b 1111 101d dddd 0bbb BST Rd,b 1111 110r rrrr 0bbb SBRC Rr,b 1111 111r rrrr 0bbb SBRS Rr,b