8080 Instruction Set (including 8085 extensions) author Neil Franklin, last modification 2008.01.09 Basics: ------- All numbers and bit patterns in this file are usually given in hex, seldom in binary, never in decimal or octal. Sources for this data: ---------------------- 1. Full description of the Z80 (upwards compatible to 8080), including an Intel<->Zilog Mnemonic convertion appendix, contained in the book "Programming the Z80" by Rodney Zaks, 3rd Edition, 1982. Used that for programming an Columbia Commander 924 (school computer, first computer I ever programmed) and later an Multitech Microprofessor MPF 1P (an other schools computer), so it can be assumed to be correct. 2. Official Siemens (Intel licensee) 8085 instruction shortlist. Used that to program an TK-80 and an Siemens SME (yet another schools 2 computers). Very unlikely to contain errors. Of course errors of my own are to be expected. Registers: ---------- (in order: data, address, pc, flags, auxillary) A 8bit Accumulator B C D E H L 8bit General Purpose Registers BC DE HL 16bit Register Pairs (= B,C D,E H,L merged as high,low) SP 16bit Stack Pointer (push pre-decr, pop post-incr) PC 16bit Program Counter F 8bit Flags Register PSW 16bit Register Pair (= A,F merged as high,low) IFF 1bit Interrupt FlipFlop (1 enables INT) IM 8bit Interrupt Mask Register (only in 8085, 8080 single flag) Flags Register: --------------- (in order: from MSB/7 to LSB/0) S Sign (result bit7 set) Z Zero (result all bits cleared) - unused A Auxillary Carry (arithmetic result carry bit3->bit4, used only by DAA) X ??? (purpose not known to me) (only in 8085) P Parity (result parity even) N Subtract (operation was additive or subtractive, used only by DAA) C Carry (arithmetic result carry bit7->"bit8") General policy seems to be: - 8bit arithmetic (incl DAA): set all SZAVNC (additions N=0, subtractions N=1) - 16bit arithmetic (DAD): set ANC (AC from high byte) - 8bit decrement/increment: set SZAVN, leave C unchanged (dec N=1, inc N=0) - 16bit decrement/increment: leave all flags, so address computation leaves all - logic stuff: set all SZAPNC (with ANC allways set to constant) - shift/rotate: set ANC - load/store/move/in/out/stack: leave all flags - jump/call/return: leave all flags Memory: ------- Program+Data memory 64k*8bit (16bit address space) I/O devices 256*8bit (8bit address space) Addressing Modes, in Assembler Syntax: -------------------------------------- (in order: reg, immediate, address, reg indirect, reg indexed, pc) A accumulator B C D E H L register B D H SP PSW register pair (B=B,C D=D,E H=H,L) -nameless- interrupt flag register (only EI/DI) -nameless- interrupt mask register (only RIM/SIM, only in 8085) n immediate8 nn immediate-extended16 n short-address8 (only IN/OUT instr) nn extended-address16 M register pair indirect B D register pair indirect (only LDAX/STAX instr) -nameless- stack pointer indirect decrement/increment (only PUSH/POP) Instruction Formats, in Machine Code Bytes: ------------------------------------------- (in order: simple, immediate, register, memory, in/out, jump+conditional) oo opcode8 oonn opcode8 immediate8 (only LDI instr) oonnnn opcode8 immediate-low8 immediate-high8 (= little endian) (only LXI) or opcode5+reg-address3 orbb opcode5+reg-address3 immediate8 or opcode6+regpair-address2 or opcode2+destreg-address3+sourcereg-address3 oonnnn opcode8 address-low8 address-high8 (= little endian) oonn opcode8 in/out-address8 ocnnnn opcode5+condit3 addr-low8 addr-high8 (= little endian) (only Jcc/Ccc) oc opcode5+condition3 (only Rcc instr) os opcode5+address3 (only RST instr) Instruction Bit Patterns and Operations: ---------------------------------------- (in order: functional grouping: arithmetic, data transfer, jumps, auxillary) arithmetic/logic 8bit 1sooosss ..ooo... opcode operation ..000... ADD A = A + source; FlagsSZAVNC,N=0 "ADD" ..001... ADC A = A + source + FlagC FlagsSZAVNC,N=0 "ADd with Carry" ..010... SUB A = A - source; FlagsSZAVNC,N=1 "SUBtract" ..011... SBB A = A - source - FlagC FlagsSZAVNC,N=1 "SuBtract with Borrow" ..100... ANA A = A bitwise-AND source; FlagsSZAPNC,A=1,N=0,C=0 "ANd Acc" ..101... XRA A = A bitwise-excl-OR source FlagsSZAPNC,A=0,N=0,C=0 "eXclusive oR Acc" ..110... ORA A = A bitwise-OR source FlagsSZAPNC,A=0,N=0,C=0 "OR Acc" ..111... CMP FlagsSZAVC = A - source; FlagN=1 "CoMPare" .s...sss source .0...000 B .0...001 C .0...010 D .0...011 E .0...100 H .0...101 L .0...110 M mem[H,L] .0...111 A .1...110 n mem[PC+] (immediate8) ADD->ADI, ADC->ACI, SUB->SUI, SBB->SBI ANA->ANI, XRA->XRI, ORA->ORI, CMP->CPI arithmetic 16bit 00ss1001 opcode operation ........ DAD HL = HL + source FlagsNC,A=bit11-carry,N=0,C=bit15-carry "Double ADd" ..ss.... source ..00.... B B,C ..01.... D D,E ..10.... H H,L ..11.... SP SP increment/decrement 8bit 00ddd10o .......o opcode operation .......0 INR dest = dest + 1; FlagsSZAVN,N=0 "INcrement Register" .......1 DCR dest = dest - 1; FlagsSZAVN,N=1 "DeCrement Register" ..ddd... destination ..000... B ..001... C ..010... D ..011... E ..100... H ..101... L ..110... M mem[H,L] ..111... A increment/decrement 16bit 00ddo011 ....o... opcode operation ....0... INX dest = dest + 1 (no flags!) "INcrement eXtended" ....1... DCX dest = dest - 1 (no flags!) "DeCrement eXtended" ..dd.... destination ..00.... B B,C ..01.... D D,E ..10.... H H,L ..11.... SP SP shift/rotate 000oo111 ...oo... opcode operation ...00... RLC A = A(bit6..0,7); FlagC=A(bit7); FlagsAN,A=0,N=0 "Rotate Left with Carry" ...01... RRC A = A(bit0,7..1); FlagC=A(bit0); FlagsAN,A=0,N=0 "Rotate Right with Carry" ...10... RAL FlagC,A = A,FlagC; FlagsAN,A=0,N=0 "Rotate Acc Left" ...11... RAR A,FlagC = FlagC,A; FlagsAN,A=0,N=0 "Rotate Acc Right" other specialised arithmetic oooooooo opcode operation 00100111 DAA if FlagN = 0 (after addition/increment) if A(bit3..0) > 9 or FlagA = 1 then A = A + 6; FlagC if A(bit7..4) > 9 or FlagC = 1 then A = A + 96 if FlagN = 1 (after subraction/decrement/negate) if A(bit3..0) > 9 or FlagA = 1 then A = A - 6; FlagC if A(bit7..4) > 9 or FlagC = 1 then A = A - 96 FlagsSZAPC "Decimal Adjust Accumulator" 00101111 CMA A = bitwise-NOT A; FlagsAN,A=1,N=1 "CoMplement Acc" load/store/register 8bit 00aao010 ....o... opcode operation ....0... STAX destination = A "STore Acc eXtendend" ....1... LDAX A = source "LoaD Acc eXtendend" ..aa.... address, source or destination ..00.... B mem[B,C] ..01.... D mem[D,E] ..11.... nn mem[mem[PC++]] (address16) STAX->STA, LDAX->LDA 0sdddsss opcode operation MOV destination = source "MOVe" ..ddd... destination ..000... B, ..001... C, ..010... D, ..011... E, ..100... H, ..101... L, ..110... M, mem[H,L] ..111... A, .1...sss source .1...000 B .1...001 C .1...010 D .1...011 E .1...100 H .1...101 L .1...110 M mem[H,L] (not with MOV M, (HLT is there!)) .1...111 A .0...110 n mem[PC+] (immediate8) MOV->MVI load/store/register 16bit 00dd0001 opcode operation ........ LXI ,nn destination = mem[PC++] (address16) "LoaD eXtend Immed" ..dd.... destination ..00.... B B,C ..01.... D D,E ..10.... H H,L ..11.... SP SP 0010o010 ....o... opcode operation ....0... SHLD mem[mem[PC++]] = HL (address16) "STore HL Direct" ....1... LHLD HL = mem[mem[PC++]] (address16) "LoaD HL Direct" oooooooo opcode operation 11111001 SPHL SP = HL "StackPointer set to HL" stack push/pop 11aa0o01 .....o.. opcode operation (push pre-decr, pop post-incr) .....0.. POP destination = mem[SP++] "POP" .....1.. PUSH mem[--SP] = source "PUSH" ..aa.... address, source or destination ..00.... B B,C ..01.... D D,E ..10.... H H,L ..11.... PSW A,F exchange 16bit oooooooo opcode operation 11100011 XTHL mem[SP] <=> HL "eXchange stack Top and HL" 11101011 XCHG DE <=> HL "eXCHanGe" input and output 1101o011 ....o... opcode operation ....0... OUT n,A io[n] = A "OUTput" ....1... IN A,n A = io[n] "INput" other specialised data transfer 001o0000 (only in 8085) ...o.... opcode operation ...0.... RIM IM = A "Read Interrupt Mask" ...1.... SIM A = IM "Set Interrupt Mask" jumps/subroutines and reset/interrupts oooooooo opcode operation 00000000 NOP do nothing "No OPeration" 01110110 HLT NOP until RESET/INT (opcode would be MOV M,M!) "HaLT processor" 11000011 JMP nn PC = mem[PC++] (address16) "JuMP" 11001001 RET PC = mem[SP++] "RETurn from subroutine" 11001101 CALL nn mem[--SP] = PC; PC = mem[PC++] (address16) "CALL subroutine" 11101001 PCHL PC = HL "ProgramCounter set to HL" oooooooo opcode operation 11aaa111 RST mem[--SP] = PC "ReSTart" PC = 0(bit15..6),aaa(bit5..3),0(bit2..0) ..aaa... number restart address ..000... 0 0000 ..001... 1 0008 ..010... 2 0010 ..011... 3 0018 ..100... 4 0020 ..101... 5 0028 ..110... 6 0030 ..111... 7 0038 ---- pin RESET IFF = 0; PC = 0000 "RESET" ---- pin INTR IFF = 0; next instr from extern (usually RST) "INTeRrupt" ---- pin RST5.5 IFF = 0; PC = 002C (only in 8085) "ReSTart 5.5" ---- pin RST6.5 IFF = 0; PC = 0034 (only in 8085) "ReSTart 6.5" ---- pin RST7.5 IFF = 0; PC = 003C (only in 8085) "ReSTart 7.5" ---- pin TRAP ??? (purpose not known to me) (only in 8085) "TRAP" branches/conditionals 11cccoo0 oo...ooo opcode operation 11...000 Rcc if condition then PC = mem[SP++] "Return *" 11...010 Jcc nn if condition then PC = mem[PC++] (address16) "Jump *" 11...100 Ccc nn if condition then mem[--SP] = PC; PC = mem[PC++] "Call *" ..ccc... cc condition ..000... NZ Z = 0 "No Zero" ..001... Z Z = 1 "Zero" ..010... NC C = 0 "No Carry" ..011... C C = 1 "Carry" ..100... PO P = 0 "Parity Odd" ..101... PE P = 1 "Parity Even" ..110... P S = 0 "Plus" ..111... M S = 1 "Minus" flags 0011o111 ....o... opcode operation ....0... STC FlagC = 1; FlagsAN,A=0,N=0 "SeT Carry flag" ....1... CMC FlagC = NOT FlagC FlagsAN,A=?,N=0 "CompleMent Carry flag" 1111o011 ....o... opcode operation ....0... DI IFF = 0 "Disable Interupt" ....1... EI IFF = 1 "Enable Interrupt" Instruction Code List: ---------------------- (full machine code bytes, in order: opcode number) 00 NOP -- - 20 RIM 30 SIM 01nnnn LXI B,nn 11nnnn LXI D,nn 21nnnn LXI H,nn 31nnnn LXI SP,nn 02 STAX B 12 STAX D 22nnnn SHLD nn 32nnnn STA nn 03 INX B 13 INX D 23 INX H 33 INX SP 04 INR B 14 INR D 24 INR H 34 INR M 05 DCR B 15 DCR D 25 DCR H 35 DCR M 06nn MVI B,n 16nn MVI D,n 26nn MVI H,n 36nn MVI M,n 07 RLC 17 RAL 27 DAA 37 STC -- - -- - -- - -- - 09 DAD B 19 DAD D 29 DAD H 39 DAD SP 0A LDAX B 1A LDAX D 2Annnn LHLD nn 3Annnn LDA nn 0B DCX B 1B DCX D 2B DCX H 3B DCX SP 0C INR C 1C INR E 2C INR L 3C INR A 0D DCR C 1D DCR E 2D DCR L 3D DCR A 0Enn MVI C,n 1Enn MVI E,n 2Enn MVI L,n 3Enn MVI A,n 0F RRC 1F RAR 2F CMA 3F CMC 20|30: unused in 8080, RIM and SIM only in 8085 40 MOV B,B 50 MOV D,B 60 MOV H,B 70 MOV M,B 41 MOV B,C 51 MOV D,C 61 MOV H,C 71 MOV M,C 42 MOV B,D 52 MOV D,D 62 MOV H,D 72 MOV M,D 43 MOV B,E 53 MOV D,E 63 MOV H,E 73 MOV M,E 44 MOV B,H 54 MOV D,H 64 MOV H,H 74 MOV M,H 45 MOV B,L 55 MOV D,L 65 MOV H,L 75 MOV M,L 46 MOV B,M 56 MOV D,M 66 MOV H,M 76 HLT 47 MOV B,A 57 MOV D,A 67 MOV H,A 77 MOV M,A 48 MOV C,B 58 MOV E,B 68 MOV L,B 78 MOV A,B 49 MOV C,C 59 MOV E,C 69 MOV L,C 79 MOV A,C 4A MOV C,D 5A MOV E,D 6A MOV L,D 7A MOV A,D 4B MOV C,E 5B MOV E,E 6B MOV L,E 7B MOV A,E 4C MOV C,H 5C MOV E,H 6C MOV L,H 7C MOV A,H 4D MOV C,L 5D MOV E,L 6D MOV L,L 7D MOV A,L 4E MOV C,M 5E MOV E,M 6E MOV L,M 7E MOV A,M 4F MOV C,A 5F MOV E,A 6F MOV L,A 7F MOV A,A 40|49|52|5B|64|6D|7F: are all NOPs 76: would be MOV M,M (3 cycle NOP) but used for HLT 80 ADD B 90 SUB B A0 ANA B B0 ORA B 81 ADD C 91 SUB C A1 ANA C B1 ORA C 82 ADD D 92 SUB D A2 ANA D B2 ORA D 83 ADD E 93 SUB E A3 ANA E B3 ORA E 84 ADD H 94 SUB H A4 ANA H B4 ORA H 85 ADD L 95 SUB L A5 ANA L B5 ORA L 86 ADD M 96 SUB M A6 ANA M B6 ORA M 87 ADD A 97 SUB A A7 ANA A B7 ORA A 88 ADC B 98 SBB B A8 XRA B B8 CMP B 89 ADC C 99 SBB C A9 XRA C B9 CMP C 8A ADC D 9A SBB D AA XRA D BA CMP D 8B ADC E 9B SBB E AB XRA E BB CMP E 8C ADC H 9C SBB H AC XRA H BC CMP H 8D ADC L 9D SBB L AD XRA L BD CMP L 8E ADC M 9E SBB M AE XRA M BE CMP M 8F ADC A 9F SBB A AF XRA A BF CMP A C0 RNZ D0 RNC E0 RPO F0 RP C1 POP B D1 POP D E1 POP H F1 POP PSW C2nnnn JNZ nn D2nnnn JNC nn E2nnnn JPO nn F2nnnn JP nn C3nnnn JMP nn D3nn OUT n E3 XTHL F3 DI C4nnnn CNZ nn D4nnnn CNC nn E4nnnn CPO nn F4nnnn CP nn C5 PUSH B D5 PUSH D E5 PUSH H F5 PUSH PSW C6nn ADI n D6nn SUI n E6nn ANI n F6nn ORI n C7 RST 0 D7 RST 2 E7 RST 4 F7 RST 6 C8 RZ D8 RC E8 RPE F8 RM C9 RET -- - E9 PCHL F9 SPHL CAnnnn JZ nn DAnnnn JC nn EAnnnn JPE nn FAnnnn JM nn -- - DBnn IN n EB XCHG FB EI CCnnnn CZ nn DCnnnn CC nn ECnnnn CPE nn FCnnnn CM nn CDnnnn CALL nn -- - -- - -- - CEnn ACI n DEnn SBI n EEnn XRI n FEnn CPI n CF RST 1 DF RST 3 EF RST 5 FF RST 7 Instruction Code Table: ----------------------- (only opcodes, in order: ver: bit7..6/5..3, hor: bit2..0) + 00 01 02 03 04 05 06 07 00 NOP LXI B, STAX B INX B INR B DCR B MVI B, RLC 08 - DAD B LDAX B DCX B INR C DCR C MVI C, RRC 10 - LXI D, STAX D INX D INR D DCR D MVI D, RAL 18 - DAD D LDAX D DCX D INR E DCR E MVI E, RAR 20 RIM LXI H, SHLD INX H INR H DCR H MVI H, DAA 28 - DAD H LHLD DCX H INR L DCR L MVI L, CMA 30 SIM LXI SP, STA INX SP INR M DCR M MVI M, STC 38 - DAD SP LDA DCX SP INR A DCR A MVI A, CMC 40 MOV B,B MOV B,C MOV B,D MOV B,E MOV B,H MOV B,L MOV B,M MOV B,A 48 MOV C,B MOV C,C MOV C,D MOV C,E MOV C,H MOV C,L MOV C,M MOV C,A 50 MOV D,B MOV D,C MOV D,D MOV D,E MOV D,H MOV D,L MOV D,M MOV D,A 58 MOV E,B MOV E,C MOV E,D MOV E,E MOV E,H MOV E,L MOV E,M MOV E,A 60 MOV H,B MOV H,C MOV H,D MOV H,E MOV H,H MOV H,L MOV H,M MOV H,A 68 MOV L,B MOV L,C MOV L,D MOV L,E MOV L,H MOV L,L MOV L,M MOV L,A 70 MOV M,B MOV M,C MOV M,D MOV M,E MOV M,H MOV M,L HLT MOV M,A 78 MOV A,B MOV A,C MOV A,D MOV A,E MOV A,H MOV A,L MOV A,M MOV A,A 80 ADD B ADD C ADD D ADD E ADD H ADD L ADD M ADD A 88 ADC B ADC C ADC D ADC E ADC H ADC L ADC M ADC A 90 SUB B SUB C SUB D SUB E SUB H SUB L SUB M SUB A 98 SBB B SBB C SBB D SBB E SBB H SBB L SBB M SBB A A0 ANA B ANA C ANA D ANA E ANA H ANA L ANA M ANA A A8 XRA B XRA C XRA D XRA E XRA H XRA L XRA M XRA A B0 ORA B ORA C ORA D ORA E ORA H ORA L ORA M ORA A B8 CMP B CMP C CMP D CMP E CMP H CMP L CMP M CMP A C0 RNZ POP B JNZ JMP CNZ PUSH B ADI RST 0 C8 RZ RET JZ - CZ CALL ACI RST 1 D0 RNC POP D JNC OUT CNC PUSH D SUI RST 2 D8 RC - JC IN CC - SBI RST 3 E0 RPO POP H JPO XTHL CPO PUSH H ANI RST 4 E8 RPE PCHL JPE XCHG CPE - XRI RST 5 F0 RP POP PSW JP DI CP PUSH PSW ORI RST 6 F8 RM SPHL JM EI CM - CPI RST 7