8051 Instruction Set (including 8052/54/58 extensions) author Neil Franklin, last modification 2008.04.30 Basics: ------- All numbers and bit patterns in this file are usually given in hex, seldom in binary, never in decimal or octal. Sources for this data: ---------------------- 1. PDF with scanned in copy of multiple Intel MCS 51 Manuals, from ftp://download.intel.com/design/mcs51/manuals/27238302.pdf . Very unlikely to contain errors. Of course errors of my own are to be expected. Processor Registers: -------------------- (in order: data, address, pc, flags, auxillary) A 8bit Accumulator (also SFR E0) R0 R1 .. R7 8bit General Purpose Registers (at 00..07 or 08..0F or 10..17 or 18..1F of data memory) B 8bit Second Accumulator (only for MUL and DIV) (SFR F0) SP 8bit Stack Pointer (SFR 81) (push pre-increment(!), pop post-decrement(!)) (must be in the 128+28bytes indirect data memory) DPTR 16bit Data Pointer (= DPH+DPL merged) (SFR 83 and 82) PC 16bit Program Counter (no SFR) PSW 8bit Processor Status Word (= flags) (SFR D0) PCON 8bit Power Control (SFR 87) IO Device Registers: -------------------- IE 8bit Interrupt Enable (SFR A8) IP 8bit Interrupt Priority (SFR B8) P0 P1 P2 P3 8bit I/O Ports 4*8 pins (SFR 80 90 A0 B0) TMOD 8bit Timer/Counter Mode Control (SFR 89) TCON 8bit Timer/Counter Control (SFR 88) T2CON 8bit Timer/Counter 2 Control (SFR C8) (only in 8052/54/58) TH0+TL0 16bit Timer/Counter 0 (= TH0+TL0 merged) (SFR 8C and 8A) TH1+TL1 16bit Timer/Counter 1 (= TH1+TL1 merged) (SFR 8D and 8B) TH2+TL2 16bit Timer/Counter 2 (= TH2+TL2 merged) (SFR CD and CC) (only in 8052/54/58) RCAP2H+RCAP2L 16bit Timer/Counter 2 Capture (SFR CB and CA) (only in 8052/54/58) SCON 8bit Serial Control (SFR 98) SBUF 8bit Serial Data Buffer (SFR 99) Processor Status Word, Flags: ----------------------------- (in order: from MSB/7 to LSB/0) CY Carry Flag (arithmetic result carry bit7->"bit8" & 1bit Accumulator) AC Auxillary Carry (arithmetic result carry bit3->bit4, used only by DA A) F0 Flag 0 (general purpose status flag) RS1 Register Select (working register bank switch) RS0 " (if 00: 00..07, 01: 08..0F, 10: 10..17, 11: 18..1F) OV Overflow Flag (arithmetic result carry bit6->bit7) - User Definable (no fixed purpose) P Parity (parity of accumulator) General policy is: - arithmetic: set all CY OV AC except MUL/DIV which set OV and clear CY, and DA which only sets CY - shift/rotate: set CY - bit stuff: set CY (CY is used as 1bit Accumulator) - everything else: leave all flags unchanged Interrupt Enable: ----------------- (in order: from MSB/7 to LSB/0) EA Enable All (1 enables only what is enabled below) - - ET2 Enable Timer 2 (1 enables timer 2 overflow) (only in 8052/54/58) ES Enable Serial Port (1 enables serial) ET1 Enable Timer 1 (1 enables timer 1 overflow) EX1 Enable External 1 (1 enables int1 pin) ET0 Enable Timer 0 (1 enables timer 0 overflow) EX0 Enable External 0 (1 enables int0 pin) Interrupt Priority: ------------------- (in order: from MSB/7 to LSB/0) - - - - PT2 Priority Timer 2 (1 high priority) (only in 8052/54/58) PS Priority Serial Port (1 high priority) PT1 Priority Timer 1 (1 high priority) PX1 Priority External 1 (1 high priority) PT0 Priority Timer 0 (1 high priority) PX0 Priority External 0 (1 high priority) Interrupt Priority High: ------------------------ Same as Interrupt Priority, but provides 2nd more significant bit for 4 levels (only in 8052/54/58) Power Control: -------------- (in order: from MSB/7 to LSB/0) SMOD Serial Mode (double baud rate) - - - - - - GF1 General Flag (no fixed purpose) GF0 General Flag (no fixed purpose) PD Power Down (freeze entire chip, high prio) (only in CHMOS versions) IDL Idle Mode (halt processor, low prio) (only in CHMOS versions) Special Function Registers: --------------------------- (in order: SFR grid) + 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 80 P0 SP DPL DPH - - - PCON TCON TMOD TL0 TL1 TH0 TH1 - - 90 P1 - - - - - - - SCON SBUF - - - - - - A0 P2 - - - - - - - IE - - - - - - - B0 P3 - - - - - - IPH IP - - - - - - - C0 - - - - - - - - T2CON - RCAP2L RCAP2H TL2 TH2 - - D0 PSW - - - - - - - - - - - - - - - E0 ACC - - - - - - - - - - - - - - - F0 B - - - - - - - - - - - - - - - B7/IPH, C8/T2CON, CA+CB/RCAP2L+RCAP2H, CC+CD/TL2+H2: only in 8052/54/58 Memory: ------- Program memory 64k*8bit (16bit address space) on chip: 4k ROM/EPROM (8051/8751) or 8k ROM/EPROM (8052/8752) or 16k ROM/EPROM (8054/8754) or 32k ROM/EPROM (8058/8758) or none at all (8031/8032, differ only in data memory) external: rest of 64k, borrowing port P0+P2 pins automatically goes external if instruction fetch at address too high if pin /EA=0 the internal memory is disabled, always goes external Data memory direct+indirect 128*8bit (7bit address space, 00..7F) on chip: 128 (all variants) no external: allways full 128 on chip 4sets of 8*8bit (00..07, 08..0F, 10..17, 18..1F) of these are 8 registers 16*8bit (20..2F) of these are 128 addressable bits (00.0..0F.7) Special Function Regs (SFRs) direct-only 128*8bit (7bit address space, 80..FF) 16*8bit (80/88/../F8) of these are 128 addressable bits (10.0..1F.7) Data memory indirect-only further 128*8bit (7bit address space, 80..FF) on chip: 0 (8051/8751/8031) or 128 (8052/8752, 8054/8754, 8058/8758, 8032) no external: allways full 128 on chip or rest unusable no growth space in main data memory addressing ist most serious misfeature forces use of external memory, chip costs, pin losses, for >256*8bit External Data memory 256*8bit or 64k*8bit (8bit or 16bit address space) borrowing port P0 pins (MOVX @R0 or @R1) or P0+P2 pins (MOVX @DPTR) for MOVX @R0 or @R1 use port P2 for bank switch up to 64k can be mapped over external program SRAM memory, gives writable programs Addressing Modes, in Assembler Syntax: -------------------------------------- (in order: reg, immediate, address, reg indirect, pc) A accumulator R0 R1 .. R7 register DPTR data pointer register #dd immediate8 #dddd immediate16 (only MOV DPTR,# instr) aa short-address8 (only data memory (00..7F) and SFRs (80..FF)) bb bit-address5+3 (only data (00.0..0F.7) and SFRs (10.0..1F.7)) @R0 @R1 register indirect (only for data memory (all 00..FF)) -nameless- stack pointer indirect decrement/increment (only PUSH/POP) @DPTR data pointer indirect (only for program or extern data memory) rr PC + offset8 (-128..+127) (only SJMP/J*/CJNE/DJNZ) (a)aa absolute-address11 (current page group) (only AJMP/ACALL instr) llll long-address16 (only LJMP/LCALL instr) @A accumulator indirect (only for program memory tables) Instruction Formats, in Machine Code Bytes: ------------------------------------------- (in order: simple, immediate, register, memory, bit, jump, condit) oo opcode8 oodd opcode8 immediate8 oodddd opcode8 immediate-low8 imm-high8 (= little endian) (only MOV DPTR) or opcode5+reg-address3 ordd opcode5+reg-address3 immediate8 or opcode7+indir-reg-address3 ordd opcode7+indir-reg-address3 immediate8 ooaa opcode8 datamem-or-SFR-address8 ooaadd opcode8 datamem-or-SFR-address8 immediate8 ooaaaa opcode8 source-datamem-or-SFR-addr8 dest-data-mem-or-SFR-addr8 oobb opcode8 bitaddr-datamem-or-SFR-address5+bitindex3 aoaa progmem-address-high3+opcode5 progmem-address-low8 (only AJMP/ACALL) oollll opcode8 progmem-address-high8 progmem-address-low8 (= big endian) oorr opcode8 offset8 (only SJMP) corr condition3+opcode5 offset8 (only Jcc) cobbrr condition3+opcode5 bitaddr-dmem-o-S-addr5+bitindex3 offs8 (only Jcc) oorr opcode5+reg-address3 offset8 (only DJNZ) oossrr opcode5+reg-address3 data-memory-or-SFR-address8 offset8 (only DJNZ) ooddrr opcode8 immediate8 offset8 (only CJNE) orddrr opcode5+reg-address3 immediate8 offset8 (only CJNE) orddrr opcode7+indir-reg-address3 immediate8 offset8 (only CJNE) ooaarr opcode8 data-memory-or-SFR-address8 offset8 (only CJNE) Instruction Bit Patterns and Operations: ---------------------------------------- (in order: functional grouping: arithmetic, data transfers, jumps, auxillary) arithmetic/logic and load oooossss oooo.... opcode operation 0010.... ADD A, A = A + source; FlagsCY,AC,OV "ADD" 0011.... ADDC A, A = A + source + FlagCY; FlagsCY,AC,OV "ADD with Carry" 0100.... ORL A, A = A bitwise-OR source "OR Logical" 0101.... ANL A, A = A bitwise-AND source "ANd Logical" 0110.... XRL A, A = A bitwise-excl-OR source "eXclusive oR Logical" 1000.... MOV aa, mem[progmem[PC+]] = source "MOVe" 1001.... SUBB A, A = A - source - FlagCY; FlagsCY,AC,OV "SUBtract w Borrow" 1110.... MOV A, A = source "MOVe" ....ssss source ....0100 #dd progmem[PC+] (immediate8) (not with MOV aa, as duplicate for MOV ,#dd with aa) (not with MOV A, as duplicate for MOV ,#dd with A) ....0101 aa mem[progmem[PC+]] (address8) (MOV A, with aa = ACC (SFR of A) is not allowed) ....0110 @R0 mem[R0] ....0111 @R1 mem[R1] ....1000 R0 ....1001 R1 ....1010 R2 ....1011 R3 ....1100 R4 ....1101 R5 ....1110 R6 ....1111 R7 logic to memory oooossss oooo.... opcode operation 0100.... ORL aa, mem[progmem[PC+]] = mem[progmem[PC]] bitwise-OR source "OR Logical" 0101.... ANL aa, mem[progmem[PC+]] = mem[progmem[PC]] bitwise-AND source "ANd Logical" 0110.... XRL aa, mem[progmem[PC+]] = mem[progmem[PC]] bitwise-excl-OR source "eXcl oR Logic" ....ssss source ....0010 A ....0011 #dd progmem[PC+] (immediate8) increment/decrement/set memory and exchange/store oooodddd oooo.... opcode operation 0000.... INC destination = destination + 1 "INCrement" 0001.... DEC destination = destination - 1 "DECrement" 0111.... MOV ,#dd destination = progmem[PC+] (immediate8) "MOVe" 1010.... MOV ,aa destination = mem[progmem[PC+]] (address8) "MOVe" 1100.... XCH A, destination <=> A "eXCHange" 1111.... MOV ,A destination = A "MOVe" ....ssss destination ....0100 A (not with MOV ,aa as duplicate of MOV A, with aa) (not with XCH A, or MOV ,A as senseless, are NOPs) ....0101 aa mem[progmem[PC+]] (address8) (not with MOV ,aa as duplicate of MOV aa, with aa) ....0110 @R0 mem[R0] ....0111 @R1 mem[R1] ....1000 R0 ....1001 R1 ....1010 R2 ....1011 R3 ....1100 R4 ....1101 R5 ....1110 R6 ....1111 R7 shift/rotate/swap oooo0011 oooo.... opcode operation 0000.... RR A A = A(bit0,7..1) "Rotate acc Right" 0001.... RRC A A,FlagCY = FlagCY,A "Rotate acc Right through Carry" 0010.... RL A A = A(bit6..0,7) "Rotate acc Left" 0011.... RLC A FlagCY,A = A,FlagCY "Rotate acc Left through Carry" oooooooo opcode operation 11000100 SWAP A A = A(bit3..0,7..4) "SWAP nibbles" oooooood ooooooo. opcode operation 1101011. XCHD ,A dest(bit3..0) = A(bit3..0) A(bit3..0) = dest(bit3..0) "eXCHange Digit" .......d destination .......0 @R0 mem[R0] .......1 @R1 mem[R1] bit logic and load oooooooo opcode operation 01110010 ORL C,bb.b C = C OR mem[progmem[PC+]]-bit-b "OR Logical" 10000010 ANL C,bb.b C = C AND mem[progmem[PC+]]-bit-b "ANd Logical" 10100000 ORL C,/bb.b C = C OR NOT mem[progmem[PC+]]-bit-b "OR Logical" 10100010 MOV C,bb.b C = mem[progmem[PC+]]-bit-b "MOVe" 10110000 ANL C,/bb.b C = C AND NOT mem[progmem[PC+]]-bit-b "ANd Logical" bit logic to memory and store oooooooo opcode operation 10010010 MOV bb.b,C mem[progmem[PC+]]-bit-b = C "MOVe" 10110010 CPL bb.b mem[progmem[PC+]]-bit-b = NOT mem[progmem[PC]]-bit-b "ComPLement" 11000010 CLR bb.b mem[progmem[PC+]]-bit-b = 0 "CLeaR" 11010010 SETB bb.b mem[progmem[PC+]]-bit-b = 1 "SET Bit" other specialised arithmetic oooo0100 oooo.... opcode operation 1000.... DIV AB A = A/B; B = remainder(A/B); FlagCY=0;FlagOV=0 "DIVide" 1010.... MUL AB B(bit15..8),A(bit7..0) = A*B FlagCY=0; FlagOV=1 if B != 0 "MULtiply" 1101.... DA A if A(bit3..0) > 9 or FlagAC = 1 then A = A + 6; FlagCY if A(bit7..4) > 9 or FlagCY = 1 then A = A + 96; FlagCY "Decimal Adjust Accumulator" 1110.... CLR A A = 0 "CLear Accumulator" 1111.... CPL A A = bitwise-NOT A "ComPLement Accumulator" stack push/pop oooooooo opcode operation (push pre-incr(!), pop post-decr(!)) 11000000 PUSH mem[+SP] = mem[progmem[PC+]] "PUSH" 11010000 POP mem[progmem[PC+]] = mem[SP-] "POP" code/external memory oooooooo opcode operation 10000011 MOVC A,@A+PC A = progmem[PC+A] "MOVe Code memory" 10010011 MOVC A,@A+DPTR A = progmem[DPTR+A] "MOVe Code memory" ooooooaa oooooo.. opcode operation/direction 111000.. MOVX A, A = extmem[source] "MOVe eXternal memory" 111100.. MOVX ,A extmem[destination] = A "MOVe eXternal memory" ......aa address, source or destination ......00 @DPTR ......10 @R0 ......11 @R1 oooooooo opcode operation 10010000 MOV DPTR,#dddd DPT = progmem[PC++] (immediate16) "MOVe" 10100011 INC DPTR DPTR = DPTR + 1 "INCrement" jumps/subroutines and reset/interrupts oooooooo opcode operation 00000000 NOP do nothing "No OPeration" 00000010 LJMP llll PC = progmem[PC++] (address16) "Long JuMP" 00010010 LCALL llll mem[++SP] = PC PC = progmem[PC++] (address16) "Long CALL" 00100010 RET PC = mem[SP--] "RETurn" 00110010 RETI PC = mem[SP--] interrupt in progress = off "RETurn from Interrupt" 01110011 JMP @A+DPTR PC = DPTR+A "JuMP" 10000000 SJMP rr PC = PC+progmem[PC+] (offset8) "Short JuMP" aaaooooo ...ooooo opcode operation ...00001 AJMP PC = PC(bit15..11),progmem[PC+] (address11) "Absolute JuMP" ...10001 ACALL mem[++SP] = PC PC = PC(bit15..11),progmem[PC+] (address11) "Absolute CALL" aaa..... address bit10..8 (bit15..11 stay, bit7..0 from 2nd instr byte) 000..... 0aa 001..... 1aa 010..... 2aa 011..... 3aa 100..... 4aa 101..... 5aa 110..... 6aa 111..... 7aa ---- pin RESET PC = 0000; P0=FF; P1=FF; P2=FF; P3=FF; SP=07; SBUF=?? rest of SFRs=00 "RESET" --- flag IE0 mem[++SP] = PC; PC = 0003 interrupt in progress = on "external Interrupt Edge 0" --- flag TF0 mem[++SP] = PC; PC = 000B interrupt in progress = on "Timer overflowed Flag 0" --- flag IE1 mem[++SP] = PC; PC = 0013 interrupt in progress = on "external Interrupt Edge 0" --- flag TF1 mem[++SP] = PC; PC = 001B interrupt in progress = on "Timer overflowed Flag 1" -- flags TI OR RI mem[++SP] = PC; PC = 0023 interrupt in progress = on "Transmit Int | Recieve Int" -- flags TF2 OR EXF2 mem[++SP] = PC; PC = 002B interrupt in progress = on "Timer overf or ext Flag 2" branches/conditionals 0ccc0000 ....oooo opcode operation ....0000 Jcc rr if condition then PC = PC+progmem[PC+] (offset8) only JBC also does: if condition then bb.b = 0 "Jump cc" .ccc.... cc condition .001.... BC bb.b mem[progmem[PC+]]-bit-b = 1 "Bit is set and Clear bit" .010.... B bb.b mem[progmem[PC+]]-bit-b = 1 "Bit is set" .011.... NB bb.b mem[progmem[PC+]]-bit-b = 0 "Not Bit is set" .100.... C FlagCY = 1 "Carry is set" .101.... NC FlagCY = 0 "Not Carry is set" .110.... Z A = 0 "acc is Zero" .111.... NZ A != 1 "acc is Not Zero" oooodddd oooo.... opcode operation 1011.... CJNE ,rr if source != #dd then PC = PC+progmem[PC+] (offset8) FlagCY=1 if less "Compare and Jump in Not Equal" ....dddd source ....0100 A,#dd progmem[PC+] (immediate8) ....0101 A,aa mem[progmem[PC+]] (address8) (compare aa with A, not #dd, as no 3-operand aaddrr possible) ....0110 @R0,#dd mem[R0] , progmem[PC+] (immediate8) ....0111 @R1,#dd mem[R1] , progmem[PC+] (immediate8) ....1000 R0,#dd progmem[PC+] (immediate8) ....1001 R1,#dd progmem[PC+] (immediate8) ....1010 R2,#dd progmem[PC+] (immediate8) ....1011 R3,#dd progmem[PC+] (immediate8) ....1100 R4,#dd progmem[PC+] (immediate8) ....1101 R5,#dd progmem[PC+] (immediate8) ....1110 R6,#dd progmem[PC+] (immediate8) ....1111 R7,#dd progmem[PC+] (immediate8) oooodddd oooo.... opcode operation 1101.... DJNZ ,rr dest = dest - 1; "Decrement and Jump if Not Zero" if dest != 0 then PC = PC+progmem[PC+] (offset8) ....dddd destination ....0101 aa mem[progmem[PC+]] (address8) ....1000 R0 ....1001 R1 ....1010 R2 ....1011 R3 ....1100 R4 ....1101 R5 ....1110 R6 ....1111 R7 flags oooooooo opcode operation 10110011 CPL C FlagCY = NOT FlagCY "ComPLement Carry" 11000011 CLR C FlagCY = 0 "CLeaR Carry" 11010011 SETB C FlagCY = 1 "SET Bit Carry" Instruction Code List: ---------------------- (full machine code bytes, in order: opcode number) 00 NOP 10bbrr JBC b,r 20bbrr JB b,r 30bbrr JNB b,r 01aa AJMP 0a 11aa ACALL 0a 21aa AJMP 1a 31aa ACALL 1a 02llll LJMP ll 12llll LCALL ll 22 RET 32 RETI 03 RR A 13 RRC A 23 RL A 33 RLC A 04 INC A 14 DEC A 24dd ADD A,#d 34dd ADDC A,#d 05aa INC a 15aa DEC a 25aa ADD A,a 35aa ADDC A,a 06 INC @R0 16 DEC @R0 26 ADD A,@R0 36 ADDC A,@R0 07 INC @R1 17 DEC @R1 27 ADD A,@R1 37 ADDC A,@R1 08 INC R0 18 DEC R0 28 ADD A,R0 38 ADDC A,R0 09 INC R1 19 DEC R1 29 ADD A,R1 39 ADDC A,R1 0A INC R2 1A DEC R2 2A ADD A,R2 3A ADDC A,R2 0B INC R3 1B DEC R3 2B ADD A,R3 3B ADDC A,R3 0C INC R4 1C DEC R4 2C ADD A,R4 3C ADDC A,R4 0D INC R5 1D DEC R5 2D ADD A,R5 3D ADDC A,R5 0E INC R6 1E DEC R6 2E ADD A,R6 3E ADDC A,R6 0F INC R7 1F DEC R7 2F ADD A,R7 3F ADDC A,R7 40rr JC r 50rr JNC r 60rr JZ r 70rr JNZ r 41aa AJMP 2a 51aa ACALL 2a 61aa AJMP 3a 71aa ACALL 3a 42aa ORL a,A 52aa ANL a,A 62aa XRL a,A 72bb ORL C,b 43aadd ORL a,#d 53aadd ANL a,#d 63aadd XRL a,#d 73 JMP @A+DPTR 44dd ORL A,#d 54dd ANL A,#d 64dd XRL A,#d 74dd MOV A,#d 45aa ORL A,a 55aa ANL A,a 65aa XRL A,a 75aadd MOV aa,#d 46 ORL A,@R0 56 ANL A,@R0 66 XRL A,@R0 76dd MOV @R0,#d 47 ORL A,@R1 57 ANL A,@R1 67 XRL A,#R1 77dd MOV @R1,#d 48 ORL A,R0 58 ANL A,R0 68 XRL A,R0 78dd MOV R0,#d 49 ORL A,R1 59 ANL A,R1 69 XRL A,R1 79dd MOV R1,#d 4A ORL A,R2 5A ANL A,R2 6A XRL A,R2 7Add MOV R2,#d 4B ORL A,R3 5B ANL A,R3 6B XRL A,R3 7Bdd MOV R3,#d 4C ORL A,R4 5C ANL A,R4 6C XRL A,R4 7Cdd MOV R4,#d 4D ORL A,R5 5D ANL A,R5 6D XRL A,R5 7Ddd MOV R5,#d 4E ORL A,R6 5E ANL A,R6 6E XRL A,R6 7Edd MOV R6,#d 4F ORL A,R7 5F ANL A,R7 6F XRL A,R7 7Fdd MOV R7,#d 80rr SJMP r 90dddd MOV DPTR,#dd A0bb ORL C,/b B0bb ANL C,/b 81aa AJMP 4a 91aa ACALL 4a A1aa AJMP 5a B1aa ACALL 5a 82bb ANL C,b 92bb MOV b,C A2bb MOV C,b B2bb CPL b 83 MOVC A,@A+PC 93 MOVC A,@A+DP A3 INC DPTR B3 CPL C 84 DIV AB 94dd SUBB A,#d A4 MUL AB B4ddrr CJNE A,#d,r 85aaaa MOV a,a 95aa SUBB A,a -- - B5aarr CJNE A,a,r 86aa MOV a,@R0 96 SUBB A,@R0 A6aa MOV @R0,a B6ddrr CJNE @R0,#dr 87aa MOV a,@R1 97 SUBB A,@R1 A7aa MOV @R1,a B7ddrr CJNE @R1,#dr 88aa MOV a,R0 98 SUBB A,R0 A8aa MOV R0,a B8ddrr CJNE R0,#d,r 89aa MOV a,R1 99 SUBB A,R1 A9aa MOV R1,a B9ddrr CJNE R1,#d,r 8Aaa MOV a,R2 9A SUBB A,R2 AAaa MOV R2,a BAddrr CJNE R2,#d,r 8Baa MOV a,R3 9B SUBB A,R3 ABaa MOV R3,a BBddrr CJNE R3,#d,r 8Caa MOV a,R4 9C SUBB A,R4 ACaa MOV R4,a BCddrr CJNE R4,#d,r 8Daa MOV a,R5 9D SUBB A,R5 ADaa MOV R5,a BDddrr CJNE R5,#d,r 8Eaa MOV a,R6 9E SUBB A,R6 AEaa MOV R6,a BEddrr CJNE R6,#d,r 8Faa MOV a,R7 9F SUBB A,R7 AFaa MOV R7,a BFddrr CJNE R7,#d,r 84: would be MOV a,#d an duplicate of 75, so recycled for DIV AB 93: should be in full A,@A+DPTR but shortened because of lack of space A4: would be MOV #d,a , senseless, so recycled for MUL AB A5: would be an duplicate of 85, senseless C0aa PUSH a D0aa POP a E0 MOVX A,@DPTR F0 MOVX @DPTR,A C1aa AJMP 6a D1aa ACALL 6a E1aa AJMP 7a F1aa ACALL 7a C2bb CLR b D2bb SETB b E2 MOVX A,@R0 F2 MOVX @R0,A C3 CLR C D3 SETB C E3 MOVX A,@R1 F3 MOVX @R1,A C4 SWAP A D4 DA A E4 CLR A F4 CPL A C5aa XCH A,a D5aarr DJNZ a,r E5aa MOV A,a F5aa MOV a,A C6 XCH A,@R0 D6 XCHD A,@R0 E6 MOV A,@R0 F6 MOV @R0,A C7 XCH A,@R1 D7 XCHD A,@R1 E7 MOV A,@R1 F7 MOV @R1,A C8 XCH A,R0 D8rr DJNZ R0,r E8 MOV A,R0 F8 MOV R0,A C9 XCH A,R1 D9rr DJNZ R1,r E9 MOV A,R1 F9 MOV R1,A CA XCH A,R2 DArr DJNZ R2,r EA MOV A,R2 FA MOV R2,A CB XCH A,R3 DBrr DJNZ R3,r EB MOV A,R3 FB MOV R3,A CC XCH A,R4 DCrr DJNZ R4,r EC MOV A,R4 FC MOV R4,A CD XCH A,R5 DDrr DJNZ R5,r ED MOV A,R5 FD MOV R5,A CE XCH A,R6 DErr DJNZ R6,r EE MOV A,R6 FE MOV R6,A CF XCH A,R7 DFrr DJNZ R7,r EF MOV A,R7 FF MOV R7,A Instruction Code Table: ----------------------- (only opcodes, in order: ver: bit7..4/3, hor: bit2..0) + 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 NOP AJMP 0a LJMP RR A INC A INC INC @R0 INC @R1 INC R0 INC R1 INC R2 INC R3 INC R4 INC R5 INC R6 INC R7 10 JBC ACALL 0a LCAL RRC A DEC A DEC DEC @R0 DEC @R1 DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 20 JB AJMP 1a RET RL A ADD A,# ADD A, ADD A,@R0ADD A,@R1 ADD A,R0 ADD A,R1 ADD A,R2 ADD A,R3 ADD A,R4 ADD A,R5 ADD A,R6 ADD A,R7 30 JNB ACALL 1a RETI RLC A ADDC A,# ADDC A, ADDC A,@0ADDC A,@1 ADDC A,R0ADDC A,R1ADDC A,R2ADDC A,R3ADDC A,R4ADDC A,R5ADDC A,R6ADDC A,R7 40 JC AJMP 2a ORL ,A ORL ,# ORL A,# ORL A, ORL A,@R0ORL A,@R1 ORL A,R0 ORL A,R1 ORL A,R2 ORL A,R3 ORL A,R4 ORL A,R5 ORL A,R6 ORL A,R7 50 JNC ACALL 2a ANL ,A ANL ,# ANL A,# ANL A, ANL A,@R0ANL A,@R1 ANL A,R0 ANL A,R1 ANL A,R2 ANL A,R3 ANL A,R4 ANL A,R5 ANL A,R6 ANL A,R7 60 JZ AJMP 3a XRL ,A XRL ,# XRL A,# XRL A, XRL A,@R0XRL A,@R1 XRL A,R0 XRL A,R1 XRL A,R2 XRL A,R3 XRL A,R4 XRL A,R5 XRL A,R6 XRL A,R7 70 JNZ ACALL 3a ORL C, JMP @A+DPMOV A,# MOV , MOV @R0, MOV @R1, MOV R0,# MOV R1,# MOV R2,# MOV R3,# MOV R4,# MOV R5,# MOV R6,# MOV R7,# 80 SJMP AJMP 4a ANL C, MOVC A,@PDIV AB MOV , MOV ,@R0 MOV ,@R1 MOV ,R0 MOV ,R1 MOV ,R2 MOV ,R3 MOV ,R4 MOV ,R5 MOV ,R6 MOV ,R7 90 MOV DPTR,ACALL 4a MOV ,C MOVC A,@DSUBB A, SUBB A, SUBB A,@0SUBB A,@1 SUBB A,R0SUBB A,R1SUBB A,R2SUBB A,R3SUBB A,R4SUBB A,R5SUBB A,R6SUBB A,R7 A0 ORL C,/ AJMP 5a MOV C, INC DPTR MUL AB - MOV @R0, MOV @R1, MOV R0, MOV R1, MOV R2, MOV R3, MOV R4, MOV R5, MOV R6, MOV R7, B0 ANL C,/ ACALL 5a CPL CPL C CJNE A, CJNE A, CJNE @0,,CJNE @1,, CJNE R0,,CJNE R1,,CJNE R2,,CJNE R3,,CJNE R4,,CJNE R5,,CJNE R6,,CJNE R7,, C0 PUSH AJMP 6a CLR CLR C SWAP A XCH A, XCH A,@R0XCH A,@1 XCH A,R0 XCH A,R1 XCH A,R2 XCH A,R3 XCH A,R4 XCH A,R5 XCH A,R6 XCH A,R7 D0 POP ACALL 6a SETB SETB C DA A DJNZ , XCHD A,@0XCHD A,@1 DJNZ R0, DJNZ R1, DJNZ R2, DJNZ R3, DJNZ R4, DJNZ R5, DJNZ R6, DJNZ R7, E0 MOVX A,@DAJMP 7a MOVX A,@0MOVX A,@1CLR A MOV A, MOV A,@R0MOV A,@R1 MOV A,R0 MOV A,R1 MOV A,R2 MOV A,R3 MOV A,R4 MOV A,R5 MOV A,R6 MOV A,R7 F0 MOVX @D,AACALL 7a MOVX @0,AMOVX @1,ACPL A MOV ,A MOV @R0,AMOV @R1,A MOV R0,A MOV R1,A MOV R2,A MOV R3,A MOV R4,A MOV R5,A MOV R6,A MOV R7,A