8048 Instruction Set author Neil Franklin, last modification 2008.04.30 Basics: ------- All numbers and bit patterns in this file are usually given in hex, seldom in binary, never in decimal or octal. Sources for this data: ---------------------- 1. PDF with manually generated "copy" of Intel MCS-48 Microcomputer Users Manual, from http://home.mnet-online.de/al/mcs-48/mcs-48.pdf . In the words of its author (in private email) "Quite likely to contain errors". He also remarks that the Intel original also has errors in it. Of course errors of my own are to be expected. Processor Registers: -------------------- (in order: data, address, pc, flags) A 8bit Accumulator R0 R1 .. R7 8bit General Purpose Registers (00..07 or 18..1F of data memory) PC 12bit Program Counter (no carry from bit10->bit11!) PSW 8bit Processor Status Word (= flags + stack pointer) IO Device Registers: -------------------- T 8bit Timer/Counter BUS P1 P2 8bit I/O Ports 3*8 pins P4 P5 P6 P7 4bit Expanded I/O Ports (using 8243 expander chip) borrowing P2(bit3..0) pins 8243s can be bank switched using P2(bit7..4) to /CS pins Processor Status Word, Flags and Stack Pointer: ----------------------------------------------- (in order: from MSB/7 to LSB/0) CY Carry (arithmetic result carry bit7->"bit8") AC Auxillary Carry (arithmetic result carry bit3->bit4, used only by DA A) F0 Flag 0 (user controlled flag 0) BS Bank Select Flag (working register bank switch, if 0: 00..07, if 1: 18..1F) 1 unused S2 Stack Pointer SP (stack can use only addr 08..17 of data memory, 8*2bytes) S1 " (push post-increment(!), pop pre-decrement(!)) S0 " (000 = 08+09, 001 = 0A+0B, 010 = 0C+0D ... 111 = 16+17) General policy is: - addition: set both CY and AC (but DA sets only CY) - shift/rotate: set CY - everything else: leave all flags unchanged Further Flags, not in Program Status Word: ------------------------------------------ F1 Flag 1 (user controlled flag 1) MB Memory Bank Flag (used as bit11 when CALL or JMP load PC) IF Interrupt Flag (0 enables INT pin) TCNTIF Timer/Counter Interrupt Flag (0 enables T/C interrupts) TF Timer/Counter Overflowed Flag (1 if has overflowed) IPF Interrupt in Progress Flag (1 in progress) Memory: ------- Program memory 4k*8bit (12bit address space) on chip: 1k ROM/EPROM (8048/8748), 2k ROM/EPROM (8049/8749) or 4k ROM (8050) or none at all (8035/8039/8040, differ only in data memory) external: rest of 4k, borrowing port BUS+P2(bit3..0) pins use (not automatically borrowed!) P2(bit7..4) for bank switch up to 64k automatically goes external if instruction fetch at address too high if pin EA=1 the internal memory is disabled, always goes external Data memory 256*8bit (8bit address space) on chip: 64 (8048/8748/8035) or 128 (8049/8749/8039) or 256 (8050/8040) no external: rest always unusable 2sets of 8*8bit (00..07, 18..1F) of these are the 8 registers 8*2*8bit (08..17) of these are the stack External Data memory 256*8bit (8bit address space) borrowing port BUS pins use (not automatically borrowed!) port P2(bit3..0) for bank switch up to 4k or even entire port P2(bit7..0) for bank switch up to 64k can be mapped over external program SRAM memory, gives writable programs Addressing Modes, in Assembler Syntax: -------------------------------------- (in order: reg, immediate, reg indirect, pc) A accumulator R0 R1 .. R7 register PSW program status word T timer register BUS P1 P2 input/output registers P4 P5 P6 P7 expanded input/output registers dd immediate8 @R0 @R1 register indirect (only for data memory) aa short-address8 (current page) (only J*/JB*/NJNZ instr) (a)aa extended-address11 (only JMP/CALL instr) @A accumulator indirect (only for program memory tables) Instruction Formats, in Machine Code Bytes: ------------------------------------------- (in order: simple, immediate, register, memory, in/out, jump, condit) oo opcode8 oodd opcode8 immediate8 or opcode5+reg-address3 or opcode7+indir-reg-address3 or opcode5+port-address3 aoaa progmem-address-high3+opcode5 progmem-address-low8 (only JMP/CALL) coaa condition4+opcode4 progmem-address8 (only Jcc instr) boaa bitindex3+opcode5 progmem-address8 (only JBb instr) oraa opcode5+reg-address3 progmem-address8 (only DJNZ instr) Instruction Bit Patterns and Operations: ---------------------------------------- (in order: functional grouping: arithmetic, data transfers, jumps, auxillary) arithmetic/logic and load A oooossss oooo.... opcode operation 0000.... ADD (only for dd source, why?) 0001.... ADDC (only for dd source, why?) 0010.... MOV A, (only for dd source, why?) 0100.... ORL A = A bitwise-OR source "OR Logical to acc" 0101.... ANL A = A bitwise-AND source "ANd Logical to acc" 0110.... ADD A = A + source; FlagsCY,AC "ADD to acc" 0111.... ADDC A = A + source + FlagCY; FlagsCY,AC "ADD to acc with Carry" 1101.... XRL A = A bitwise-excl-OR source "eXclusive oR Logical to acc" 1111.... MOV A, A = source "MOVe to acc" ....ssss source ....0000 @R0 mem[R0] ....0001 @R1 mem[R1] ....0011 dd mem[PC+] (immediate8) (special case ADD|ADDC|MOV, why?) ....1000 R0 ....1001 R1 ....1010 R2 ....1011 R3 ....1100 R4 ....1101 R5 ....1110 R6 ....1111 R7 increment/decrement and exchange/store/set memory oooodddd oooo.... opcode operation 0000.... DEC (only for A destination) 0001.... INC destination = destination + 1 "INCrement" 0010.... XCH ,A destination <=> A "eXCHange" 1010.... MOV ,A destination = A "MOVe from acc" 1011.... MOV ,dd destination = progmem[PC+] (immediate8) "MOVe immed data" 1100.... DEC destination = destination - 1 "DECrement" ....dddd destination ....0000 @R0 mem[R0] (missing for DEC, why?) ....0001 @R1 mem[R1] (missing for DEC, why?) ....0111 A (not for XCH or MOV) ....1000 R0 ....1001 R1 ....1010 R2 ....1011 R3 ....1100 R4 ....1101 R5 ....1110 R6 ....1111 R7 shift/rotate/swap oooooood ooooooo. opcode operation 0011000. XCHD ,A dest(bit3..0) = A(bit3..0) A(bit3..0) = dest(bit3..0) "eXCHange Digit" .......d destination .......0 @R0 mem[R0] .......1 @R1 mem[R1] oooooooo opcode operation 01000111 SWAP A A = A(bit3..0,7..4) "SWAP nibbles" oooo0111 oooo.... opcode operation 0110.... RRC A A,FlagCY = FlagCY,A "Rotate Right with Carry" 0111.... RR A A = A(bit0,7..1) "Rotate Right without carry" (RRC/RR carry/no-carry revers relative to both ADD/ADDC and RL/RLC) 1110.... RL A A = A(bit6..0,7) "Rotate Left without carry" 1111.... RLC A FlagCY,A = A,FlagCY "Rotate Left with Carry" other specialised arithmetic oooo0111 oooo.... opcode operation 0010.... CLR A A = 0 "CLeaR Acc" 0011.... CPL A A = bitwise-NOT A "ComPLement Acc" 0101.... DA A if A(bit3..0) > 9 or FlagAC = 1 then A = A + 6; FlagCY if A(bit7..4) > 9 or FlagCY = 1 then A = A + 96; FlagCY "Decimal Adjust Accumulator" external memory 100o000a ...o.... opcode operation/direction ...0.... MOVX A, A = extmem[source] "MOVe eXternal memory" ...1.... MOVX ,A extmem[destination] = A "MOVe eXternal memory" .......a address, source or destination .......0 @R0 extmem[R0] .......1 @R1 extmem[R1] input and output oooooooo opcode operation 00000010 OUTL BUS BUS = A; low strobe pin WR "OUTput Latch?" (why here, and not at 00111000?) 00001000 INS A,BUS A = BUS; low strobe on RD "INput Strobe" 10001000 ORL BUS,dd BUS = BUS bitwise-OR progmem[PC+] (immediate8) (only if OUTL since last ext mem access) "OR Logical" 10011000 ANL BUS,dd BUS = BUS bitwise-AND progmem[PC+] (immediate8) (only if OUTL since last ext mem access) "ANd Logical" oooo1ppp oooo.... opcode opration 0000.... IN A,Pp A = port p "INput" 0011.... OUTL Pp,A port p = A "OUTput Latch?" 1000.... ORL Pp,dd port p = port p bitwise-OR progmem[PC+] (immediate8) "OR Logical" 1001.... ANL Pp,dd port p = port p bitwise-AND progmem[PC+] (immediate8) "ANd Logical" .....ppp port .....001 1 .....010 2 oooo1ppp oooo.... opcode opration 0000.... MOVD A,Pp A(bit7..4) = 0; A(bit3..0) = port p "MOVe Digit" 0011.... MOVD Pp,A port p = A(bit3..0) "MOVe Digit" 1000.... ORLD Pp,A port p = port p bitwise-OR A(bit3..0) "OR Log Digit" 1001.... ANLD Pp,A port p = port p bitwise-AND A(bit3..0) "ANd Log Digit" .....ppp expanded port .....100 4 .....101 5 .....110 6 .....111 7 other specialised data transfer oooooooo opcode operation 01000010 MOV A,T A = T (timer) "MOVe from timer" 01100010 MOV T,A T = A (timer) "MOVe to timer" 10100011 MOVP A,@A A = progmem[PC(bit11..8),A] "MOVe from Prog memory" 11000111 MOV A,PSW A = PSW (program status word) "MOVe from prog stat" 11010111 MOV PSW,A PSW = A (program status word) "MOVe to prog stat" 11100011 MOVP3 A,@A A = progmem[0011(bit11..8),A] "MOVe from Prog mem 3xx" jumps/subroutines and reset/interrupts oooooooo opcode operation 00000000 NOP do nothing "No OPeration" 10110011 JMPP @A PC = PC(bit11..8),A "indirect JuMP within Page" 10000011 RET PC = mem[--SP] "RETurn" 10010011 RETR PSW(bit7..4),PC = mem[--SP] IPF = 0 (not in progress) "RETurn with prog stat Restore" aaaooooo ...ooooo opcode operation ...00101 JMP aaa PC = MBF(bit11),aaa(bit10..8),progmem[PC+] (address12) "JuMP" ...10101 CALL aaa mem[SP++] = PSW(bit7..4),PC; "CALL subroutine" PC = MBF(bit11),aaa(bit10..8),progmem[PC+] (address12) aaa..... addressbit10..8 000..... 0aa 001..... 1aa 010..... 2aa 011..... 3aa 100..... 4aa 101..... 5aa 110..... 6aa 111..... 7aa ---- pin RESET PC = 000; SP = 0; BS = 0; MBF = 0; P1 = FF; P2 = FF "RESET" IPF = IF = TCNTIF = 1 (disabled); stop counter/timer TF = 0; F0 = 0; F1 = 0; T0 CLK disabled ---- pin INT IPF = 1 (in progress); mem[SP++] = PSW(bit4..7),PC; PC = 003 "INTerrupt" --- flag TF IPF = 1 (in progress); "Timer Flag interrupt" mem[SP++] = PSW(bit4..7),PC; PC = 007 branches/conditionals ccccoooo ....oooo opcode operation ....0110 Jcc aa if condition then PC = PC(bit11..8),progmem[PC+] (address8) "Jump cc" only JTF also does: TF = 0 cccc.... cc condition 0001.... TF FlagTF = 1 "Timer/counter overflowed Flag" 0010.... NT0 PinT0 = 0 "Not Test0 pin" 0011.... T0 PinT0 = 1 "Test0 pin" 0100.... NT1 PinT1 = 0 "Not Test1 pin" 0101.... T1 PinT1 = 1 "Test1 pin" 0111.... F1 FlagF1 = 1 "user Flag 1" 1000.... NI PinINT = 0 (= interrupt triggered!) "Not Interrupt" 1001.... NZ A != 0 "Not Zero" 1011.... F0 FlagF0 = 1 "user Flag 0" 1100.... Z A = 0 "Zero" 1110.... NC FlagCY = 0 "Not Carry" 1111.... C FlagCY = 1 "Carry" bbbooooo ...ooooo opcode operation ...10010 JBb aa if A(bitb) = 1 then PC = PC(bit11..8),progmem[PC+] (addr8) "Jump Bit 0..7" bbb..... b = bit to test 000..... 0 001..... 1 010..... 2 011..... 3 100..... 4 101..... 5 110..... 6 111..... 7 oooodddd ooooo... opcode operation 11101... DJNZ ,aa dest = dest - 1; "Decrement and Jump if Not Zero" if dest != 0 then PC = PC(bit11..8),progmem[PC+] (addr8) .....ddd destination .....000 R0 .....001 R1 .....010 R2 .....011 R3 .....100 R4 .....101 R5 .....110 R6 .....111 R7 flags oooo0101 opcode operation 00000101 EN I FlagIF = 0 "Enable interrupt flipflop" 00010101 DIS I FlagIF = 1 "DISable interrupt flipflop" 00100101 EN TCNTI FlagTCNTIF = 0 "ENable timer/counter int flipflop" 00110101 DIS TCNTI FlagTCNTIF = 1 "DISable timer/counter int flipflop" 01000101 STRT CNT "STaRT counter/timer in counter mode" 01010101 STRT T "STaRT counter/timer in timer mode" 01100101 STOP TCNT "STOP counter/timer" 01110101 ENT0 CLK sysclock on T0 pin, disable only by reset "ENable T0" 10000101 CLR F0 FlagF0 = 0 "CLeaR user flag 0" 10010101 CPL F0 FlagF0 = NOT FlagF0 "ComPLement user flag 0" 10100101 CLR F1 FlagF1 = 0 "CLeaR user flag 1" 10110101 CPL F1 FlagF1 = NOT FlagF1 "ComPLement user flag 1" 11000101 SEL RB0 FagBS = 0 "SELect Register Bank 0" 11010101 SEL RB1 FlagBS = 1 "SELect Register Bank 1" 11100101 SEL MB0 FlagMB = 0 "SELect program Memory Bank 0" 11110101 SEL MB1 FlagMB = 1 "SELect program Memory Bank 1" oooo0111 opcode operation 10010111 CLR C FlagCY = 0 "CLeaR carry flag" 10100111 CPL C FlagCY = NOT FlagCY "ComPLement carry flag" Instruction Code List: ---------------------- (full machine code bytes, in order: opcode number) 00 NOP 10 INC @R0 20 XCH A,@R0 30 XCHD A,@R0 -- - 11 INC @R1 21 XCH A,@R1 31 XCHD A,@R1 02 OUTL BUS,A 12aa JB0 a -- - 32aa JB1 a 03dd ADD A,d 13dd ADDC A,d 23dd MOV A,d -- - 04aa JMP 0a 14aa CALL 0a 24aa JMP 1a 34aa CALL 1a 05 EN I 15 DIS I 25 EN TCNTI 35 DIS TCNTI -- - 16aa JTF a 26aa JNT0 a 36aa JT0 a 07 DEC A 17 INC A 27 CLR A 37 CPL A 08 INS A,BUS 18 INC R0 28 XCH A,R0 -- - 09 IN A,P1 19 INC R1 29 XCH A,R1 39 OUTL P1,A 0A IN A,P2 1A INC R2 2A XCH A,R2 3A OUTL P2,A -- - 1B INC R3 2B XCH A,R3 -- - 0C MOVD A,P4 1C INC R4 2C XCH A,R4 3C MOVD P4,A 0D MOVD A,P5 1D INC R5 2D XCH A,R5 3D MOVD P5,A 0E MOVD A,P6 1E INC R6 2E XCH A,R6 3E MOVD P6,A 0F MOVD A,P7 1F INC R7 2F XCH A,R7 3F MOVD P7,A 02: would better fit in at the unused 38 03|13|23: would better fit in at the unused 63|73|F3 0B|3B: would be port 3, non-existant hardware 38: would be OUTL BUS,A , why missing? 40 ORL A,@R0 50 ANL A,@R0 60 ADD A,@R0 70 ADDC A,@R0 41 ORL A,@R1 51 ANL A,@R1 61 ADD A,@R1 71 ADDC A,@R1 42 MOV A,T 52aa JB2 a 62 MOV T,A 72aa JB3 a 43dd ORL A,d 53dd ANL A,d -- - -- - 44aa JMP 2a 54aa CALL 2a 64aa JMP 3a 74aa CALL 3a 45 START CNT 55 STAT T 65 STOP TCNT 75 ENT0 CLK 46aa JNT1 a 56aa JT1 a -- - 76aa JF1 a 47 SWAP A 57 DA A 67 RRC A 77 RR A 48 ORL A,R0 58 ANL A,R0 68 ADD A,R0 78 ADDC A,R0 49 ORL A,R1 59 ANL A,R1 69 ADD A,R1 79 ADDC A,R1 4A ORL A,R2 5A ANL A,R2 6A ADD A,R2 7A ADDC A,R2 4B ORL A,R3 5B ANL A,R3 6B ADD A,R3 7B ADDC A,R3 4C ORL A,R4 5C ANL A,R4 6C ADD A,R4 7C ADDC A,R4 4D ORL A,R5 5D ANL A,R5 6D ADD A,R5 7D ADDC A,R5 4E ORL A,R6 5E ANL A,R6 6E ADD A,R6 7E ADDC A,R6 4F ORL A,R7 5F ANL A,R7 6F ADD A,R7 7F ADDC A,R7 67|77: carry/no-carry reversed relative to both 6x/7x ADD/ADDC and E7/F7 RL/RLC 80 MOVX A,@R0 90 MOVX @R0,A A0 MOV @R0,A B0dd MOV @R0,d 81 MOVX A,@R1 91 MOVX @R1,A A1 MOV @R1,A B1dd MOV @R1,d -- - 92aa JB4 a -- - B2aa JB5 a 83 RET 93 RETR A3 MOVP A,@A B3 JMPP @A 84aa JMP 4a 94aa CALL 4a A4aa JMP 5a B4aa CALL 4a 85 CLR F0 95 CPL F0 A5 CLR F1 B5 CPL F1 86aa JNI a 96aa JNZ a -- - B6aa JF0 a -- - 97 CLR C A7 CPL C -- - 88dd ORL BUS,d 98dd ANL BUS,d A8 MOV R0,A B8dd MOV R0,d 89dd ORL P1,d 99dd ANL P1,d A9 MOV R1,A B9dd MOV R1,d 8Add ORL P2,d 9Add ANL P2,d AA MOV R2,A BAdd MOV R2,d -- - -- - AB MOV R3,A BBdd MOV R3,d 8C ORLD P4,A 9C ANLD P4,A AC MOV R4,A BCdd MOV R4,d 8D ORLD P5,A 9D ANLD P5,A AD MOV R5,A BDdd MOV R5,d 8E ORLD P6,A 9E ANLD P6,A AE MOV R6,A BEdd MOV R6,d 8F ORLD P7,A 9F ANLD P7,A AF MOV R7,A BFdd MOV R7,d 8B|9B: would be port 3, non-existant hardware 96: would actually be position for true test, JNZ better on C6, JZ on unused D6 -- - D0 XRL A,@R0 -- - F0 MOV A,@R0 -- - D1 XRL A,@R1 -- - F1 MOV A,@R1 -- - D2aa JB6 a -- - F2aa JB7 a -- - D3dd XRL A,d E3 MOVP3 A,@A -- - C4aa JMP 6a D4aa CALL 6a E4aa JMP 7a F4aa CALL 7a C5 SEL RB0 D5 SEL RB1 E5 SEL MB0 F5 SEL MB1 C6aa JZ a -- - E6aa JNC a F6aa JC a C7 MOV A,PSW D7 MOV PSW,A E7 RL A F7 RLC A C8 DEC R0 D8 XRL A,R0 E8aa DJNZ R0,a F8 MOV A,R0 C9 DEC R1 D9 XRL A,R1 E9aa DJNZ R1,a F9 MOV A,R1 CA DEC R2 DA XRL A,R2 EAaa DJNZ R2,a FA MOV A,R2 CB DEC R3 DB XRL A,R3 EBaa DJNZ R3,a FB MOV A,R3 CC DEC R4 DC XRL A,R4 ECaa DJNZ R4,a FC MOV A,R4 CD DEC R5 DD XRL A,R5 EDaa DJNZ R5,a FD MOV A,R5 CE DEC R6 DE XRL A,R6 EEaa DJNZ R6,a FE MOV A,R6 CF DEC R7 DF XRL A,R7 EFaa DJNZ R7,a FF MOV A,R7 C0|C1|E0|E1: missing DEC|DJNZ @R0|@R1, why missing? C6: would actually be position for an false test, JNZ, JZ better on unused D6 Instruction Code Table: ----------------------- (only opcodes, in order: ver: bit7..4/3, hor: bit2..0) + 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 NOP - OUTL BU,AADD A, JMP 0a EN I - DEC A INS A,BUSIN A,P1 IN A.P2 - MOVD A,P4MOVD A,P5MOVD A,P6MOVD A,P7 10 INC @R0 INC @R1 JB0 ADDC A, CALL 0a DIS I JTF INC A INC R0 INC R1 INC R2 INC R3 INC R4 INC R5 INC R6 INC R7 20 XCH A,@0 XCH A,@1 - MOV A, JMP 1a EN TCNTI JNT0 CLR A XCH A,R0 XCH A,R1 XCH A,R2 XCH A,R3 XCH A,R4 XCH A,R5 XCH A,R6 XCH A,R7 30 XCHD A,@0XCHD A,@1JB1 - CALL 1a DIS TCNTIJT0 CPL A - OUTL P1,AOUTL P2,A- MOVD P4,AMOVD P5,AMOVD P6,AMOVD P7,A 40 ORL A,@R0ORL A,@R1MOV A,T ORL A, JMP 2a START CNTJNT1 SWAP A ORL A,R0 ORL A,R1 ORL A,R2 ORL A,R3 ORL A,R4 ORL A,R5 ORL A,R6 ORL A,R7 50 ANL A,@R0ANL A,@R1JB2 ANL A, CALL 2a START T JT1 DA A ANL A,R0 ANL A,R1 ANL A,R2 ANL A,R3 ANL A,R4 ANL A,R5 ANL A,R6 ANL A,R7 60 ADD A,@R0ADD A,@R1MOV T,A - JMP 3a STOP TCNT- RRC A ADD A,R0 ADD A,R1 ADD A,R2 ADD A,R3 ADD A,R4 ADD A,R5 ADD A,R6 ADD A,R7 70 ADDC A,@0ADDC A,@1JB3 - CALL 3a ENT0 CLK JF1 RR A ADDC A,R0ADDC A,R1ADDC A,R2ADDC A,R3ADDC A,R4ADDC A,R5ADDC A,R6ADDC A,R7 80 MOVX A,@0MOVX A,@1- RET JMP 4a CLR F0 JNI - ORL BUS, ORL P1, ORL - ORLD P4,AORLD P5,AORLD P6,AORLD P7,A 90 MOVX @0,AMOVX @1,AJB4 RETR CALL 4a CPL F0 JNZ CLR C ANL BUS, ANL P1, ANL - ANLD P4,AANLD P5,AANLD P6,AANLD Pt,A A0 MOV @R0,AMOV @R1,A- MOVP A,@AJMP 5a CLR F1 - CPL C MOV R0,A MOV R1,A MOV R2,A MOV R3,A MOV R4,A MOV R5,A MOV R6,A MOV R7,A B0 MOV @R0, MOV @R1, JB5 JMPP @A CALL 5a CPL F1 JF0 - MOV R0, MOV R1, MOV R2, MOV R3, MOV R4, MOV R5, MOV R6, MOV R7, C0 - - - - JMP 6a SEL RB0 JZ MOV A,PSW DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 D0 XRL A,@R0XRL A,@R1JB6 XRL A, CALL 6a SEL RB1 - MOV PSW,A XRL A,R0 XRL A,R1 XRL A,R2 XRL A,R3 XRL A,R4 XRL A,R5 XRL A,R6 XRL A,R7 E0 - - - MOVP3 A,@JMP 7a SEL MB0 JNC RL A DJNZ R0, DJNZ R1, DJNZ R2, DJNZ R3, DJNZ R4, DJNZ R5, DJNZ R6, DJNZ R7, F0 MOV A,@R0MOV A,@R1JB7 - CALL 7a SEL MB1 JC RLC A MOV A,R0 MOV A,R1 MOV A,R2 MOV A,R3 MOV A,R4 MOV A,R5 MOV A,R6 MOV A,R7