8008 Instruction Set author Neil Franklin, last modification 2008.01.02 Basics: ------- All numbers and bit patterns in this file are usually given in hex, seldom in binary, never in decimal or octal (except assembler operands, all in octal). Sources for this data: ---------------------- 1. PDF with scanned in copy of Intel 8008 Users Manual Rev 4 of Nov 1973, from http://www.bitsavers.org/pdf/intel/MCS8/8008usersManualRev4_Nov73.pdf Very unlikely to contain errors. Of course errors of my own are to be expected. Registers: ---------- (in order: data, address, pc, flags) A 8bit Accumulator B C D E H L 8bit General Purpose Registers M 16bit Register Pair (= H,L merged as high,low) -nameless- 3bit Stack Pointer, selects active PC PC0..PC7 8*16bit Program Counter Stack -nameless- 4bit Control Bits (= flags) Control Bits, Flags: -------------------- (in order: flag select codes: from 00 to 11) C Carry (arithmetic result carry bit7->"bit8") Z Zero (result all bits cleared) S Sign (result bit7 set) P Parity (result parity even) General policy is: - arithmetic: set all CZSP - decrement/increment: set ZSP, leave C unchanged - logic stuff: set all CZSP (with C allways set to 0) - shift/rotate: set only C - load/store/move/in/out: leave all flags unchanged - jump/call/return: leave all flags unchanged Memory: ------- Program+Data memory 16k*8bit (14bit address space) Output devices 3/4*32*8bit (5bit address space) Output+Input devices 1/4*32*8bit (5bit address space) Addressing Modes, in Assembler Syntax: -------------------------------------- (in order: reg, immediate, reg indirect, pc) A accumulator B C D E H L register I bbb immediate8 (3 octal digits, 8 bits) (I = "immediate mode") M register pair HL indirect (M = "memory register") bbbbbb address14 (6 octal digits, 14 bits) (only JMP/CAL instr) bb address5 (2 octal digits, 5 bits) (only INP/OUT instr) Instruction Formats, in Machine Code Bytes: ------------------------------------------- (in order: simple, immediate, register, in/out, jump+conditional) oo opcode8 oobb opcode8 immediate8 (only LDI instr) or opcode5+reg-address3 orbb opcode5+reg-address3 immediate8 (only Arith *I instr) or opcode2+destreg-address3+sourcereg-address3 oa opcode3+in/out-address5 (only INP/OUT instr) ocbbbb opcode4+condit4 addr-low8 addr-high6 (= little endian) (only JMP/CAL) oa opcode5+address3 (only RST instr) Instruction Bit Patterns and Operations: ---------------------------------------- (in order: functional grouping: arithmetic, data transfer, jumps) arithmetic/logic s0ooosss ..ooo... opcode operation ..000... ADs A = A + source; FlagsCZSP "ADd" ..001... ACs A = A + source + FlagC; FlagsCZSP "Add with Carry" ..010... SUs A = A - source; FlagsCZSP "SUbtract" ..011... SBs A = A - source - FlagC; FlagsCZSP "Subtract with Borrow" ..100... NDs A = A bitwise-AND source; FlagsCZSP,C=0 "aND" ..101... XRs A = A bitwise-excl-OR source; FlagsCZSP,C=0 "eXclusive oR" ..110... ORs A = A bitwise-OR source; FlagsCZSP,C=0 "OR" ..111... CPs FlagsCZSP = A - source "ComPare" s....sss s = source 1....000 A 1....001 B 1....010 C 1....011 D 1....100 E 1....101 H 1....110 L 1....111 M = mem[H,L] 0....100 I = mem[PC+] (immediate8) increment/decrement 00ddd00o .......o opcode operation .......0 INd dest = dest + 1; FlagsZSP "INcrement" .......1 DCd dest = dest - 1; FlagsZSP "DeCrement" ..ddd... d = destination ..000... - (not with A (HLT is there!)) ..001... B ..010... C ..011... D ..100... E ..101... H ..110... L ..111... - (not with M (read-update-write memory access not implemented)) shift/rotate 000oo010 ...oo... opcode operation ...00... RLC A = A(bit6..0,7); FlagC=A(bit7) "Rotate Left around Carry" ...01... RRC A = A(bit0,7..1); FlagC=A(bit0) "Rotate Right around Carry" ...10... RAL FlagC,A = A,FlagC "Rotate Accumulator Left" ...11... RAR A,FlagC = FlagC,A "Rotate Accumulaor Right" register/load/store ssdddsss opcode operation Lds destination = source "LoaD" ..ddd... d = destination ..000... A ..001... B ..010... C ..011... D ..100... E ..101... H ..110... L ..111... M = mem[H,L] 11...sss d = source 11...000 A 11...001 B 11...010 C 11...011 D 11...100 E 11...101 H 11...110 L 11...111 M = mem[H,L] (not together with LM* = LMM (HLT is there!)) 00...110 I = mem[PC+] (immediate8) input and output 11ooaaa1 ..oo.... opcode operation (and first 2 IO address bits) ..00.... INP 0a io[00a] = A ; A = io[00a] "INPut" ..01.... OUT 1a io[01a] = A "OUTput" ..10.... OUT 2a io[02a] = A "OUTput" ..11.... OUT 3a io[03a] = A "OUTput" ....aaa. a = last 3 IO address bits ....000. 0 ....001. 1 ....010. 2 ....011. 3 ....100. 4 ....101. 5 ....110. 6 ....111. 7 jumps/subroutines and reset/interrupt oooooooo opcode operation 0000000x HLT suspend until INT (would be INA and DCA!) "HaLT" 00xxx111 RET PC stack retreat one "RETurn" 01xxx100 JMP bbbbbb PC = mem[PC++] (address14, 6 octal digits) "JuMP" 01xxx110 CAL bbbbbb PC stack advance one PC = mem[PC++] (addr14, 6 octal) "CALl" 11111111 HLT suspend until INT (opcode would be LMM!) "HaLT" oooooooo opcode operation 00aaa101 RST PC stack advance one "ReSTart" PC = 0(bit13..6),aaa(bit5..3),0(bit2..0) ..aaa... number restart address ..000... 000 0000 ..001... 010 0008 ..010... 020 0010 ..011... 030 0018 ..100... 040 0020 ..101... 050 0028 ..110... 060 0030 ..111... 070 0038 ---- pin INT next instruction from extern, usually RST "INTerrupt" in case of reset, PC = 0000 output, so automatic mem(0) branches/conditionals oocccooo oo...ooo opcode operation 00...011 Rcc if condition then PC stack retreat one "Return cc" 01...000 Jcc bbbbbb if condition then PC = mem[PC++] (addr14, 6 octal) "Jump cc" 01...010 Ccc bbbbbb if condition then PC stack advance one; PC = mem[PC++] "Call cc" ..ccc... cc condition ..000... FC C = 0 "False Carry" ..001... FZ Z = 0 "False Zero" ..010... FS S = 0 "False Sign" ..011... FP P = 0 "False Parity" ..100... TC C = 1 "True Carry" ..101... TZ Z = 1 "True Zero" ..110... TS S = 1 "True Sign" ..111... TP P = 1 "True Parity" Instruction Code List: ---------------------- (full machine code bytes, in order: opcode number) 00 HLT 10 INC 20 INE 30 INL 01 HLT 11 DCC 21 DCE 31 DCL 02 RLC 12 RAL -- - -- - 03 RFC 13 RFS 23 RTC 33 RTS 04bb ADI bbb 14bb SUI bbb 24bb NDI bbb 34bb ORI bbb 05 RST 00 15 RST 20 25 RST 40 35 RST 60 06bb LAI bbb 16bb LCI bbb 26bb LEI bbb 36bb LLI bbb 07 RET 17 RET 27 RET 37 RET 08 INB 18 IND 28 INH -- - 09 DCB 19 DCD 29 DCH -- - 0A RRC 1A RAR -- - -- - 0B RFZ 1B RFP 2B RTZ 3B RTP 0Cbb ACI bbb 1Cbb SBI bbb 2Cbb XRI bbb 3Cbb CPI bbb 0D RST 10 1D RST 30 2D RST 50 3D RST 70 0Ebb LBI bbb 1Ebb LDI bbb 2Ebb LHI bbb 3Ebb LMI bbb 0F RET 1F RET 2F RET 3F RET 00|01: would be INA and DCA, but both used for HLT 38|39: would be INM and DCM, but are not implemented (are in 8080) 40bbbb JFC bbbbbb 50bbbb JFS bbbbbb 60bbbb JTC bbbbbb 70bbbb JTS bbbbbb 41 INP 00 51 OUT 10 61 OUT 20 71 OUT 30 42bbbb CFC bbbbbb 52bbbb CFS bbbbbb 62bbbb CTC bbbbbb 72bbbb CTS bbbbbb 43 INP 01 53 OUT 11 63 OUT 21 73 OUT 31 44bbbb JMP bbbbbb 54bbbb JMP bbbbbb 64bbbb JMP bbbbbb 74bbbb JMP bbbbbb 45 INP 02 55 OUT 12 65 OUT 22 75 OUT 32 46bbbb CAL bbbbbb 56bbbb CAL bbbbbb 66bbbb CAL bbbbbb 76bbbb CAL bbbbbb 47 INP 03 57 OUT 13 67 OUT 23 77 OUT 33 48bbbb JFZ bbbbbb 58bbbb JFP bbbbbb 68bbbb JTZ bbbbbb 78bbbb JTP bbbbbb 49 INP 04 59 OUT 14 69 OUT 24 79 OUT 34 4Abbbb CFZ bbbbbb 5Abbbb CFP bbbbbb 6Abbbb CTZ bbbbbb 7Abbbb CTP bbbbbb 4B INP 05 5B OUT 15 6B OUT 25 7B OUT 35 4Cbbbb JMP bbbbbb 5Cbbbb JMP bbbbbb 6Cbbbb JMP bbbbbb 7Cbbbb JMP bbbbbb 4D INP 06 5D OUT 16 6D OUT 26 7D OUT 36 4Ebbbb CAL bbbbbb 5Ebbbb CAL bbbbbb 6Ebbbb CAL bbbbbb 7Ebbbb CAL bbbbbb 4F INP 07 5F OUT 17 6F OUT 27 7F OUT 37 80 ADA 90 SUA A0 NDA B0 ORA 81 ADB 91 SUB A1 NDB B1 ORB 82 ADC 92 SUC A2 NDC B2 ORD 83 ADD 93 SUD A3 NDD B3 ORD 84 ADE 94 SUE A4 NDE B4 ORE 85 ADH 95 SUH A5 NDH B5 ORH 86 ADL 96 SUL A6 NDL B6 ORL 87 ADM 97 SUM A7 NDM B7 ORM 88 ACA 98 SBA A8 XRA B8 CPA 89 ACB 99 SBB A9 XRB B9 CPB 8A ACC 9A SBC AA XRC BA CPC 8B ACD 9B SBD AB XRD BB CPD 8C ACE 9C SBE AC XRE BC CPE 8D ACH 9D SBH AD XRH BD CPH 8E ACL 9E SBL AE XRL BE CPL 8F ACM 9F SBM AF XRM BF CPM C0 LAA D0 LCA E0 LEA F0 LLA C1 LAB D1 LCB E1 LEB F1 LLB C2 LAC D2 LCC E2 LEC F2 LLC C3 LAD D3 LCD E3 LED F3 LLD C4 LAE D4 LCE E4 LEE F4 LLE C5 LAH D5 LCH E5 LEH F5 LLH C6 LAL D6 LCL E6 LEL F6 LLL C7 LAM D7 LCM E7 LEM F7 LLM C8 LBA D8 LDA E8 LHA F8 LMA C9 LBB D9 LDB E9 LHB F9 LMB CA LBC DA LDC EA LHC FA LMC CB LBD DB LDD EB LHD FB LMD CC LBE DC LDE EC LHE FC LME CD LBH DD LDH ED LHH FD LMH CE LBL DE LDL EE LHL FE LML CF LBM DF LDM EF LHM FF HLT C0|C9|D2|DB|E4|ED|F6: are all NOPs, C0 is the official NOP instruction FF: would be LMM (3 cycle NOP), but used for HLT Instruction Code Table: ----------------------- (only opcodes, in order: ver: bit7..6/5..3, hor: bit2..0) + 00 01 02 03 04 05 06 07 00 HLT HLT RLC RFC ADI RST 00 LAI RET 08 INB DCB RRC RFZ ACI RST 10 LBI RET 10 INC DCC RAL RFS SUI RST 20 LCI RET 18 IND DCD RAR RFP SBI RST 30 LDI RET 20 INE DCE - RTC NDI RST 40 LEI RET 28 INH DCH - RTZ XRI RST 50 LHI RET 30 INL DCL - RTS ORI RST 60 LLI RET 38 - - - RTP CPI RST 70 LMI RET 40 JFC INP 00 CFC INP 01 JMP INP 02 CAL INP 03 48 JFZ INP 04 CFZ INP 05 JMP INP 06 CAL INP 07 50 JFS OUT 10 CFS OUT 11 JMP OUT 12 CAL OUT 13 58 JFP OUT 14 CFP OUT 15 JMP OUT 16 CAL OUT 17 60 JTC OUT 20 CTC OUT 21 JMP OUT 22 CAL OUT 23 68 JTZ OUT 24 CTZ OUT 25 JMP OUT 26 CAL OUT 27 70 JTS OUT 30 CTS OUT 31 JMP OUT 32 CAL OUT 33 78 JTP OUT 34 CTP OUT 35 JMP OUT 36 CAL OUT 47 80 ADA ADB ADC ADD ADE ADH ADL ADM 88 ACA ACB ACC ACD ACE ACH ACL ACM 90 SUA SUB SUC SUD SUE SUH SUL SUM 98 SBA SBB SBC SBD SBE SBH SBL SBM A0 NDA NDB NDC NDD NDE NDH NDL NDM A8 XRA XRB XRC XRD XRE XRH XRL XRM B0 ORA ORB ORC ORD ORE ORH ORL ORM B8 CPA CPB CPC CPD CPE CPH CPL CPM C0 LAA LAB LAC LAD LAE LAH LAL LAM C8 LBA LBB LBC LBD LBE LBH LBL LBM D0 LCA LCB LCC LCD LCE LCH LCL LCM D8 LDA LDB LDC LDD LDE LDH LDL LDM E0 LEA LEB LEC LED LEE LEH LEL LEM E8 LHA LHB LHC LHD LHE LHH LHL LHM F0 LLA LLB LLC LLD LLE LLH LLL LLM F8 LMA LMB LMC LMD LME LMH LML HLT translated to newer (= 8080-like) Mnemonics as in later 8008 docs: + 00 01 02 03 04 05 06 07 00 HLT HLT RLC RNC ADI RST 0 MVI A, RET 08 INR B DCR B RRC RNZ ACI RST 1 MVI B, RET 10 INR C DCR C RAL RP SUI RST 2 MVI C, RET 18 INR D DCR D RAR RPO SBI RST 3 MVI D, RET 20 INR E DCR E - RC NDI RST 4 MVI E, RET 28 INR H DCR H - RZ XRI RST 5 MVI H, RET 30 INR L DCR L - RM ORI RST 6 MVI L, RET 38 - - - RPE CPI RST 7 MVI M, RET 40 JNC IN 0 CNC IN 1 JMP IN 2 CALL IN 3 48 JNZ IN 4 CNZ IN 5 JMP IN 6 CALL IN 7 50 JP OUT 8 CP OUT 9 JMP OUT 10 CALL OUT 11 58 JPO OUT 12 CPO OUT 13 JMP OUT 14 CALL OUT 15 60 JC OUT 16 CC OUT 17 JMP OUT 18 CALL OUT 19 68 JZ OUT 20 CZ OUT 21 JMP OUT 22 CALL OUT 23 70 JM OUT 24 CM OUT 25 JMP OUT 26 CALL OUT 27 78 JPE OUT 28 CPE OUT 29 JMP OUT 30 CALL OUT 31 80 ADD A ADD B ADD C ADD D ADD E ADD H ADD L ADD M 88 ADC A ADC B ADC C ADC D ADC E ADC H ADC L ADC M 90 SUB A SUB B SUB C SUB D SUB E SUB H SUB L SUB M 98 SBB A SBB B SBB C SBB D SBB E SBB H SBB L SBB M A0 ANA A ANA B ANA C ANA D ANA E ANA H ANA L ANA M A8 XRA A XRA B XRA C XRA D XRA E XRA H XRA L XRA M B0 ORA A ORA B ORA C ORA D ORA E ORA H ORA L ORA M B8 CMP A CMP B CMP C CMP D CMP E CMP H CMP L CMP M C0 MOV A,A MOV A,B MOV A,C MOV A,D MOV A,E MOV A,H MOV A,L MOV A,M C8 MOV B,A MOV B,B MOV B,C MOV B,D MOV B,E MOV B,H MOV B,L MOV B,M D0 MOV C,A MOV C,B MOV C,C MOV C,D MOV C,E MOV C,H MOV C,L MOV C,M D8 MOV D,A MOV D,B MOV D,C MOV D,D MOV D,E MOV D,H MOV D,L MOV D,M E0 MOV E,A MOV E,B MOV E,C MOV E,D MOV E,E MOV E,H MOV E,L MOV E,M E8 MOV H,A MOV H,B MOV H,C MOV H,D HOV H,E MOV H,H MOV H,L MOV H,M F0 MOV L,A MOV L,B MOV L,C MOV L,D MOV L,E MOV L,H MOV L,L MOV L,M F8 MOV M,A MOV M,B MOV M,C MOV M,D MOV M,E MOV M,H MOV M,L HLT