6809 Instruction Set author Neil Franklin, last modification 2008.01.09 Basics: ------- All numbers and bit patterns in this file are usually given in hex, seldom in binary, never in decimal or octal. Sources for this data: ---------------------- 1. Centerfold 2-page table of instruction mnemonics and opcodes and byte lengths and flags (but no postbyte formats), published in german "mc" (micro computer) magazine 1/1982 edition. Used that for programming an Dragon 32 (first computer I owned, second I programmed), so it can be assumed to be correct. But one error found: in BGT/BLE flag C should be Z. 2. Reprint of official Motorola 6809E instruction table, as appendix in an book containing an in depth description of the 6809E based Dragon 32 and 64 computers. Very unlikely to contain errors (but actually found what seems to be one, as it contradicts itsself, see ASR instruction NOTE:). Of course errors of my own are to be expected. Registers: ---------- (in order: data, address, pc, flags) A 8bit Accumulator B 8bit Accumulator D 16bit Double Accumulator (= A,B merged as high,low) DP 8bit Direct Page Register (for DP,8bit merged as high,low address) X Y 16bit Index Registers S 16bit System Stack Pointer (push pre-decr, pull post-incr) U 16bit User Stack Pointer (") PC 16bit Program Counter CC 8bit Condition Code Register (= flags) Condition Code Register, Flags: ------------------------------- (in order: from MSB/7 to LSB/0) E Entire State on Stack (1 after IRQ and NMI, 0 after FIRQ) F FIRQ Interrupt Mask (1 diables FIRQ) H Half Carry (arithmetic result carry bit3->bit4, used only for DAA) I IRQ Interrupt Mask (1 diables IRQ) N Negative (result bit7 set) Z Zero (result all bits cleared) V oVerflow (arithmetic result carry bit6->bit7) C Carry (arithmetic result carry bit7->"bit8") General policy seems to be: - 8bit arithmetic: set all HNZVC (addition correct H, subtraction undefined H) - 16bit arithmetic: set NZVC (no H as no 16bit DAA?) - decrement/increment: set NZV, leave C unchanged, so address inc/dec leaves C - logic stuff and load and store(!): set NZV (with allways V=0) - shift/rotate left: set NZVC - shift/rotate right: set only NZC (no V as not using carry chain?) - clear: set NZVC - jump/branch/call/return: leave all flags unchanged Memory: ------- Program+Data memory 64k*8bit (16bit address space) (I/O uses part of above, memory mapped I/O (section of address space)) Addressing Modes, in Assembler Syntax: -------------------------------------- (in order: reg, immediate, address, reg indirect, reg indexed, pc, mem indir) A accumulator A B accumulator B D double accumulator (= A+B merged) X Y index register U S stack register #ii immediate8 (2 hex digits) #iiii immediate16 (4 hex digits) dd direct-address8 (using DP reg and dd, gives DP,dd) (2 hex digits) hhll extended-address16 (4 hex digits) ,R register indirect (where R=X|X|U|S) n,R register indirect + offset5 (1.25 hex digits) nn,R register indirect + offset8 (2 hex digits) nnnn,R register indirect + offset16 (4 hex digits) A,R register indirect + register A offset B,R register indirect + register B offset D,R register indirect + register D offset ,R+ register indirect post autoinc 1 (no mem indir, needs 2 bytes) ,R++ register indirect post autoinc 2 ,-R register indirect pre autodec 1 (no mem indir, needs 2 bytes) ,--R register indirect pre autodec 2 -nameless- stack pointer indirect decrement/increment (only PSH*/PUL* instr) nn PC + offset8 (-128..+127) (only B*/LB* instr) nnnn PC + offset16 (only B*/LB* instr) nn,PCR PC register indirect + offset8 (2 hex digits) nnnn,PCR PC register indirect + offset16 (4 hex digits) [,hhll] memory indirect (4 hex digits) [,*R*] all above register indir (exept: n,R ,R+ ,-R) and then 2nd mem ind Instruction Formats, in Machine Code Bytes: ------------------------------------------- (in order: simple, immediate, register, memory, postbyte, jump, condit, prefix) oo opcode8 ooii opcode8 immediate8 ooiiii opcode8 immediate-high8 immediate-low8 (= big endian) oods opcode8 destreg-address4+sourcereg-address4 (only EXG/TFR instr) oobb opcode8 reg-select-bitfield8 (only PSH*/PUL* instr) oodd opcode8 address8 oohhll opcode8 address-high8 address-low8 (= big endian) oopp opcode8 postbyte-mode6+reg-addr2 (w/o offset or w reg offset) oopn opcode8 postbyte-mode1+reg-addr2+offset5 ooppnn opcode8 postbyte-mode6+reg-addr2 offset8 ooppnnnn opcode8 postbyte-mode6+reg-addr2 offset-high8 offs-low8 (= big endian) ocnn opcode4-condition4 offset8 (only BRA/BRcc instr) 10** prefix-regswitch-or-longbranch8 above... 10ocnnnn prefix-rs-or-lb8 op4-cond4 of-high8 of-low8 (= big endian) (only LBR*) 11** prefix-regswitch8 above... Instruction Bit Patterns and Operations: ---------------------------------------- (in order: by functional grouping: arithmetic, data transfer, jumps, auxillary) arithmetic/logic and load/store 8bit 1ammoooo ....oooo opcode operation ....0000 SUBa a = a - mem[address]; FlagsHNZVC,H=? "SUBtract" ....0001 CMPa FlagsNZVC = a - mem[address]; FlagH=? "CoMPare" ....0010 SBCa a = a - mem[address] - FlagC; FlagsHNZV,H=? "SuBtract w C" ....0100 ANDa a = a bitwise-AND mem[address]; FlagsNZV,V=0 "AND" ....0101 BITa FlagsNZ = a bitwise-AND mem[address]; FlagV=0 "BIt Test" ....0110 LDa a = mem[address]; FlagsNZV,V=0 "LoaD" ....0111 STa mem[address] = a; FlagsNZV,V=0 "STore" ....1000 EORa a = a bitwise-excl-OR mem[address]; FlagsNZV,V=0 "Excl OR" ....1001 ADCa a = a + mem[address] + FlagC; FlagsHNZV "ADd w Carry" ....1010 ORa a = a bitwise-OR mem[address]; FlagsNZV,V=0 "OR" ....1011 ADDa a = a + mem[address]; FlagsHNZVC "Add" .a...... a source/target accumulator .0...... A A .1...... B B ..mm.... mode address ..00.... #ii PC+ (immediate8) (not with STa, modifying immediate is senseless) ..01.... dd DP,mem[PC+] (address8) ..10.... pp -postbyte-address- ..11.... hhll mem[PC++] (address16) arithmetic and load/store 16bit 1ommoooo .o..oooo opcode operation .0..0011 SUBD D = D - mem[address]; FlagsNZVC "SUBtract from D" with prefix 00010000 SUBD -> CMPD "CoMPare with D" with prefix 00010001 SUBD -> CMPU "CoMPare with U" .0..1100 CMPX FlagsNZVC = X - mem[address] "CoMPare with X" with prefix 00010000 CMPX -> CMPY "CoMPare with Y" with prefix 00010001 CMPX -> CMPS "CoMPare with S" .0..1110 LDX X = mem[address]; FlagsNZV,V=0 "LoaD register X" with prefix 00010000 LDX -> LDY "LoaD register Y" .0..1111 STX mem[address] = X; FlagsNZV,V=0 "STore register X" with prefix 00010000 STX -> STY "STore register Y" .1..0011 ADDD D = D + mem[address]; FlagsNZVC "ADD to D" .1..1100 LDD D = mem[address]; FlagsNZV,V=0 "LoaD register D" .1..1101 STD mem[address] = D; FlagsNZV,V=0 "STore register D" .1..1110 LDU U = mem[address]; FlagsNZV,V=0 "LoaD register U" with prefix 00010000 LDU -> LDS "LoaD register S" .1..1111 STU mem[address] = U; FlagsNZV,V=0 "STore register U" with prefix 00010000 STU -> STS "STore register S" ..mm.... mode address ..00.... #iiii PC++ (immediate16) (not with ST*, modifying immed is senseless) ..01.... dd DP,mem[PC+] (address8) ..10.... pp -postbyte-address- ..11.... hhll mem[PC++] (address16) negate/complement and shift/rotate and increment/decrement and test/clear 0mmmoooo ....oooo opcode operation ....0000 NEGm mem[address] = 0 - mem[address]; FlagsHNZVC,H=? "NEGate" ....0011 COMm mem[address] = bitwise-NOT mem[address]; FlagsNZVC,V=0,C=1 "COMplement" ....0100 LSRm mem[address],FlagC = 0,mem[address]; FlagsNZ(noV!),N=0 "Logical Shift Right" ....0110 RORm mem[address],FlagC = FlagC,mem[address]; FlagsNZ(noV!) "ROtate Right" ....0111 ASRm mem[address],FlagC = mem(bit7),mem[address]; FlagsNZC(noV!) NOTE: official Motorola 6809E instruction table claims that ASR and ASL leave flag H undefined, but that LSL (is ASL!) and LSR do not change H, docu bug? "Arithmetic Shift Right" ....1000 ASLm FlagC,mem[address] = mem[address],0; FlagsNZV "Arithmetic Shift Left" = LSLm additional name for ASLm "Logical Shift Left" ....1001 ROLm FlagC,mem[address] = mem[address],FlagC; FlagsNZV "ROtate Left" ....1010 DECm mem[address] = mem[address] - 1; FlagsNZV(noC!) "DECrement" ....1100 INCm mem[address] = mem[address] + 1; FlagsNZV(noC!) "INCrement" ....1101 TSTm FlagsNZ = mem[address] - 0; FlagV=0 "TeST" ....1111 CLRm mem[address] = 0; FlagsNZVC,N=0,Z=1,V=0,C=0 "CLeaR" .000.... m mode address .000.... nothing dd DP,mem[PC+] (address8) .100.... A A A instead of mem[address] .101.... B B B instead of mem[address] .110.... nothing pp -postbyte-address- .111.... nothing hhll mem[PC++] (address16) indexed address calculation 000100oo ......oo opcode operation ......00 LEAX X = -postbyte-address-; FlagZ "Load Effective Address to X" ......01 LEAY Y = -postbyte-address-; FlagZ "Load Effective Address to Y" ......02 LEAS S = -postbyte-address- "Load Effective Address to S" ......03 LEAU U = -postbyte-address- "Load Effective Address to U" other specialised arithmetic oooooooo opcode operation 00011001 DAA if A(bit3..0) > 9 or FlagH then A = A + 6; FlagC if A(bit7..4) > 9 or FlagC then A = A + 96; FlagsNZVC,V=0 "Decimal Adjust Accumulator" 00011101 SEX A(bit7..0) = B(bit7); FlagsNZV,V=0 "Sign EXtend" 00111010 ABX X = X + 0(bit15..8),B(bit7..0) "Add Acc B to reg X" 00111101 MUL D = A * B; FlagsZC,C=bit7-for-rounding "MULtiply" register 8bit and 16bit 0001111o ddddssss .......o ........ opcode operation .......0 ........ EXG reg d <=> reg s "EXchanGe" .......1 ........ TFR reg d = reg s "TransFeR" ........ 0ddd.... destination register for 16bit ........ 0000.... D ........ 0001.... X ........ 0010.... Y ........ 0011.... U ........ 0100.... S ........ 0101.... PC ........ 1ddd.... destination register for 8bit ........ 1000.... A ........ 1001.... B ........ 1010.... CC ........ 1011.... DP ........ ....ssss source register (identical as for dddd) stack push/pull 000101sd bbbbbbbb .......d ........ opcode operation (push pre-decr, pull post-incr) .......0 ........ PSHs mem[-s] = regs "PUSh" .......1 ........ PULs regs = mem[s+] "PULl" ......s. ........ s stack ......0. ........ S S ......1. ........ U U ........ bbbbbbbb register bitfield (can combine, PSH* PC->CC, PUL* CC->PC) ........ 10000000 PC (pull PC last gives return from subroutine for free) ........ 01000000 U (if stack S) or S (if stack U) ........ 00100000 Y ........ 00010000 X ........ 00001000 DP ........ 00000100 B ........ 00000010 A ........ 00000001 CC ........ 11111111 everything jumps/subroutines and reset/interrupts oooooooo opcode operation 00001110 JMP dd PC = DP,mem[PC+] (address8) "JuMP" 01101110 JMP hhll PC = mem[PC++] (address16) "JuMP" 01111110 JMP pp PC = -postbyte-address- "JuMP" 00010010 NOP do nothing "No OPeration" 00010011 SYNC wait until any interrupt; run that interrupt if non-masked; then allways continue code "SYNChronise" 00010110 LBRA nnnn PC = PC+mem[PC++] (offset16) "Long BRanch" 00010111 LBSR nnnn mem[--S] = PC PC = PC+mem[PC++] (offset16) "Long Branch SubRoutine" 00111001 RTS PC = mem[S++] "ReTurn from Subroutine" 00111011 RTI CC = mem[S++] if FlagE=1 then rest = mem[S++] PC = mem[S++] "ReTurn from Interrupt" 00111111 SWI mem[--S] = PC,rest,CC; FlagF=1; FlagI=1 PC = mem[FFFA/FFFB] "SoftWare Interrupt" with prefix 00010000 SWI -> SWI2 mem[--S] = PC,rest,CC; (no flags!) PC = mem[FFF4/FFF5] "SoftWare Interrupt 2" with prefix 00010001 SWI -> SWI3 mem[--S] = PC,rest,CC; (no flags!) PC = mem[FFF2/FFF3] "SoftWare Interrupt 3" 10001101 BSR nn mem[--S] = PC; "Branch SubRoutine" PC = PC+mem[PC+] (offset8) 10011101 JSR dd mem[--S] = PC; "Jump SubRoutine" PC = DP,mem[PC+] (address8) 10101101 JSR hhll mem[--S] = PC; "Jump SubRoutine" PC = mem[PC++] (address16) 10111101 JSR pp mem[--S] = PC; "Jump SubRoutine" PC = -postbyte-address- ---- pin RESET FlagF=1; FlagI=1; PC = mem[FFFE/FFFF] "RESET" ---- pin NMI mem[--S] = PC,rest,CC; FlagE=1; FlagF=1; FlagI=1 PC = mem[FFFC/FFFD] "Non Maskable Interrupt" ---- pin IRQ mem[--S] = PC,rest,CC; FlagE=1; FlagI=1 PC = mem[FFF8/FFF9] "Interupt ReQuest" ---- pin FIRQ mem[--S] = PC,CC; FlagE=0; FlagF=1; FlagI=1 PC = mem[FFF6/FFF7] "Fast Interrupt ReQuest" branches/conditionals oooocccc oooo.... opcode operation 0010.... Bcc nn if condition then PC = PC+mem[PC+] (offset8) "Branch cc" with prefix 00010000 Bcc nn -> LBcc nnnn if condition then PC = PC+mem[PC++] (offset16) "Long Branch cc" ....cccc cc condition ....0000 RA 0 = 0 (= unconditional jump relative) "BRanch Allways" ....0001 RN 0 = 1 (= NOP) "BRanch Never" ....0010 HI Z OR C = 0 "HIgher" ....0011 LS Z OR C = 1 "Lower or Same" ....0100 CC C = 0 "Carry Clear" = HS additional name for CC "Higher or Same" ....0101 CS C = 1 "Carry Set" = LO additional name for CS "LOwer" ....0110 NE Z = 0 "Not Equal" ....0111 EQ Z = 1 "Equal" ....1000 VC V = 0 "oVerflow Clear" ....1001 VS V = 1 "oVerflow Set" ....1010 PL N = 0 "PLus" ....1011 MI N = 1 "MInus" ....1100 GE N XOR V = 0 "Greater or Equal" ....1101 LT N XOR V = 1 "Less Than" ....1110 GT Z OR (N XOR V) = 0 "Greater Than" ....1111 LE Z OR (N XOR V) = 1 "Less or Equal" flags oooooooo opcode operation 00011010 ORCC CC = CC bitwise-OR immediate "OR (set) Condition Code" see flags section at top for immediate byte bit pattern 00011100 ANDCC CC = CC bitwise-AND immediate "AND (clear) Condition Code" 00111100 CWAI CC = CC bitwise-AND immediate mem[--S] = PC,rest,CC (as if for SWI or NMI) wait for non-masked interrupt; run that continue code "Clear condition code and WAIt" Indexed Adressing Postbyte Bit Patterns and Operations: ------------------------------------------------------- 0bbooooo .bb..... base register R .00..... X .01..... Y .10..... U .11..... S ...ooooo offset address ...nnnnn n,R R+pp(bit4..0) (offset5) 1bbimmmm .bb..... base register (insert as R below) .00..... X .01..... Y .10..... U .11..... S ...i.... indirect final-address is: ...0.... * below intermediate-address ...1.... [*] mem[below intermediate-address] (address16) ....mmmm mode intermediate-address is: ...00000 ,R+ R (post autoinc 1) (no memory indirect, that needs 2 bytes) ....0001 ,R++ R (post autoinc 2) ...00010 ,-R R (pre autodec 1) (no memory indirect, that needs 2 bytes) ....0011 ,--R R (pre autodec 2) ....0100 ,R R ....0101 B,R R+B ....0110 A,R R+A ....1000 nn,R R+mem[PC+] (offset8) ....1001 nnnn,R R+mem[PC++] (offset16) ....1011 D,R R+D .xx.1100 nn,PCR PC+mem[PC+] (offset8) (xx = don't care, R ignored, allways PC used instead) .xx.1101 nnnn,PCR PC+mem[PC++] (offset16) (xx = don't care, R ignored, allways PC used instead) ...11111 [hhll] mem[PC++] (address16) (no direct, as that is already an non-postbyte mode) Instruction Code List: ---------------------- (full machine code bytes, in order: opcode number) 00dd NEG dd 10** prefix10 20nn BRA nn 30pp* LEAX * -- - 11** prefix11 21nn BRN nn 31pp* LEAY * -- - 12 NOP 22nn BHI nn 32pp* LEAS * 03dd COM dd 13 SYNC 23nn BLS nn 33pp* LEAU * 04dd LSR dd -- - 24nn BCC nn 34bb PSHS bb -- - -- - 25nn BCS nn 35bb PULS bb 06dd ROR dd 16nnnn LBRA nnnn 26nn BNE nn 36bb PSHU bb 07dd ASR dd 17nnnn LBSR nnnn 27nn BEQ nn 37bb PULU bb 08dd ASL dd -- - 28nn BVC nn -- - 09dd ROL dd 19 DAA 29nn BVS nn 39 RTS 0Add DEC dd 1Aii ORCC #ii 2Ann BPL nn 3A ABX -- - -- - 2Bnn BMI nn 3B RTI 0Cdd INC dd 1Cii ANDCC #ii 2Cnn BGE nn 3Cii CWAI #ii 0Ddd TST dd 1D SEX 2Dnn BLT nn 3D MUL 0Edd JMP dd 1Eds EXG ds 2Enn BGT nn -- - 0Fdd CLR dd 1Fds TFR ds 2Fnn BLE nn 3F SWI 10**: prefix10, converts SUBD->CMPD, CMPX->CMPY, LDX->LDY, STX->STY LDU->LDS, STU->STS, B*->LB*, SWI->SWI2 11**: prefix11, converts SUBD->CMPU, CMPX->CMPS, SWI->SWI3 24|25: identical operation also opcodes BHS|BLO, fitting with BHI|BLS 30-37pp*: postbyte, *=0..2 additional offset bytes, depending on address mode 40 NEGA 50 NEGB 60pp* NEG * 70hhll NEG hhll -- - -- - -- - -- - -- - -- - -- - -- - 43 COMA 53 COMB 63pp* COM * 73hhll COM hhll 44 LSRA 54 LSRB 64pp* LSR * 74hhll LSR hhll -- - -- - -- - -- - 46 RORA 56 RORB 66pp* ROR * 76hhll ROR hhll 47 ASRA 57 ASRB 67pp* ASR * 77hhll ASR hhll 48 ASLA 58 ASLB 68pp* ASL * 78hhll ASL hhll 49 ROLA 59 ROLB 69pp* ROL * 79hhll ROL hhll 4A DECA 5A DECB 6App* DEC * 7Ahhll DEC hhll -- -- - -- - -- - 4C INCA 5C INCB 6Cpp* INC * 7Chhll INC hhll 4D TSTA 5D TSTB 6Dpp* TST * 7Dhhll TST hhll -- -- 5E -- 6Epp* JMP * 7Ehhll JMP hhll 4F CLRA 5F CLRB 6Fpp* CLR * 7Fhhll CLR hhll 4E|5E: would be JMP A|B ; jumping to register is impossible, so no opcode 60-6Fpp*: postbyte, same as 30-37pp* 80ii SUBA #ii 90dd SUBA dd A0pp* SUBA * B0hhll SUBA hhll 81ii CMPA #ii 91dd CMPA dd A1pp* CMPA * B1hhll CMPA hhll 82ii SBCA #ii 92dd SBCA dd A2pp* SBCA * B2hhll SBCA hhll 83iiii SUBD #iiii 93dd SUBD dd A3pp* SUBD * B3hhll SUBD hhll 84ii ANDA #ii 94dd ANDA dd A4pp* ANDA * B4hhll ANDA hhll 85ii BITA #ii 95dd BITA dd A5pp* BITA * B5hhll BITA hhll 86ii LDA #ii 96dd LDA dd A6pp* LDA * B6hhll LDA hhll -- - 97dd STA dd A7pp* STA * B7hhll STA hhll 88ii EORA #ii 98dd EORA dd A8pp* EORA * B8hhll EORA hhll 89ii ADCA #ii 99dd ADCA dd A9pp* ADCA * B9hhll ADCA hhll 8Aii ORA #ii 9Add ORA dd AApp* ORA * BAhhll ORA hhll 8Bii ADDA #ii 9Bdd ADDA dd ABpp* ADDA * BBhhll ADDA hhll 8Cii CMPX #iiii 9Cdd CMPX dd ACpp* CMPX * BChhll CMPX hhll 8Dnn BSR nn 9Ddd JSR dd ADpp* JSR * BDhhll JSR hhll 8Eii LDX #iiii 9Edd LDX dd AEpp* LDX * BEhhll LDX hhll -- - 9Fdd STX dd AFpp* STX * BFhhll STX hhll 87: would be STA #ii ; modifying immediate is senseless, so no opcode 8F: would be STX #iiii ; same as for 87 A0-AFpp*: postbyte, same as 30-37pp* C0ii SUBB #ii D0dd SUBB dd E0pp* SUBB * F0hhll SUBB hhll C1ii CMPB #ii D1dd CMPB dd E1pp* CMPB * F1hhll CMPB hhll C2ii SBCB #ii D2dd SBCB dd E2pp* SBCB * F2hhll SBCB hhll C3iiii ADDD #iiii D3dd ADDD dd E3pp* ADDD * F3hhll ADDD hhll C4ii ANDB #ii D4dd ANDB dd E4pp* ANDB * F4hhll ANDB hhll C5ii BITB #ii D5dd BITB dd E5pp* BITB * F5hhll BITB hhll C6ii LDB #ii D6dd LDB dd E6pp* LDB * F6hhll LDB hhll -- - D7dd STB dd E7pp* STB * F7hhll STB hhll C8ii EORB #ii D8dd EORB dd E8pp* EORB * F8hhll EORB hhll C9ii ADCB #ii D9dd ADCB dd E9pp* ADCB * F9hhll ADCB hhll CAii ORB #ii DAdd ORB dd EApp* ORB * FAhhll ORB hhll CBii ADDB #ii DBdd ADDB dd EBpp* ADDB * FBhhll ADDB hhll CCiiii LDD #iiii DCdd LDD dd ECpp* LDD * FChhll LDD hhll -- - DDdd STD dd EDpp* STD * FDhhll STD hhll CEiiii LDU #iiii DEdd LDU dd EEpp* LDU * FEhhll LDU hhll -- - DFdd STU dd EFpp* STU * FFhhll STU hhll C7: would be STB #ii ; modifying immediate is senseless, so no opcode CD|CF: would be STD|STU #iiii ; same as for C7 E0-EFpp*: postbyte, same as 30-37pp* Instruction Code Table: ----------------------- (only opcodes, in order: ver: bit7..4/3, hor: bit2..0) + 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 NEG - - COM LSR - ROR ASR ASL ROL DEC - INC TST JMP CLR 10 prefix10 prefix11 NOP SYNC - - LBRA LBSR - DAA ORCC # - ANDC # SEX EXG TFR 20 BRA BRN BHI BLS BCC BCS BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE 30 LEAX LEAY LEAS LEAU PSHS PULS PSHU PULU - RTS ABX RTI CWAI # MUL - SWI 40 NEGA - - COMA LSRA - RORA ASRA ASLA ROLA DECA - INCA TSTA - CLRA 50 NEGB - - COMB LSRB - RORB ASRB ASLB ROLB DECB - INCB TSTB - CLRB 60 NEG - - COM LSR - ROR ASR ASL ROL DEC - INC TST JMP CLR 70 NEG - - COM LSR - ROR ASR ASL ROL DEC - INC TST JMP CLR 80 SUBA # CMPA # SBCA # SUBD # ANDA # BITA # LDA # - EORA # ADCA # ORA # ADDA # CMPX # BSR LDX # - 90 SUBA CMPA SBCA SUBD ANDA BITA LDA STA EORA ADCA ORA ADDA CMPX JSR LDX STX A0 SUBA CMPA SBCA SUBD ANDA BITA LDA STA EORA ADCA ORA ADDA CMPX JSR LDX STX B0 SUBA CMPA SBCA SUBD ANDA BITA LDA STA EORA ADCA ORA ADDA CMPX JSR LDX STX C0 SUBB # CMPB # SBCB # ADDD # ANDB # BITB # LDB # - EORB # ADCB # ORB # ADDB # LDD # - LDU # - D0 SUBB CMPB SBCB ADDD ANDB BITB LDB STB EORB ADCB ORB ADDB LDD STD LDU STU E0 SUBB CMPB SBCB ADDD ANDB BITB LDB STB EORB ADCB ORB ADDB LDD STD LDU STU F0 SUBB CMPB SBCB ADDD ANDB BITB LDB STB EORB ADCB ORB ADDB LDD STD LDU STU